KR101183640B1 - Method for forming contact plug in semiconductor device - Google Patents

Abstract

The present invention is to provide a method for forming a contact plug of a semiconductor device which can prevent the landing plug contact and the gate pattern from being short-circuited when forming the landing plug contact to which the self-aligned contact process is applied. Preparing a substrate on which a pattern is formed, forming an SOC film on the entire structure including the gate pattern, forming an SOC film pattern to etch the SOC film to fill the gate pattern, and to form the SOC film pattern. Forming an interlayer insulating film on the entire structure including the stepped layer, etching the interlayer insulating film to expose the upper surface of the SOC pattern, and removing the exposed SOC pattern to form a contact hole between the gate pattern. And forming a contact plug in which the contact hole is embedded. It provides a method for forming the contact plug party.

Semiconductor devices, self-alignment, landing plug contacts, SOC films, patterning

Description

TECHNICAL FOR FORMING CONTACT PLUG IN SEMICONDUCTOR DEVICE

1A to 1E are cross-sectional views illustrating a method of forming a landing plug contact applying a self-aligned contact process according to the related art.

2A to 2F are cross-sectional views illustrating a method for forming a landing plug contact to which a self-aligned contact process according to an exemplary embodiment of the present invention is applied.

Description of the Related Art

110 semiconductor substrate 111 gate insulating film

112: gate electrode layer 113: gate capping film

115: gate pattern 116: spacer

117 SOC film 117A SOC film pattern

118: hard mask pattern 119: interlayer insulating film

120: etch back process 121: landing plug contact hole

123: Landing plug contact

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming a landing plug contact of a semiconductor device of 80 nm or less by applying a self aligned contact (SAC) process.

Due to the miniaturization of the pattern due to the high integration of the semiconductor device, various elements of the semiconductor device have a stacked structure. Accordingly, contact plugs were formed to connect upper and lower parts of the stacked elements. Recently, in forming such a contact plug, for example, a landing plug contact (LPC) which forms a lower area of the contact plug with a minimum area and a larger area than the lower area in order to increase the process margin for subsequent processes. contact) technology is being used.

However, the landing plug contact technology has difficulty in etching between structures having a high aspect ratio, and a landing plug contact technology using a self aligned contact (SAC) process has been introduced.

1A to 1E are cross-sectional views illustrating a method for forming a landing plug contact applying a self-aligned contact process according to the related art.

First, as shown in FIG. 1A, a gate insulating layer 11, a gate electrode layer 12, and a gate capping layer 13 are formed on a semiconductor substrate 10 on which an isolation layer (not shown), a well (not shown), and the like are formed. The gate pattern 15 of this laminated structure is formed. In this case, the gate insulating layer 11 is formed of a conventional oxide film-based material such as a silicon oxide film, and the gate electrode layer 12 is typically made of any one of polysilicon, W, WN, and WSi _X (where _X is 1 to 10). Or a combination thereof.

In addition, the gate capping layer 13 is to protect the gate electrode layer 12 during subsequent landing plug contact hole formation, and uses a nitride layer-based material such as silicon nitride (SiN) or silicon oxynitride (SiON).

Subsequently, a source / drain region (not shown) is formed in the substrate 10 between the neighboring gate patterns 15, and then spacers 16 are formed on both sidewalls of the gate pattern 15. Thereafter, the photoresist 17 is coated on the entire upper surface of the substrate 10 including the gate pattern 15.

Subsequently, as illustrated in FIG. 1B, the photoresist pattern 17A is formed by performing exposure and development processes. In this case, the photoresist pattern 17A is formed to cover the landing plug contact predetermined region where the landing plug contact is to be formed.

Subsequently, as shown in FIG. 1C, after the interlayer insulating film 19 is deposited on the entire upper surface of the substrate 10 including the photoresist pattern 17A, the etch back (the back surface of the photoresist pattern 17A is exposed). The interlayer insulating film 19 is etched by performing an etchback process. The interlayer insulating film 19 is made of an oxide film.

Subsequently, as shown in FIG. 1D, a strip process is performed to remove the photoresist pattern 17A. As a result, the landing plug contact hole 20 is formed in the landing plug contact scheduled region.

Subsequently, as shown in FIG. 1E, a landing plug contact 21 for filling the landing plug contact hole 20 is formed. For example, after the contact material is deposited on the interlayer insulating layer 19 to fill the landing plug contact hole 20, the landing plug contact 21 is formed by planarizing the contact material.

However, according to the related art, there are various difficulties in forming the landing plug contact 21 in the gate pattern 15 by self-alignment.

First, in order to perform the exposure process for forming the photoresist pattern 17A, the upper surface of the photoresist 17 must be flat. To obtain such a flat surface, the thickness of the photoresist 17 must be secured to some extent. However, as the inter-pattern size of the semiconductor device gradually becoming higher is reduced, the thickness of the photoresist 17 is also reduced, so that it is almost impossible to obtain the photoresist 17 having a flat top surface. In particular, it is more impossible when using ArF photoresist.

Second, even if the upper surface of the photoresist 17 itself is completely flat, the photoresist 17 is applied with non-uniform thickness due to the topology of the gate pattern 15 as the lower structure, so that normal photoresist patterning is performed. it's difficult. This problem becomes more serious as the size between patterns decreases.

Third, since the oxide film is deposited on the photoresist pattern 17A, the photoresist pattern 17A is affected by the deposition temperature of the oxide film. Therefore, there is a restriction that only an oxide film having a low deposition temperature should be used.

As a result, according to the related art, it is difficult to form the photoresist pattern 17A for defining the landing plug contact area between the neighboring gate patterns 15 due to the above-described difficulty, so that the landing plug contact 21 and the gate pattern ( The problem arises that 15) are shorted with each other.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and a method of forming a contact plug of a semiconductor device capable of preventing a shorting of the landing plug contact and the gate pattern when forming a landing plug contact to which a self-aligned contact process is applied. To provide that purpose.

According to an aspect of the present invention, there is provided a method including preparing a substrate having a plurality of gate patterns, forming an SOC film on an entire structure including the gate pattern, and etching the SOC film. Forming an SOC film pattern filling the gate pattern, forming an interlayer insulating film on the entire structure including the SOC film pattern, and etching the interlayer insulating film to expose an upper surface of the SOC pattern. And forming a contact hole between the gate pattern by removing the exposed SOC pattern, and forming a contact plug in which the contact hole is embedded.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. Also, throughout the specification, the same reference numerals denote the same components.

Example

2A through 2F are cross-sectional views illustrating a method of forming a landing plug contact applying a self-aligned contact process according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, a gate insulating layer 111, a gate electrode layer 112, and a gate capping layer 113 are formed on a semiconductor substrate 110 on which an isolation layer (not shown), a well (not shown), and the like are formed. The gate pattern 115 of this laminated structure is formed. In this case, the gate insulating layer 111 may be formed of a conventional oxide-based material such as a silicon oxide film, and the gate electrode layer 112 may be formed of any one of polysilicon, W, WN, and WSi _X (where _X is a natural number) or these. Form in combination.

In addition, the gate capping layer 113 is to protect the gate electrode layer 112 during the subsequent landing plug contact hole formation, and uses a nitride-based material such as silicon nitride (SiN) or silicon oxynitride (SiON).

Subsequently, although not shown in the drawing, a source / drain region is formed in the substrate 110 exposed between the gate patterns 115, and spacers 116 are formed on both sidewalls of the gate pattern 115 according to a known spacer forming technique. Form.

Subsequently, a spin on coating (SOC) film 117 is formed on the entire upper surface of the substrate 110 including the gate pattern 115. The SOC film 117 must be a material having thermal stability against oxide film deposition temperature so that there is no problem in the deposition of the oxide film, and only the SOC film 117 is selectively removed without affecting the gate pattern 115 during the subsequent etching process. It should preferably be an organic compound consisting of elements of C, H and O. As such, there are various commercially available materials for the organic compound having thermal stability. Representatively, Dow Corning's 'SiLK' (trade name). 'SiLK' is an organic material deposited by spin coating, and has a thermal stability since it is cured at a high temperature of 450 ° C. In particular, the material has thermally stable properties for deposition of oxide materials mainly used in semiconductor processes, such as Plasma-Enhanced Tetra Ethyl Ortho Silicate (PETOS), High Density Plasma (HDP) oxide, and Chemical Vapor Deposition (CVD) oxide. .

In addition, unlike the conventional photoresist material, the SOC film 117 is deposited by a spin coating method, so that the SOC film 117 can be deposited to a sufficient thickness, thereby having a flat upper surface.

That is, in the embodiment of the present invention, in order to define a landing plug contact area, a SOC film having a characteristic of depositing a flat upper surface while having thermal stability at an oxide deposition temperature without using a photoresist material is used. do. Thus, all the problems of the conventional photoresist material can be solved. For example, since a normal SOC film pattern can be formed during a subsequent etching process, the SOC film pattern can be formed in a desired landing plug contact predetermined region, thereby preventing a short circuit between the landing plug contact and the gate pattern.

Subsequently, after the hard mask material is deposited on the SOC film 117, the photoresist pattern 119 is formed on the hard mask material. The photoresist pattern 119 is to define a landing plug contact scheduled region in which the landing plug contact is to be formed, and is formed to correspond to the landing plug contact scheduled region. In addition, the hard mask material may have an etch selectivity with respect to the SOC film 117 using an inorganic material such as an oxide film, SiON, SiN, SiCN, SiOC, or an organic compound material containing silicon (Si). At this time, the content of Si is preferably 10 to 50%.

Subsequently, an etching process using the photoresist pattern 119 as a mask is performed to etch the hard mask material. As a result, the hard mask pattern 118 is formed.

Subsequently, as illustrated in FIG. 2B, after the strip process is performed to remove the photoresist pattern 119, the SOC film 117 (see FIG. 2A) exposed through the hard mask pattern 118 is etched. As a result, the SOC film pattern 117A covering the landing plug contact scheduled region is formed. When the SOC film 117 is etched, any one gas plasma selected from a group of O ₂ , N ₂ , H ₂ , NH _3, and CH ₄ or a combination gas plasma thereof is used. As a result, only the SOC layer 117 may be selectively etched without damaging the gate pattern 115.

Subsequently, as illustrated in FIG. 2C, an interlayer insulating layer 119 is deposited on the entire upper surface of the substrate 110 including the hard mask pattern 118. In this case, the interlayer insulating film 119 is formed of an oxide film-based material. For example, the interlayer insulating film 119 is formed of any one of PETEOS, HDP oxide film, and CVD oxide film.

Subsequently, as illustrated in FIG. 2D, an etch back process 120 is performed to planarize the interlayer insulating film 119 and the SOC film pattern 117A. In addition, a chemical mechanical polishing process (CMP) may be performed to planarize the interlayer insulating film 119 and the SOC film pattern 117A.

Subsequently, as illustrated in FIG. 2E, an etching process is performed to remove the SOC film pattern 117A. As a result, the landing plug contact hole 121 is formed in the landing plug contact scheduled region. When removing the SOC film pattern 117A, any one gas plasma selected from the group of O ₂ , H _2, and N ₂ or a combination gas plasma thereof is used.

Subsequently, as shown in FIG. 2F, a landing plug contact 123 for filling the landing plug contact hole 121 is formed. For example, the landing plug contact material 121 is deposited so that the landing plug contact material is buried, and then CMP is formed to form the landing plug contact 123. As a result, the landing plug contact 123 may be formed to be self-aligned to the landing plug contact predetermined region.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, instead of using a photoresist material to define a landing plug contact region, an oxide film which is subsequently processed after the landing plug contact is formed by using an SOC film having thermal stability at the oxide deposition temperature. Thermally stable device characteristics can be maintained even during deposition.

In addition, according to the present invention, instead of using a photoresist material to define a landing plug contact region, a SOC film deposited by spin coating and having a flat top surface itself is used. Pattern formation is possible. Therefore, the SOC film pattern can be formed in a desired landing plug contact predetermined region, thereby preventing a short circuit between the landing plug contact and the gate pattern.

Claims (8)

Preparing a substrate on which a plurality of gate patterns are formed; Forming an SOC film on the entire structure including the gate pattern; Etching the SOC film to form an SOC film pattern filling the gap between the gate patterns of a predetermined region of a contact plug; Forming an interlayer insulating film on the entire structure including the SOC film pattern; Etching the interlayer insulating film to expose an upper surface of the SOC pattern; Removing the exposed SOC patterns to form contact holes between the gate patterns; And Forming a contact plug in which the contact hole is embedded Contact plug forming method of a semiconductor device comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, Forming the SOC film pattern, Forming a hard mask pattern on the SOC film; And Etching the SOC layer through the hard mask pattern Contact plug forming method of a semiconductor device comprising a. Claim 3 has been abandoned due to the setting registration fee. The method of claim 2, And said interlayer insulating film is formed of an oxide film. Claim 4 has been abandoned due to the setting registration fee. The method of claim 3, wherein And the SOC film is formed of an organic compound consisting of C, H, and O elements to have stability at the oxide film deposition temperature. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein The hard mask pattern is a contact plug forming method of a semiconductor device formed of an organic material containing silicon or an inorganic material made of any one of an oxide film, SiON, SiN, SiCN and SiOC. Claim 6 has been abandoned due to the setting registration fee. The method according to claim 4 or 5, Forming the SOC film pattern, Claim 7 was abandoned upon payment of a set-up fee. The method according to claim 4 or 5, The forming of the contact hole by removing the SOC film may include: O ₂ , N ₂ And a method of forming a contact plug of a semiconductor device using any one of the gas plasmas selected from the group of H ₂ or a combination gas plasma thereof. Claim 8 was abandoned when the registration fee was paid. The method according to any one of claims 2 to 5, The etching of the interlayer insulating layer may include performing an etch back or chemical mechanical polishing process.

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