KR100825034B1 - Semiconductor device with nitride?nitride?oxide spacer and method for manufacturing the same - Google Patents

Abstract

The present invention is to provide a semiconductor device suitable for improving the reliability of the device by reducing the parasitic capacitance between the storage node contact and the bit line due to the contact spacer, the method of manufacturing a semiconductor device of the present invention is a plurality of bits Forming a line; Forming a nitride film spacer on sidewalls of the bit line; Forming an interlayer insulating film over the entire surface until filling between the bit lines; Etching the interlayer insulating layer to form a storage node contact hole between the bit lines; Forming a nitride film along a surface of the interlayer insulating film including the storage node contact hole; Deforming a portion of the nitride film to form an oxide film; Selectively etching the oxide layer and the nitride layer to form a double layer contact spacer on a sidewall of the storage node contact hole; And forming a storage node contact plug to fill the storage node contact hole, and forming an insulation structure between the bit line and the storage node contact in a NIT (Nitride-Nitride-Oxide) structure. There is an effect that can reduce the liver parasitic capacitance.

Parasitic capacitance, storage node contact, contact spacer, permittivity, radical oxidation

Description

A semiconductor device having a spacer having a nitride film-nitride film-oxide structure, and a method of manufacturing the same {SEMICONDUCTOR DEVICE WITH NITRIDE-NITRIDE-OXIDE SPACER AND METHOD FOR MANUFACTURING THE SAME}

1 is a view showing the structure of a semiconductor device according to the prior art.

2 is a view showing the structure of a semiconductor device according to an embodiment of the present invention.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

4 is a detailed view illustrating an insulating structure between a storage node contact and a bit line according to an exemplary embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 first interlayer insulating film

33: landing plug contact 34: second interlayer insulating film

35: bit line 35A: barrier metal

35B: Tungsten Film 36: Bit Liner Facer

37: third interlayer insulating film 40: storage node contact hole

41, 41B: spacer nitride film 41A: spacer oxide film

42: storage node contact 100: contact spacer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method of manufacturing capacitors in semiconductor devices for reducing parasitic capacitance.

Higher integration of semiconductor devices results in a reduction in spacing between lines and a thinner thickness of each interlayer insulating film that insulates between word lines and bit lines or capacitors. Parasitic capacitance (C) increases to deteriorate device characteristics.

In this case, simply increasing the thickness of the interlayer insulating layer to reduce the parasitic capacitance may cause a decrease in the gap fill margin of the interlayer insulating layer due to the decrease in the gap between the lines and the gap.

In particular, in the case of semiconductor devices of 80 nm or less technology, there is a concern that the reliability of devices due to such parasitic capacitance increases.

1 is a view showing the structure of a semiconductor device according to the prior art.

Referring to FIG. 1, a first interlayer insulating layer 12 is formed on a semiconductor substrate 11, and a landing plug contact 13 is formed in a contact hole penetrating through the first interlayer insulating layer 12. Then, a second interlayer insulating film 14 is formed on the landing plug contact 13 and the first interlayer insulating film 12, and the barrier metal 15A and the tungsten film (a) are formed on a predetermined region of the second interlayer insulating film 14. A plurality of bit lines BL in which 15B) and the hard mask nitride film 15C are sequentially stacked are formed. A bit line spacer 16 is formed on both sidewalls of each bit line, and a third interlayer insulating film 17 is formed on the entire surface including the bit line BL. In addition, the third interlayer insulating layer 17 and the second interlayer insulating layer 14 are etched to form a storage node contact hole 18 that opens the landing plug contact 13 surface between the bit lines BL and the storage node. A contact spacer 19 of an insulating material is formed on the sidewall of the contact hole 18. In addition, the storage node contact hole 18 connected to the landing plug contact 13 is embedded in the storage node contact hole 18.

In the prior art as described above, as the contact spacer 19 and the bit liner 16 use a nitride film, the insulation structure between the bit line BL and the storage node contact 20 has a nit (Nitride-Nitride) structure. do.

However, in the prior art, the nitride film used as the contact spacer 19 has a high dielectric constant of 7 or more, causing large parasitic capacitance between the bit line BL and the storage node contact 20.

In order to reduce the parasitic capacitance, when an oxide film having a lower dielectric constant than that of the nitride film is used as the contact spacer 19, a loss of a predetermined thickness occurs in the cleaning step that proceeds after the entire surface of the contact spacer 19 is etched. ) Will not be able to ensure a sufficient thickness to be provided. In addition, if the cleaning time is reduced to reduce the thickness loss, the impurity layer such as native oxide may not be completely removed on the landing plug, thereby increasing the contact resistance between the storage node contact and the landing plug contact. have.

The present invention has been proposed to solve the above problems of the prior art, and provides a semiconductor device suitable for improving the reliability of the device by reducing the parasitic capacitance between the storage node contact and the bit line due to the contact spacer, and its manufacturing method There is a purpose.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a plurality of bit lines; Forming a nitride film spacer on sidewalls of the bit line; Forming an interlayer insulating film over the entire surface until filling between the bit lines; Etching the interlayer insulating layer to form a storage node contact hole between the bit lines; Forming a nitride film along a surface of the interlayer insulating film including the storage node contact hole; Deforming a portion of the nitride film to form an oxide film; Selectively etching the oxide layer and the nitride layer to form a double layer contact spacer on a sidewall of the storage node contact hole; And forming a storage node contact plug to fill the storage node contact hole, wherein the forming of the spacer further includes a cleaning step for removing by-products after selective etching of the oxide film and the nitride film. The oxide film may be formed by oxidizing a part of the nitride film, and the oxidation may be radical oxidation.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

2 is a diagram showing the structure of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2, the insulating material structure between the bit line 35 and the storage node contact 42 has a triple structure of the bit line spacer 36, the spacer nitride film 41B, and the spacer oxide film 41A.

In detail, a landing plug contact 33 is formed on the semiconductor substrate 31 on which the predetermined process is completed and insulated from the neighboring layer by the first interlayer insulating layer 32, and the second interlayer is formed on the first interlayer insulating layer 32. An insulating film 34 is formed.

A plurality of bit lines 35 stacked on the second interlayer insulating film 34 in the order of the barrier metal 35A, the tungsten film 35B, and the hard mask nitride film 35C are arranged at predetermined intervals, Bit line spacers 36 are formed on both side walls of the line 35.

A third interlayer insulating film 37 is formed on the bit line 35, and the landing plug contact 33 passes through the third interlayer insulating film 37 and the second interlayer insulating film 34 between the bit lines 35. The storage node contact hole 40 for opening the surface is formed.

A contact spacer 100 having a double structure of a spacer nitride film 41B and a spacer oxide film 41A is formed on the sidewall of the storage node contact hole 40. Here, the spacer oxide film 41A is an oxide film obtained by oxidizing a part of the spacer nitride film 41B through radical oxidation. As will be described later, the spacer nitride film 41B is a spacer nitride film remaining after radical oxidation.

The storage node contact 42 is buried in the storage node contact hole 40.

Looking at the reference numeral '200', which is an insulating film structure for examining the capacitance between the storage node contact 42 and the tungsten film 35B of the bit line 35, the tungsten of the storage node contact 42 and the bit line 35 is described. The structure for interlayer insulation between the films 35B is a triple structure of the spacer oxide film 41A, the spacer nitride film 41B, and the bit line spacer 36, which is a nitride film material. Since the insulating material of the triple structure includes a spacer oxide film 41A of an oxide film material having a lower dielectric constant than the nitride film, the nitride film-nitride film-oxide film is moved from the tungsten film 35B of the bit line 35 toward the storage node contact 42. It becomes NNO (Nitride-Nitrdie-Oxide) structure of. Looking in the opposite direction, the structure becomes ONN.

As described above, when an insulating material having an NNO (or ONN) structure exists between the bit line 35 and the storage node contact 42, the bit line 35 and the storage node contact 42 as compared with the nit structure (Nitride-Nitride) structure. Parasitic capacitance decreases. This is because the spacer oxide film 41A having the NNO structure has a lower dielectric constant than the rest of the nitride film material, and thus the dielectric constant for determining the parasitic capacitance between the bit line tungsten 35 and the storage node contact 42 is substantially reduced. That is, since the capacitance is proportional to the dielectric constant in the formula for calculating the capacitance, the smaller the dielectric constant, the smaller the capacitance accordingly.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 3A, a first interlayer insulating film 32 is formed on the semiconductor substrate 31 on which a predetermined process such as a transistor including an isolation layer and a gate line (or word line) is completed, and then a first interlayer is formed. A landing plug contact 33 is formed through the insulating film 32 and connected to a part of the semiconductor substrate 31 (preferably a source / drain region of the transistor). In this case, the landing plug contact 33 is formed of polysilicon.

Subsequently, after forming the second interlayer insulating film 34 on the first interlayer insulating film 32 including the landing plug contact 33, the plurality of bit lines 35 are formed on a predetermined surface of the second interlayer insulating film 34. To form. At this time, the bit line 35 is a line pattern stacked in the order of the barrier metal 35A, the tungsten film 35B, and the hard mask nitride film 35C, and the barrier metal 35A has a Ti / TiN structure.

Subsequently, a bit line spacer insulating film is deposited on the entire surface including the bit line 35, and then etched back to form a spacer-type bit line spacer 36 in contact with both sidewalls of the bit line 35. Here, the bit liner 36 is formed by depositing a silicon nitride film to a thickness of 100 to 250 GPa and then etching it back.

Subsequently, a third interlayer insulating film 37 is deposited on the entire surface until the bit lines 35 are filled. At this time, the third interlayer insulating film 37 is formed of an oxide film such as BPSG, similarly to the first and second interlayer insulating films 32 and 34, and the third interlayer insulating film 37 mitigates surface curvature due to the underlying structure. In order to achieve this, a planarization process such as chemical mechanical polishing (CMP) may be further performed.

Next, a hard mask layer 38 is formed on the third interlayer insulating film 37. At this time, the hard mask layer 38 is introduced to overcome the lack of selectivity in the etching process using the subsequent photoresist pattern, preferably formed of polysilicon.

Subsequently, a photoresist film is coated on the hard mask layer 38 and patterned by exposure and development to form a photoresist pattern 39. In this case, the photoresist pattern 39 serves as a storage node contact mask.

Subsequently, the hard mask layer 38 is etched using the photoresist pattern 39 as an etching barrier.

As shown in FIG. 3B, the storage node contact etching process using the remaining photoresist pattern 39 and the hard mask layer 38 as an etching barrier is performed.

That is, the third interlayer insulating film 37 and the second interlayer insulating film 34 are etched using the remaining photoresist pattern 39 and the hard mask layer 38 as an etching barrier, and the landing plug contacts between the bit lines 35 are etched. A storage node contact hole 40 for opening the surface of 33 is formed. The above etching process may be performed by a self aligned contact etching (SAC) method, and the photoresist pattern 39 is not consumed and remains when the storage node contact hole 40 is formed.

After the storage node contact hole 40 is formed, the hard mask layer 38 is removed and the cleaning process is continuously performed to remove by-products generated in the etching process. Here, the hard mask layer 38 is removed in the chamber in which the storage node contact etching is performed.

As shown in FIG. 3C, a spacer nitride film 41 used as a storage node contact spacer is deposited on the third interlayer insulating layer 37 including the storage node contact hole 40. At this time, the spacer nitride film 41 is deposited to a thickness of 100 to 350 GPa, and is formed by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). Preferably, the spacer nitride film 41 is a silicon nitride film (Si ₃ N ₄ ).

As shown in FIG. 3D, immediately after the formation of the spacer nitride film 41, radical oxidation is performed to oxidize a portion of the surface of the spacer nitride film 41. By such radical oxidation, a part of the spacer nitride film 41 becomes a spacer oxide film 41A, and the remainder remains as a spacer nitride film 41B. Preferably, the spacer oxide film 41A has a Si _x O _y structure.

The radical oxidation for forming the spacer oxide film 41A is performed by injecting oxygen and hydrogen into the plasma chamber and applying power for plasma generation. In detail, the top side for plasma generation using a mixed gas of O ₂ / H ₂ O or a mixed gas of H ₂ / O ₂ as an oxidizing atmosphere gas at a pressure of 0.3 to 1.5 Torr and a temperature range of 400 to 700 ° C. Top RF power is 3000 to 4000W, and side RF power is 300 to 1000W. Oxygen radicals in the plasma generated by the above conditions and silicon (Si) in the spacer nitride film 41 react to form 'Si _x O _y ' to form 30 to 80% of the thickness of the spacer nitride film 41. A spacer oxide film 41A having a thickness is formed and the remainder is left as a spacer nitride film 41B.

The principle in which the spacer oxide film 41A is formed will be described in detail. Oxygen radicals and 'silicon (Si)' in the space-depositing film 41 react first to form SiO ₂ . As such, the reason why the oxygen radicals and the silicon in the spacer nitride film 41 react first is because a gas having a hydrogen component such as hydrogen (H ₂ ) or H ₂ O is used, and hydrogen undergoes a reduction reaction with the spacer nitride film 41. And the 'Si' generated by the reduction reaction reacts with the oxygen radicals so that a part of the spacer nitride film 41 is changed into SiO ₂ . This oxidation reaction is called 'radical oxidation'.

The spacer oxide film 41A formed through the series of radical oxidations described above generally exhibits a different film density from that of a pure oxide film by a deposition method such as LPCVD or PECVD. That is, the wet etching rate of the pure oxide film by the vapor deposition method and the oxide film by the radical oxidation is different depending on the density difference of the structure itself.

For example, the oxide film formed through radical oxidation has a wet etching rate slower than that of pure SiO ₂ by the vapor deposition method. HDP oxide, which is known to use the concept of radical oxidation, is known to have a slower wet etch rate than a pure oxide film by evaporation during wet etching using BOE (Buffered Oxide Etchant) solution.

This slow wet etch rate minimizes the loss of the spacer oxide layer 41A during subsequent cleaning, thereby sufficiently maintaining the thickness of the storage node contact spacer.

As described above, the spacer oxide film 41A formed through radical oxidation not only has a lower dielectric constant (dielectric constant 3.9) than the nitride film (dielectric constants 7 to 10) but also has a wet etching rate slower than that of the pure oxide film, so that subsequent contact spacer etching and After the subsequent cleaning process, the desired amount of contact spacers can be left. As a result, parasitic capacitance can be lowered. The parasitic capacitance will be described later.

As shown in FIG. 3E, the spacer oxide layer 41A and the spacer nitride layer 41B are etched to the entire surface to expose the surface of the landing plug contact 33 while contacting the sidewall of the storage node contact hole 40. To form. At this time, since the contact spacer 100 has a double structure of the spacer oxide film 41A and the spacer nitride film 41B, a sufficient thickness to prevent the tungsten film 35B and the storage node contact plug of the bit line 35 from shorting. Has

Subsequently, washing is performed to remove the etch byproducts. At this time, the washing is wet cleaning, the first washing using a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ), and the second washing is performed to the NH ₄ / HF mixed solution.

As shown in FIG. 3F, a conductive film is deposited on the third interlayer insulating film 37 until the storage node contact hole 40 in which the contact spacer 100 is formed is filled. At this time, for example, a polysilicon film is used as the conductive film. Then, the storage node contact 42 is formed by planarizing the conductive film until the surface of the third interlayer insulating film 37 is exposed by performing full surface etching or chemical mechanical polishing.

Reference numeral 200 in FIG. 3F denotes an insulating film structure between the storage node contact 42 and the tungsten film 35B of the bit line 35.

FIG. 4 is a detailed view of reference numeral '200', which is an insulating film structure for examining the capacitance between the storage node contact 42 and the tungsten film 35B of the bit line 35 of FIG. 3F.

That is, FIG. 4 is a detailed view illustrating an insulating structure between a storage node contact and a bit line according to an exemplary embodiment of the present invention, wherein the interlayer insulation between the storage node contact 42 and the tungsten film 35B of the bit line 35 is performed. The structure for the structure is a triple structure of the spacer oxide film 41A, the spacer nitride film 41B, and the bit line spacer 36, which is a nitride film material. Since the insulating material of the triple structure includes a spacer oxide film 41A of an oxide film material having a lower dielectric constant than the nitride film, the nitride film-nitride film-oxide film is moved from the tungsten film 35B of the bit line 35 toward the storage node contact 42. It becomes NNO (Nitride-Nitrdie-Oxide) structure of. Looking in the opposite direction, the structure becomes ONN.

As described above, when an insulating material having an NNO structure is present between the tungsten film 35B of the bit line 35 and the storage node contact 42, the bit line 35 and the storage node contact as compared to the nit structure (NN). Parasitic capacitance decreases between (42). This is because the spacer oxide film 41A having the NNO structure has a lower dielectric constant than the rest of the nitride film material, so that the dielectric constant for determining the parasitic capacitance between the bit line 35 and the storage node contact 42 is substantially reduced. That is, since the capacitance is proportional to the dielectric constant in the formula for calculating the capacitance, the smaller the dielectric constant, the smaller the capacitance accordingly.

In addition, since the spacer oxide layer 41A having a small thickness loss is provided even after the subsequent cleaning, the thickness is maintained for the interlayer insulation between the storage node contact 42 and the bit line 35. The capacitance between the bit lines 35 is further reduced.

For example, the capacitance of the capacitor C is defined as in Equation 1 below.

Is the permittivity, A _S is the effective area of the electrode, and d is the distance between the electrodes. In Equation 1, the capacitance (C) is proportional to the dielectric constant (ε) and the area (A _S ), and can be seen to be inversely proportional to the distance (d) between electrodes, and in order to reduce the capacitance (C), the dielectric constant (ε) What is necessary is to reduce the area A _S and increase the thickness d.

In the present invention, since the spacer oxide film 41A is formed by oxidizing a part of the spacer nitride film 41 through radical oxidation among the factors for determining the capacitance, it can be seen that there is some increase in the thickness d, and the nitride film-nitride film-oxide film There is a change in permittivity (ε) due to the triple structure of. However, there is no increase in area.

For example, since the spacer oxide film 41A having a low dielectric constant is inserted, the total dielectric constant of the insulating material between the bit line 35 and the storage node contact 42 may be inserted as the spacer oxide film 41A having the low dielectric constant is inserted. Decreases. In addition, since the spacer oxide film 41A is formed through radical oxidation, an increase in thickness is accompanied.

As a result, the parasitic capacitance between the bit line 35 and the story node contact 42 is reduced by changing the structure of the insulating material between the bit line 35 and the storage node contact 42 to the NNO structure.

According to the embodiment described above, when forming the contact spacer 100 provided on the sidewall of the storage node contact hole, the spacer nitride film 41 is deposited with a contact spacer material, and then a part of the spacer nitride film 41 is removed. By oxidizing through radical oxidation to form a double-contact structure in which the spacer oxide film 41A is formed on the spacer nitride film 41B, it is possible to have a lower dielectric constant and a thickness increase effect than a single film spacer using only the nitride film. .

Therefore, parasitic capacitance between the storage node contact 42 and the tungsten film 35B of the bit line 35 can be reduced.

In addition, since the spacer oxide film 41A is formed by radical oxidation, the loss due to the subsequent cleaning process can be minimized, and the thickness of the contact spacer can be maintained to a thickness sufficient to insulate.

As a result, the present invention implements a contact spacer capable of maintaining a sufficient thickness for insulation while having a low dielectric constant, thereby reducing unwanted parasitic capacitance values, thereby improving device reliability.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention described above, after depositing a nitride film with a contact material, the nitride film is oxidized through radical oxidation to realize an oxide film having a slow wet etching rate, thereby increasing the thickness of the insulating film for low dielectric constant and interlayer insulation. There is an effect that can reduce the parasitic capacitance value.

In addition, since the same effect can be obtained without increasing the thickness of the interlayer insulating film, the gap fill margin of the interlayer insulating film can be increased.

Claims (17)

Forming a plurality of bit lines; Forming a nitride film spacer on sidewalls of the bit line; Forming an interlayer insulating film over the entire surface until filling between the bit lines; Etching the interlayer insulating layer to form a storage node contact hole between the bit lines; Forming a nitride film along a surface of the interlayer insulating film including the storage node contact hole; Deforming a portion of the nitride film to form an oxide film; Selectively etching the oxide layer and the nitride layer to form a double layer contact spacer on a sidewall of the storage node contact hole; And Forming a storage node contact plug to fill the storage node contact hole Method for manufacturing a semiconductor device comprising a. The method of claim 1, Forming the spacers, The method of manufacturing a semiconductor device further comprising a cleaning step for removing by-products after selective etching of the oxide film and the nitride film. delete The method of claim 1, The oxide film, A method of manufacturing a semiconductor device, which is formed by oxidizing a part of the nitride film. The method of claim 4, wherein The oxidation is a method of manufacturing a semiconductor device is radical oxidation. The method of claim 5, The radical oxidation, A method of manufacturing a semiconductor device using a mixed gas of O ₂ and H ₂ O or a mixed gas of H ₂ and O ₂ as an oxidation atmosphere. The method of claim 6, The radical oxidation is, The manufacturing method of the semiconductor element which advances in the pressure of 0.3-1.5 Torr and the temperature atmosphere of 400-700 degreeC. The method of claim 1, The nitride film, The manufacturing method of the semiconductor element formed in 100-350 micrometers thickness. The method of claim 1, The oxide film, The manufacturing method of the semiconductor element which becomes 30 to 80% thickness of the said nitride film thickness. The method of claim 2, The cleaning step, 1. A method for manufacturing a semiconductor device in which a primary cleaning using a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ) and a secondary cleaning using an NH ₄ / HF mixed solution are performed sequentially. The method of claim 1, The plurality of bit lines, A method of manufacturing a semiconductor device having a structure in which a barrier metal, tungsten, and a hard mask nitride film are sequentially stacked. delete delete delete delete A plurality of bit lines; A storage node contact formed between the plurality of bit lines; A nitride film spacer in contact with the sidewalls of the bit line; And A contact spacer in contact with the storage node contact; The contact spacer includes a nitride film in contact with the nitride film spacer and an oxide film in contact with the storage node contact by oxidizing a portion of the nitride film through radical oxidation. The method of claim 16, The oxide film, A semiconductor device which becomes 30 to 80% of the thickness of the nitride film.

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