KR20020058436A - Method of forming contact hole in semiconductor device - Google Patents
Method of forming contact hole in semiconductor device Download PDFInfo
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- KR20020058436A KR20020058436A KR1020000086542A KR20000086542A KR20020058436A KR 20020058436 A KR20020058436 A KR 20020058436A KR 1020000086542 A KR1020000086542 A KR 1020000086542A KR 20000086542 A KR20000086542 A KR 20000086542A KR 20020058436 A KR20020058436 A KR 20020058436A
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- bit line
- interlayer insulating
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 30
- 125000006850 spacer group Chemical group 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000003860 storage Methods 0.000 claims abstract description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 229920005591 polysilicon Polymers 0.000 abstract description 8
- 238000000059 patterning Methods 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 239000003989 dielectric material Substances 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 콘택홀의 형성 방법에 관한 것이며, 더 자세히는 반도체소자의 자기정렬 콘택(Self-aligned contact) 식각 후의 콘택트 스페이서(Contact spacer) 형성 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a contact hole, and more particularly, to a process of forming a contact spacer after self-aligned contact etching of a semiconductor device.
반도체 소자의 고집적화에 따라 패턴 및 패턴 간극이 미세화되고 있으며, 이에 따라 공정 마진이 줄어들고 있다. 특히 스토리지노드 콘택 형성 시 공정 마진이 크게 감소되어 수율 저하의 주된 요인이 되었다.Patterns and pattern gaps are miniaturized with high integration of semiconductor devices, thereby reducing process margins. In particular, the process margin was greatly reduced when forming storage node contacts, which was a major factor in yield reduction.
이러한 스토리지노드 콘택 형성 시 공정 마진을 증가시키기 위하여 자기정렬콘택(SAC) 공정이 도입되어 사용되고 있다.In order to increase the process margin when forming the storage node contact, a self-aligned contact (SAC) process is introduced and used.
도 1a 내지 도 1b는 종래기술에 따른 반도체소자의 콘택홀 형성 방법에 있어서의 문제점을 도시한 도면이다.1A to 1B illustrate problems in a method for forming a contact hole in a semiconductor device according to the prior art.
도 1a 내지 도 1b에 도시된 바와 같이, 반도체기판(10) 상에 소자격리를 위한 제1층간절연막(11)이 선택적으로 식각되어 형성되어 있고, 상기 드러난 기판(10) 상에 폴리실리콘 등을 이용한 플러그(12)가 형성되어 있다. 상기플러그(12) 상부에 제2층간절연막(13), 비트라인(14), 하드마스크 질화막(15)과 상기 비트라인(14)의 측벽에 접하는 측벽 스페이서(16)가 형성되어 있다. 상기 제2도전패턴 상부에 제3층간절연막(17)이 형성되어 있다. 상기 제2, 제3 층간절연막(13, 17)이 선택적으로 식각되어 콘택홀(도시하지 않음)이 형성되어 있으며, 상기 콘택홀(도시하지 않음) 내부에 스토리지노드(Storagenode) 콘택을 위한 도전패턴(18)이 콘택되어 있다.As shown in FIGS. 1A to 1B, a first interlayer insulating film 11 for device isolation is selectively etched on the semiconductor substrate 10, and polysilicon or the like is formed on the exposed substrate 10. The used plug 12 is formed. A second interlayer insulating film 13, a bit line 14, a hard mask nitride film 15, and sidewall spacers 16 contacting sidewalls of the bit line 14 are formed on the plug 12. A third interlayer insulating layer 17 is formed on the second conductive pattern. The second and third interlayer insulating layers 13 and 17 are selectively etched to form contact holes (not shown), and conductive patterns for storage node contacts within the contact holes (not shown). (18) is in contact.
상술한 바와 같은 종래의 콘택홀 형성 방법은, 도 1b에 도시된 바와 같이 오정렬(Misalignment) 정도가 심한 경우는 콘택홀 식각 시 상기 하드마스크 질화막(15) 위에서 식각 정지를 발생하기에 충분한 폴리머가 상기 제3층간절연막(17)의 측벽에 형성되므로 상기 비트라인(14)과 도전패턴(18)의 전기적 단락(Short)이 발생하지 않는다.As described above, in the conventional method for forming a contact hole, as shown in FIG. 1B, when the misalignment degree is severe, sufficient polymer is sufficient to generate an etch stop on the hard mask nitride layer 15 during etching of the contact hole. Since it is formed on the sidewall of the third interlayer insulating layer 17, an electrical short between the bit line 14 and the conductive pattern 18 does not occur.
그러나, 도 1a에 도시된 바와 같이 상기 하드마스크 질화막(15)의 끝부분에 걸칠 정도로 오정렬 정도가 심하지 않을 경우, 비트라인(14)과 도전패턴(18)의 전기적 단락(19)이 발생하게 된다.However, as shown in FIG. 1A, when the misalignment is not so severe as to cover the end of the hard mask nitride film 15, an electrical short 19 between the bit line 14 and the conductive pattern 18 occurs. .
한편, 종래기술의 문제점인 상기 비트라인(14)과 도전패턴(18)의 전기적 단락을 방지하기 위해 상기 측벽 스페이서(16)의 두께를 증가시키는 방법도 있을 수 있으나, 이럴 경우 후속의 제3층간절연막(17)의 갭필(Gap fill) 불량을 초래하는 문제점이 발생한다.On the other hand, there may be a method of increasing the thickness of the side wall spacer 16 to prevent the electrical short between the bit line 14 and the conductive pattern 18, which is a problem of the prior art, in this case, the subsequent interlayer There arises a problem that leads to a gap fill defect of the insulating film 17.
본 발명은 상기 종래기술의 문제점을 해결하기 위한 것으로서, 스토리지노드 콘택 시 비트라인과의 단락을 방지하는데 적합한 반도체소자의 콘택홀 형성 방법을 제공함에 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object thereof is to provide a method for forming a contact hole in a semiconductor device suitable for preventing a short circuit with a bit line during a storage node contact.
도 1a 내지 도 1b는 종래기술에 따라 형성된 콘택홀의 문제점을 도시한 도면,1a to 1b is a view showing a problem of a contact hole formed according to the prior art,
도 2a 내지 도 2e는 본 발명의 실시예에 따른 콘택홀 형성 방법을 도시한 도면.2A to 2E illustrate a method of forming a contact hole according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
20 : 반도체 기판20: semiconductor substrate
21 : 제1층간절연막21: first interlayer insulating film
22 : 플러그22: plug
23 : 제2층간절연막23: second interlayer insulating film
24 : 비트라인24: bit line
25 : 하드마스크 질화막25: hard mask nitride film
26 : 측벽 스페이서26: sidewall spacer
27 : 제3층간절연막27: third interlayer insulating film
28 : 콘택홀28: contact hole
29 : 콘택트 스페이서29: contact spacer
30 : 도전패턴30: conductive pattern
상기의 목적을 달성하기 위한 본 발명의 콘택홀 형성 방법은, 플러그가 형성된 반도체 기판 상에 상부 하드마스크 질화막 및 측벽 스페이서를 구비한 비트라인을 형성하는 제1단계; 상기 제1 단계가 완료된 전체구조 상부에 층간절연막을 형성하는 제2단계; 캐패시터 형성 영역의 상기 층간절연막을 식각하여 콘택홀을 형성하는 제3단계; 상기 층간절연막 측벽을 따라 저압 화학기상 증착법에 의한 질화막을 이용한 전면 식각된 콘택트 스페이서를 형성하는 제4단계; 및 상기 제4단계가 완료된 콘택홀 내부에 스토리지노드 콘택을 위한 도전패턴을 형성하는 제5단계를 포함하여 이루어짐을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a contact hole, the method including: forming a bit line having an upper hard mask nitride layer and a sidewall spacer on a plug-type semiconductor substrate; A second step of forming an interlayer insulating film on the entire structure where the first step is completed; A third step of forming a contact hole by etching the interlayer insulating layer in the capacitor formation region; Forming a front-etched contact spacer using a nitride film by a low pressure chemical vapor deposition method along sidewalls of the interlayer dielectric layer; And a fifth step of forming a conductive pattern for the storage node contact in the contact hole where the fourth step is completed.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2e는 본 발명의 실시예에 따른 콘택홀의 형성 방법을 도시한 도면이다.2A to 2E illustrate a method of forming a contact hole according to an exemplary embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이 반도체 기판(20) 상에 통상적인 절연 물질을 이용하여 제1층간절연막(21)을 형성한 후, 선택적으로 식각하여 상기 기판(20)상의 일부분을 오픈시킨다. 이어서, 상기 오픈된 기판(20) 상에 폴리실리콘 등을 이용하여 플러그(22)를 형성한 후, 제2층간절연막(23)을 형성한다.First, as shown in FIG. 2A, a first interlayer insulating film 21 is formed on a semiconductor substrate 20 using a conventional insulating material, and then selectively etched to open a portion of the substrate 20. Subsequently, after the plug 22 is formed on the open substrate 20 using polysilicon or the like, a second interlayer insulating film 23 is formed.
다음으로, 도 2b에 도시된 바와 같이 상기 제2층간절연막(23) 상에 폴리실리콘 등을 이용하여 비트라인(24) 형성하고, 이위에 하드마스크 질화막(25)을 차례로 형성한 후, 소정패턴으로 패터닝하여 비트라인(24)을 형성한 다음, 상기 비트라인(24)의 측면에 예컨대, 통상의 질화막 등을 이용하여 측벽 스페이서(26)를 형성한다. 이어서, 상기 비트라인(24)과 후속 공정에 의한 상부의 절연을 위한 제3층간절연막(27)을 형성한다.Next, as shown in FIG. 2B, the bit line 24 is formed on the second interlayer insulating film 23 using polysilicon or the like, and the hard mask nitride film 25 is sequentially formed thereon, and then a predetermined pattern is formed. After forming the bit line 24 by patterning, the sidewall spacers 26 are formed on the side surfaces of the bit line 24 using, for example, a conventional nitride film or the like. Subsequently, a third interlayer insulating layer 27 is formed to insulate the bit line 24 and the upper part by a subsequent process.
이어서 도 2c에 나타낸 바와 같이 자기정렬 콘택(self-aligned contact)에 의해 상기 제2, 제3 층간절연막(23, 27)을 선택적으로 식각하여 콘택홀(28)을 형성한다.Subsequently, as shown in FIG. 2C, the second and third interlayer insulating films 23 and 27 are selectively etched by self-aligned contact to form a contact hole 28.
구체적으로, 소정의 콘택마스크(도시하지 않음)를 이용하여 상기 제2, 제3 층간절연막(23, 27)을 선택적으로 식각하여 콘택부위를 노출시키는 바, C2F6, C3F8, C4F8, C5F8, CH3F, CH2F2또는 CHF3등의 CF계 가스를 이용하여 식각하며, 상기 하드마스크 질화막(25) 위에서 식각 정지가 이루어지도록 한다.Specifically, the second and third interlayer insulating films 23 and 27 are selectively etched using a predetermined contact mask (not shown) to expose the contact portions, such as C 2 F 6 , C 3 F 8 , Etching is performed using CF gas such as C 4 F 8 , C 5 F 8 , CH 3 F, CH 2 F 2, or CHF 3, and the etch stop is performed on the hard mask nitride layer 25.
다음으로, 도 2d에 도시된 바와 같이 상기 콘택홀(28)이 드러나도록 선택적으로 식각된 제3층간절연막(27) 측벽을 따라 50Å 내지 300Å의 두께가 되도록 콘택트 스페이서(29)를 형성한다.Next, as shown in FIG. 2D, the contact spacers 29 are formed to have a thickness of 50 μs to 300 μs along the sidewalls of the third interlayer insulating layer 27 selectively etched to expose the contact holes 28.
상기 콘택트 스페이서(29) 형성 과정을 구체적으로 살펴보면, 결과물 전면에저압화학기상증착법(Low Pressure Chemical Vapor Deposition; LPCVD)을 이용하여 질화막(29)을 증착한다. 이어서, 전면식각을 통해 상기 제3층간절연막(27)의 측벽을 따라 상기 콘택트 스페이서(29)가 남도록 하는 바, 상기 콘택홀(28) 하부의 상기 플러그(22)가 드러나도록 한다.Looking at the formation of the contact spacer 29 in detail, the nitride film 29 is deposited on the entire surface of the resultant using low pressure chemical vapor deposition (LPCVD). Subsequently, the contact spacers 29 remain along the sidewalls of the third interlayer insulating layer 27 through the entire surface etching so that the plugs 22 below the contact holes 28 are exposed.
이때, 상기 콘택홀(28) 식각 시 발생하는 데미지에 의해 증가하는 콘택저항을 감소하도록 하기 위해 CF4, O2, Ar, NF3또는 He 등의 가스를 이용한다.In this case, a gas such as CF 4 , O 2 , Ar, NF 3, or He is used to reduce contact resistance that is increased due to damage generated during etching of the contact hole 28.
다음으로, 도 2e에 도시된 바와 같이 상기 콘택홀(28)에 폴리실리콘을 증착한 다음, 상기 폴리실리콘을 선택적으로 패터닝하여 스토리지노드 등의 콘택을 위한 도전패턴(30)을 콘택시킨다.Next, as illustrated in FIG. 2E, polysilicon is deposited in the contact hole 28, and then the polysilicon is selectively patterned to contact the conductive pattern 30 for a contact such as a storage node.
상기와 같은 공정을 실시하는 경우, 전극간 단락 마진 확보를 위해 측벽 스페이서의 두께를 늘리지 않아도 되므로 제3층간절연막의 갭필 특성을 향상시킬 수 있다. 또한, 콘택홀 형성 후 저압 화학기상증착법에 의한 질화막을 증착하여 콘택트 스페이서를 형성함으로서, 워드라인 또는 비트라인과 콘택의 단락 마진을 확보하여 전극간 단락을 방지함과 동시에 자기정렬 콘택 후의 식각 공정시 워드라인 또는 비트라인 스페이서의 손실을 후속 콘택트 스페이서 식각에서 어느 정도 보상해 줄 수 있다.In the above process, the thickness of the sidewall spacers does not have to be increased to secure the short-circuit margin between the electrodes, thereby improving the gap fill characteristic of the third interlayer insulating film. In addition, after forming the contact hole, by depositing a nitride film by a low pressure chemical vapor deposition method to form a contact spacer, the short-circuit margin between the word line or bit line and the contact is secured to prevent short-circuit between the electrodes and at the same time during the etching process after the self-aligned contact The loss of wordline or bitline spacers can be compensated to some extent in subsequent contact spacer etching.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 콘택홀 형성 방법은 콘택홀 형성 후 콘택트 스페이서를 형성함으로써, 콘택과 비트라인 또는 워드라인의 단락을 방지하며 콘택저항을 감소시켜 소자의 수율을 향상시킬 수 있는 효과가 있다.The contact hole forming method of the present invention as described above, by forming a contact spacer after the formation of the contact hole, it is possible to prevent a short circuit between the contact and the bit line or word line and to reduce the contact resistance to improve the yield of the device .
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| KR100825034B1 (en) * | 2006-02-21 | 2008-04-24 | 주식회사 하이닉스반도체 | Semiconductor device with nitride?nitride?oxide spacer and method for manufacturing the same |
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