KR20020019286A - Contact wiring in semiconductor device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A contact structure of a semiconductor device and a manufacturing method thereof are provided to simplify manufacturing processes and to reduce a contact resistance by directly forming a storage node contact using a single step. CONSTITUTION: After forming word lines(32) on a semiconductor substrate(31), spacers(33) are formed at both sidewalls of the word lines(32). After forming a first interlayer dielectric(34) on the resultant structure, a bit line contact hole is formed. After forming a barrier metal film(35) on the bit line contact hole, a tungsten plug(36) is filled into the bit line contact hole. A bit line(37) is formed on the tungsten plug(36). After forming a second interlayer dielectric(38) on the resultant structure, node contact holes are formed by sequentially etching the second and first interlayer dielectrics(38,34). A polysilicon plug(39) is filled into the node contact holes.

Description

CONTACT WIRING IN SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a contact wiring and a manufacturing method of the semiconductor device.

Referring to the accompanying drawings, a contact wiring and a manufacturing method of a conventional semiconductor device will be described.

1 is a cross-sectional view illustrating a structure of contact wiring of a conventional semiconductor device.

2A to 2E are cross-sectional views illustrating a method of manufacturing a contact wiring of a conventional semiconductor device.

As shown in FIG. 1, a contact wiring of a conventional semiconductor device includes a plurality of word lines 2 formed in one line direction on a semiconductor substrate 1, and sidewall insulating layers 3 are formed on both sides of each word line 2. There is this. Although not shown in the drawings, the semiconductor substrate 1 is divided into active regions and a field region, a field oxide film is formed in the field region, and the word lines 2 are configured to cross each active region. Source and drain regions are formed in the active regions on both sides of the word line 2.

A first interlayer insulating film 4 is formed on the entire surface of the semiconductor substrate 1 including the word line 2 and the sidewall insulating film 3, and the drain and source regions are formed in the active regions on both sides of the word line 3. The first bit line contact hole and the first storage node contact hole are formed in the interlayer insulating film 4 so as to be exposed.

First and second poly plugs 4a and 4b are formed in the first bit line contact hole and the first storage node contact hole, and a second interlayer is formed on the front surface including the first and second poly plugs 4a and 4b. The insulating film 6 is deposited.

In addition, a second bit line contact hole is formed in the second interlayer insulating film 6 so that one region of the first poly plug 4a in the first bit line contact hole is exposed, and titanium is formed along the surface of the second bit line contact hole. A stacked barrier metal 7 of titanium nitride (Ti / TiN) is formed.

A tungsten plug 8 is formed in the second bit line contact hole on the barrier metal 7, and there is a tungsten bit line 9 in contact with the tungsten plug 8 and formed in one line direction. A third interlayer insulating film 10 is formed on the entire surface of the second interlayer insulating film 6 including 9).

A second storage node contact hole is formed in the third and second interlayer insulating films 10 and 6 so that a part of the second poly plug 4b is exposed, and the storage node 11 is formed in the second storage node contact hole. Formed.

Referring to the method of manufacturing the contact wiring of the conventional semiconductor device configured as described above are as follows.

First, as illustrated in FIG. 2A, a plurality of word lines 2 are formed on the semiconductor substrate 1 so as to have a single line direction. The figure shows four word lines arranged in parallel. Although not shown in the drawing, the semiconductor substrate 1 is defined as a field region and an active region, a field oxide film is formed in the field region, and a source region and a drain region are formed in the active region on both sides of the word line 2.

Subsequently, an oxide film or a nitride film is deposited as an insulating film on the entire surface of the semiconductor substrate 1, and the sidewall insulating film 3 is formed on both sides of each word line 2 by etching the insulating film by a dry etching method.

The first interlayer insulating film 4 is deposited on the entire surface of the semiconductor substrate 1 including the word line 2 and the sidewall spacers 3.

Although not shown in the drawings, the first interlayer insulating film 4 is formed so that the source and drain regions of both sides of the word line 2 are exposed, that is, the portion where the first bit line contact hole and the first storage node contact hole are to be formed. The photoresist pattern is formed to be open, and the first interlayer insulating layer 4 is removed using the photoresist pattern formed as a mask to form a first bit line contact hole and a first storage node contact hole.

The first poly plug 4a and the second poly plug 4b are deposited on the first interlayer dielectric layer including the first bit line contact hole and the first storage node contact hole, and then etched back. Form.

Next, as shown in Fig. 2C, a second interlayer insulating film 6 is deposited on the first interlayer insulating film 5 including the first and second poly plugs 4a and 4b.

A second bit line contact hole is formed in the second interlayer insulating film 6 so that a part of the first poly plug 4a formed in the first bit line contact hole is exposed.

A barrier metal 7 in which titanium and titanium nitride are stacked is formed on a surface of the second bit line contact hole, and a tungsten plug 8 is formed in the second bit line contact hole.

Thereafter, the tungsten bit line 9 is formed to be in contact with the tungsten plug 8 to form a one-line direction.

A third interlayer insulating film 10 is deposited on the second interlayer insulating film 6 including the tungsten bit line 9.

Next, as shown in FIG. 2E, the third and second interlayer insulating films 10 and 6 are sequentially etched so that one region of the second poly plug 4b is exposed to form a second storage node contact hole.

Thereafter, a polysilicon layer is deposited on the entire surface including the second storage node contact hole and then etched back to form the storage node 11 in the second storage node contact hole.

The contact wiring and the manufacturing method of the conventional semiconductor device as described above has the following problems.

Since the storage node contact and the bit line contact must be doubled through two etching processes, the process may be complicated, resulting in a low yield and a high resistance.

The present invention has been made to solve the above problems, and in particular, it is an object of the present invention to provide a contact wiring of a semiconductor device suitable for reducing the contact resistance while simplifying the process and a manufacturing method thereof.

1 is a cross-sectional view showing a structure of contact wiring of a conventional semiconductor device

2A through 2E are cross-sectional views illustrating a method of manufacturing a contact wiring of a conventional semiconductor device.

3 is a structural cross-sectional view showing a contact wiring of a semiconductor device of the present invention.

4A through 4E are cross-sectional views illustrating a method of manufacturing contact wiring in a semiconductor device according to the present invention.

Explanation of symbols for the main parts of the drawings

31: semiconductor substrate 32: word line

33 sidewall insulating film 34 first interlayer insulating film

35: barrier metal layer 36: tungsten plug

37: bit line 38: second interlayer insulating film

39: poly plug

The contact wiring of the semiconductor device according to the present invention for achieving the above object is a first interlayer insulating film having a word line formed in one line direction on the semiconductor substrate, a bit line contact hole is formed so that the impurity region on one side of the word line is exposed, A barrier metal formed along a bit line contact hole surface, a first plug formed in the bit line contact hole on the barrier metal, a bit line formed in a one-line direction to contact the first plug, and the first interlayer including the bit line And a second plug formed in the node contact hole, and a second interlayer insulating film formed on the insulating film, a node contact hole formed in the second and first interlayer insulating films so that an impurity region on the other side of the word line is exposed.

The method for manufacturing a contact wiring of a semiconductor device according to the present invention having the above structure includes the steps of forming a word line in a line direction on a semiconductor substrate, forming a first interlayer insulating film on the entire surface of the semiconductor substrate, Forming a bit line contact hole in the first interlayer insulating film to expose the impurity region, forming a barrier metal along the bit line contact hole surface, and forming a first plug in the bit line contact hole on the barrier metal Forming a bit line in one line direction to be in contact with the first plug, forming a second interlayer insulating film on the first interlayer insulating film including the bit line, and revealing impurity regions on the other side of the word line. Forming a node contact hole in the second and first interlayer dielectric layers, and forming a second plug in the node contact hole The features.

Referring to the accompanying drawings, a contact wiring and a method of manufacturing the semiconductor device of the present invention will be described.

3 is a cross-sectional view illustrating a structure of contact wiring of a semiconductor device of the present invention, and FIGS. 4A to 4E are cross-sectional views illustrating a method of manufacturing contact wiring of a semiconductor device of the present invention.

The present invention relates to a technology for preventing storage node contact and bit line contact resistance from increasing in accordance with the current trend of reducing process margin due to a reduction in design rule in high-density DRAM technology.

First, the contact wiring of the semiconductor device of the present invention has a plurality of word lines 32 formed in one line direction on the semiconductor substrate 31 as shown in FIG. 3, and both side surfaces of each word line 32 have sidewall insulating films ( 33) There is. Although not shown in the drawing, the semiconductor substrate 31 is divided into active regions and a field region, a field oxide film is formed in the field region, and the word lines 32 are configured to cross each active region. Source and drain regions are formed in the active regions on both sides of the word line 32.

The first interlayer insulating film 34 is formed on the entire surface of the semiconductor substrate 31 including the word line 32 and the sidewall insulating layer 33, and the drain region formed in the active region between the word lines 33 is exposed. Bit line contact holes are formed in the interlayer insulating film 34.

A barrier metal 35 in which titanium (Ti) and titanium nitride (TiN) are stacked is formed along the surface of the bit line contact hole. A tungsten plug 36 is formed in the bit line contact hole including the barrier metal 35.

A tungsten bit line 37 is formed on the tungsten plug 36 so as to be in contact with each other and form a one-line direction.

A second interlayer insulating film 38 is formed on the first interlayer insulating film 34 including the tungsten bit line 37, and the second interlayer insulating film 38 is formed so that the source region of each word line 32 is exposed. Node contact holes are formed in the first interlayer insulating film 34.

A poly plug 39 is formed in each node contact hole.

Next, a method for manufacturing contact wiring of the semiconductor device of the present invention having the above configuration will be described.

First, as illustrated in FIG. 4A, a plurality of word lines 32 are formed on the semiconductor substrate 31 so as to have a single line direction. The figure shows four word lines arranged in parallel. Although not shown in the drawing, the semiconductor substrate 31 is defined as a field region and an active region, a field oxide film is formed in the field region, and a source region and a drain region are formed in the active regions on both sides of the word line 32.

Thereafter, an oxide film or a nitride film is deposited as an insulating film on the entire surface of the semiconductor substrate 31, and then the insulating film is etched by a dry etching method to form sidewall insulating films 33 on both sides of each word line 32.

The first interlayer insulating film 34 is deposited on the entire surface of the semiconductor substrate 31 including the word line 32 and the sidewall spacers 33.

Although not shown in the drawings, a photoresist pattern is formed so that the drain region between the word lines 32 is exposed, that is, the first interlayer insulating layer 34 of the portion where the bit line contact hole is to be opened is formed. The bit line contact hole is formed by removing the first interlayer insulating layer 34 between the word lines 32 using the pattern as a mask.

Next, as shown in FIG. 4B, a barrier metal in which Ti / TiN is laminated by sequentially depositing titanium (Ti) and titanium nitride (TiN) on the bit line contact hole surface and the first interlayer insulating layer 34 formed above. (35) is formed.

Tungsten is then deposited in the bit line contact holes on the barrier metal 35. After that, the planarization process is performed such that the barrier metal 35 and tungsten are formed only in the bit line contact hole. As a result, a tungsten plug 35 is formed on the barrier metal 35 in the bit line contact hole.

Next, as shown in FIG. 4C, tungsten (W) is deposited on the entire surface, and tungsten is dry-etched to be in contact with the tungsten plug 35 of the bit line contact hole and form a one-line direction to form a tungsten bit line 37. do.

As shown in FIG. 4D, a second interlayer insulating film 38 is deposited on the first interlayer insulating film 34 including the tungsten bit line 37.

As shown in FIG. 4E, the second and first interlayer insulating layers 38 and 34 are etched to form node contact holes so that the source region on the other side of the word line 32 having the bit line formed on one side thereof is exposed.

Next, polysilicon is deposited on the second interlayer insulating film 38 including the node contact hole, and then a planarization process is performed to form a poly plug 39 in the node contact hole.

The contact wiring and manufacturing method of the semiconductor device of the present invention as described above has the following effects.

First, it is possible to reduce the production cost by simplifying the process by directly forming the storage node contacts at once instead of forming them twice.

Second, by forming a tungsten plug in the bit line contacts, PT1 and F / T yields can be improved.

Claims (5)

A word line formed in one line direction on the semiconductor substrate A first interlayer dielectric layer having a bit line contact hole formed to expose an impurity region on one side of the word line; Barrier metal formed along the bit line contact hole surface; A first plug formed in the bit line contact hole on the barrier metal; A bit line formed in one line direction to contact the first plug, A second interlayer insulating film formed on the first interlayer insulating film including the bit line, A node contact hole formed in the second and first interlayer dielectric layers so that the impurity regions on the other side of the word line are exposed; And a second plug formed in the node contact hole. The contact wiring of claim 1, wherein the first plug and the bit line are made of tungsten. Forming word lines on a semiconductor substrate in one line direction; Forming a first interlayer insulating film on the entire surface of the semiconductor substrate, Forming a bit line contact hole in the first interlayer insulating layer so that an impurity region on one side of the word line is exposed; Forming a barrier metal along the bit line contact hole surface; Forming a first plug in the bit line contact hole on the barrier metal; Forming a bit line in one line direction to be in contact with the first plug, Forming a second interlayer insulating film on the first interlayer insulating film including the bit line; Forming a node contact hole in the second and first interlayer dielectric layers so that an impurity region on the other side of the word line is exposed; And forming a second plug in the node contact hole. 4. The method of claim 3, wherein the first plug and the bit line are formed of tungsten. The method of claim 3, wherein the barrier metal is formed by sequentially stacking titanium and titanium nitride.