KR100399935B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of obtaining sufficient contact space margin. CONSTITUTION: The first insulating layer(43) and a conductive layer are sequentially formed on a silicon substrate(41). The conductive layer is partially etched by isotropic etching and entirely etched by anisotropic etching, thereby forming a bit line conductive pattern(44a) of polygon structure. The second insulating layer(46) is then formed on the resultant structure. A contact hole is then formed by selectively etching the second and first insulating layer.

Description

Semiconductor device manufacturing method

The present invention relates to a method for securing a space margin when forming a contact hole or a bit line contact hole of a storage node during a manufacturing process of a semiconductor device.

Due to the high integration of semiconductor devices, the space between patterns in the chip is gradually decreasing.

Therefore, SOSCON (Sidewall Oxide Spacer Contact) or Tapered etching process is currently used to secure such space margin when forming contact holes in dynamic RAM (DRAM) devices of more than 64M class. When the contact hole is etched, the bonding layer is exposed to the plasma twice, thereby increasing the damage of the bonding layer. Inclined etching also does not completely solve the short-circuit problem between the two conductors due to reduced spacer margins in the design. In addition, self-aligned contacts are currently being considered, but the production process is difficult due to the complicated process.

Polysilicon and a contact hole forming process and problems thereof in a conventional device manufacturing process will be described with reference to FIGS. 1A through 1B, 2A through 2C, and 3A through 3B. .

First, in FIGS. 1A and 1B, FIG. 1A shows a device isolation film 2 and a gate electrode (not shown) formed on the silicon substrate 1, followed by deposition of an interlayer oxide film 3 and a bit line contact hole (not shown). And a bit line conductive film (using polysilicon and tungsten silicide film) are deposited thereon, and then a bit line mask pattern (not shown) is formed to form the bit line 4 using the mask pattern. After the mask pattern is removed, the interlayer oxide film 6 is deposited again, and the storage node contact mask pattern 7 is formed thereon.

1B is a cross-sectional view of the contact mask pattern 7 removed after anisotropically etching the oxide films 3 and 6 using the contact mask pattern 7 as an etching mask. In this case, there is a problem in that a short space occurs when depositing a storage node conductive film in a subsequent process because the bit line is exposed due to insufficient space margin as shown in "A" of the figure.

2A to 2C show a conventional SOSCON process, and since FIG. 2A is the same as the process of FIG. 1A, description thereof will be omitted. FIG. 2B is a cross-sectional view of the oxide film 8 deposited on the entire structure after the process described in FIG.

FIG. 2C is a cross-sectional view of the oxide film space 8 formed on the sidewall of the contact hole by etching without a mask by a dry etching method. In this case, the spacer margin problem described in FIG. 1 is solved, but the process is complicated, and the bonding layer is exposed to the etching plasma twice during dry etching of the interlayer oxide layer for forming contact holes and front etching for forming the spacer oxide layer. The problem that damage to a bonding layer occurs like "B" of a figure becomes worse. This has a problem in that the refresh characteristics of DRAM are deteriorated.

3A to 3B illustrate a conventional etch process, and since FIG. 3A is the same as the process of FIGS. 1A and 2A, the description thereof will be omitted.

FIG. 3B is a cross-sectional view illustrating a state in which the interlayer oxide films 3 and 6 are inclinedly etched using the contact mask pattern 7 as an etch mask, and a space margin problem is present as shown in FIG. Able to know.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device which secures contact space margin of a highly integrated device and prevents defects and deterioration of the device.

In order to achieve the above object, the present invention comprises the steps of sequentially forming a first insulating layer and a second conductive layer on the first conductive layer; Forming a mask pattern for patterning the second conductive layer on the second conductive layer; Isotropically etching a predetermined thickness of the second conductive layer using the mask pattern as an etch barrier, and anisotropically etching the remaining thickness to form a polygonal second conductive layer pattern having an upper edge cut off; Removing the mask pattern; Forming a second insulating layer on the entire structure; And selectively etching the second insulating layer and the first insulating layer to form a contact hole through which a predetermined portion of the first conductive layer is exposed.

In addition, the present invention comprises the steps of sequentially forming a first insulating layer and a second conductive layer on the first conductive layer; Forming a mask pattern for patterning the second conductive layer on the second conductive layer; The second conductive layer is etched using the mask pattern as an etch barrier, and the second conductive layer is etched while the mask material is eroded by a predetermined etch selectivity, so that the top edge of the second conductive layer is cut off. Forming a conductive layer pattern; Removing the mask pattern; Forming a second insulating layer on the entire structure; And selectively etching the second insulating layer and the first insulating layer to form a contact hole through which a predetermined portion of the first conductive layer is exposed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings 4A to 4E and 5A to 5E.

4A to 4E illustrate a method of forming an electrode in a polygonal shape by eroding a photoresist as a bit line mask when forming a bit line conductive layer pattern.

First, as shown in FIG. 4A, the device isolation layer 42 and the gate electrode (not shown) are formed on the silicon substrate 41 in the same manner as in the prior art. Then, the deposition of the interlayer oxide layer 43 and the bit line contact hole (not shown) are performed. And a bit line conductive film 44 are deposited thereon, and then a photoresist pattern 45 that is a bit line mask pattern is formed.

4B is a cross-sectional view showing a state in which the bit line conductive film 44 is etched using the photoresist pattern 45 as an etch mask and etched with an etch selectivity ratio of 1 to 2: 1 with the photoresist. After etching, the photoresist pattern 45a is eroded to show that the bit line conductive layer pattern 44a has a polygonal shape.

Subsequently, as shown in FIG. 4C, the photoresist pattern 45a remaining after etching is removed.

Subsequently, an interlayer oxide film 46 is deposited as shown in the 4D diagram, and a storage node context mask pattern 47 is formed thereon.

4E is a cross sectional view showing the contact mask pattern 47 being removed after the interlayer oxide films 43 and 46 are inclinedly etched using the contact mask pattern 47 as an etch mask. Likewise, since the space margin of the sidewall of the bit line electrode pattern 44a is sufficient, it can be seen that a short circuit problem does not exist during deposition of the storage node conductive layer in a subsequent process.

5A to 5E illustrate another embodiment of the present invention, in which the conductive film pattern is anisotropically etched using a gas etchant added with SF ₆ and then anisotropically etched after the bit line conductive film pattern is formed. To form a polygon shape.

First, as shown in FIG. 5A, the device isolation layer 52 and the gate electrode (not shown) are formed on the silicon substrate 51 as in the prior art. Then, the deposition of the interlayer oxide layer 53 and the bit line contact hole (not shown) are performed. After forming and depositing the bit line conductive film 54 thereon, the photoresist pattern 55 which is a bit line mask pattern is formed.

Subsequently, the bit line conductive film 54 is etched using the photoresist pattern 55 as an etching mask, and only a part of the thickness of the bit line conductive film 54 is isotropically etched using an etching gas containing SF ₆ gas. Next, as the residual thickness is anisotropically etched, as shown in the drawing, some of the bit line conductive film patterns 54a under the photoresist pattern 55, which is a mask pattern, are isotropically etched to form a polygonal shape as a whole. Shows.

In the case of LRC's TCP (transformer coupled plaslma) equipment, the isotropic etching conditions of the bit line conductive film are 5 ~ 500mT, 100 ~ 1000W Top Power, 30 ~ 500W Bottom Power (10 ~ 150sccm C12, 5 ~ 100sccm N2, 5 ~ 100sccm SF ₆ , 2 ~ 5cm Electrode Gap, 2 ~ 15 Torr He Back Side Pressure, anisotropic etching condition is 5 ~ 500mT, 100 ~ 1000W Top Power ), 30 ~ 500W Bottom Power, 10 ~ l50sccm C12, 3 ~ 50sccm 02, 2 ~ 5cm Electrode Gap, 2 ~ 15Torr He Back Side Pressure.

Subsequently, the photoresist pattern 55 is removed as in FIG. 5C.

Subsequently, an interlayer oxide film 56 is deposited as shown in the 5D diagram, and a storage node contact mask pattern 57 is formed thereon.

Next, FIG. 5E is a cross-sectional view of the interlayer oxide layers 53 and 56 inclinedly etched using the contact mask pattern 57 as an etch mask, and then removing the contact mask pattern 57, denoted by reference numeral “E”. As shown in FIG. 5, the spacer margin of the bit line sidewall is sufficient, so that a short circuit problem does not exist during deposition of the storage conductive layer in a subsequent process.

In the exemplary embodiment of the present invention, the contact process of the storage node has been described as an example. However, the present invention may be applied to all contact processes in semiconductor devices such as DRAM bit line contacts and other SRAMs.

As described above, the present invention is to prevent the short-circuit with the other conductive film that occurs when the semiconductor device is highly integrated during the contact process in the lower process, and thus prevents the improvement of the device's characteristics and accelerates the high integration of the device. have.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope without departing from the technical spirit of the present invention. It will be apparent to those who have knowledge.

1A to 1B is a conventional process of forming a contact hole,

2A to 2C is another conventional contact hole forming process diagram,

3A through 3B or another conventional contact hole forming process diagram,

4A through 4E are contact hole forming process diagrams according to one embodiment of the present invention;

5A to 5E are contact hole forming process diagrams according to another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

41, 51: silicon substrate

42, 52,: device isolation film

43, 53, 46, 56: interlayer oxide film

44, 54: bit line conductive film

45,55 bit line mask (photoresist pattern)

44a, 54a: bit line conductive film pattern

45a, 55a: photoresist pattern

47: Storage Node Context Mask Pattern

Claims (12)

In the semiconductor device manufacturing method, Sequentially forming a first insulating layer and a second conductive layer on the first conductive layer; Forming a mask pattern for patterning the second conductive layer on the second conductive layer; Isotropically etching a predetermined thickness of the second conductive layer using the mask pattern as an etch barrier, and anisotropically etching the remaining thickness to form a polygonal second conductive layer pattern having an upper edge cut off; Removing the mask pattern; Forming a second insulating layer on the entire structure; And Selectively etching the second insulating layer and the first insulating layer to form a contact hole exposing a predetermined portion of the first conductive layer; And selectively etching the second insulating layer and the first insulating layer to form a contact hole, wherein the width of the second insulating layer and the first insulating layer is narrowed toward the lower portion of the contact hole. The method of claim 1, The isotropic etching and the anisotropic etching for forming the conductive layer pattern is a semiconductor device manufacturing method, characterized in that the dry etching in the same equipment. The method of claim 2, And the second conductive layer is a polysilicon layer. The method of claim 3, wherein The isotropic dry etching of the polysilicon layer uses a gas containing at least SF ₆ gas as an etching source gas. The method of claim 2, And said first conductive layer is a semiconductor substrate. The method of claim 5, And the second conductive layer pattern is a gate electrode or a bit line of a dynamic RAM. In the semiconductor device manufacturing method, Sequentially forming a first insulating layer and a second conductive layer on the first conductive layer; Forming a mask pattern for patterning the second conductive layer on the second conductive layer; The second conductive layer is etched using the mask pattern as an etch barrier, and the second conductive layer is etched while the mask material is eroded by a predetermined etch selectivity, so that the upper edge of the second conductive layer is cut off. Forming a conductive layer pattern; Removing the mask pattern; Forming a second insulating layer on the entire structure; And Selectively etching the second insulating layer and the first insulating layer to form a contact hole exposing a predetermined portion of the first conductive layer. The method of claim 7, wherein And selectively etching the second insulating layer and the first insulating layer to form a contact hole, wherein the width of the second insulating layer and the first insulating layer is narrowed toward the lower portion of the contact hole. The method according to claim 7 or 8, The etching method for forming the second conductive layer pattern is a semiconductor device manufacturing method, characterized in that using the etching prescription of the etching selectivity of the mask material and the second conductive layer material is 1: 1 to 2: 1. The method of claim 9, And the second conductive layer is a polysilicon layer. The method of claim 10, And said first conductive layer is a semiconductor substrate. The method of claim 10, And the second conductive layer pattern is a gate electrode or a bit line of a dynamic RAM.