KR100301427B1 - Method of etching semiconductor device provided with hard mask - Google Patents
Method of etching semiconductor device provided with hard mask Download PDFInfo
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- KR100301427B1 KR100301427B1 KR1019990023589A KR19990023589A KR100301427B1 KR 100301427 B1 KR100301427 B1 KR 100301427B1 KR 1019990023589 A KR1019990023589 A KR 1019990023589A KR 19990023589 A KR19990023589 A KR 19990023589A KR 100301427 B1 KR100301427 B1 KR 100301427B1
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- Prior art keywords
- hard mask
- etching
- film
- semiconductor device
- insulating film
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- 238000005530 etching Methods 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 230000003667 anti-reflective effect Effects 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims description 12
- 229910021332 silicide Inorganic materials 0.000 claims description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 3
- 230000001052 transient effect Effects 0.000 claims description 3
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 21
- 229920000642 polymer Polymers 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 229910008486 TiSix Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
본 발명은 하드마스크를 갖는 반도체소자의 식각방법에 관한 것으로, 특히 이 방법은 반도체기판 상부에 게이트 절연막/ 도프트 폴리실리콘/ 티타늄실리사이드/ 비반사막/ 하드마스크용 절연막을 순차적으로 적층하고, 하드마스크용 절연막 상부에 반도체소자의 영역을 정의하기 위한 포토레지스트 패턴을 형성하고, 비반사막을 식각 정지막으로 삼아서 상기 패턴에 의해 드러난 하드마스크용 절연막만을 선택적으로 식각하고, 비반사막과 티타늄실리사이드층 및 폴리실리콘을 동일챔버에서 식각하여 반도체소자 패턴을 형성한 후에 포토레지스트 패턴을 제거한다. 이에 따라, 본 발명은 하드마스크와 비반사막을 동시에 선택식각하지 않고 분리해서 식각하므로써 하드마스크 아래 티타늄실리사이드의 상부면에서 발생하는 폴리머 생성을 최소화하여 정확한 반도체소자의 패턴을 확보할 수 있다.The present invention relates to an etching method of a semiconductor device having a hard mask, and in particular, the method sequentially stacks an insulating film for a gate insulating film / doped polysilicon / titanium silicide / non-reflective film / hard mask on a semiconductor substrate, and then hard mask. A photoresist pattern is formed on the insulating film to define a region of the semiconductor device, and only the hard mask insulating film exposed by the pattern is selectively etched using the non-reflective film as an etch stop film, and the non-reflective film, the titanium silicide layer, and the poly After the silicon is etched in the same chamber to form the semiconductor device pattern, the photoresist pattern is removed. Accordingly, the present invention can secure the accurate pattern of the semiconductor device by minimizing the generation of polymer generated on the upper surface of the titanium silicide under the hard mask by separately etching the hard mask and the anti-reflective film without selective etching.
Description
본 발명은 반도체소자의 제조 공정에 관한 것으로서, 특히 금속실리사이드층을 갖는 반도체소자의 포토레지스트 패턴에 대한 식각 선택비를 높이기 위해 사용되는 하드마스크의 식각 공정시 폴리머 발생을 최소화할 수 있는 하드마스크를 갖는 반도체소자의 식각방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device. In particular, a hard mask capable of minimizing polymer generation during an etching process of a hard mask used to increase an etching selectivity for a photoresist pattern of a semiconductor device having a metal silicide layer is provided. An etching method of a semiconductor device having a.
반도체장치의 고집적화로 소자의 크기가 축소됨에 따라 전기저항이 낮은 전기 배선재료를 요구하고 있으며, 이에 반도체장치의 워드라인 또한 고융점 저저항의 금속 실라사이드막을 사용하여 배선의 저항특성을 낮추고 있다.As the size of the device is reduced due to the high integration of semiconductor devices, electrical wiring materials having low electrical resistance are required. Accordingly, the word lines of semiconductor devices are also using a metal silicide film having a high melting point and low resistance to lower wiring resistance characteristics.
한편, 통상의 텅스텐실리사이드(WSix)보다 비저항(Rs)이 작은 티타늄실리사이드(TiSix)가 적용되고 있는 워드라인 또는 기타 디바이스의 패터닝 공정은 포토레지스트 패턴에 대한 식각 선택비를 보강하거나 상부 디바이스 형성에 필요한 물질을 삽입하는 목적으로 Si3N4이나 SiON 등의 산화/질화물질을 이용하여 하드마스크를 형성하고 있다. 또한, 상기 하드마스크 하부에는 포토레지스트의 미세한 정의를 위해서 비반사막을 추가 삽입하고 있다.Meanwhile, the patterning process of word lines or other devices in which titanium silicide (TiSix), which has a lower specific resistance (Rs) than that of conventional tungsten silicide (WSix), is applied to enhance the etching selectivity of the photoresist pattern or to form the upper device. In order to insert the material, a hard mask is formed using an oxidizing / nitriding material such as Si 3 N 4 or SiON. In addition, an antireflective film is further inserted under the hard mask in order to finely define the photoresist.
도 1a 내지 도 1b는 종래 기술에 의한 하드마스크를 갖는 반도체소자의 식각공정을 나타낸 단면도들이다. 여기서, 반도체소자의 식각 공정은 도프트 폴리실리콘/실리사이드층이 적층된 폴리사이드(polycide)구조의 워드라인 패터닝 공정을 예로 든다.1A to 1B are cross-sectional views illustrating an etching process of a semiconductor device having a hard mask according to the prior art. The etching process of the semiconductor device may be a word line patterning process of a polycide structure in which a doped polysilicon / silicide layer is stacked.
이를 참조하면, 도 1a에 도시된 바와 같이 반도체기판으로서 실리콘기판(10)에 STI(Shallow Trench Isolate) 공정을 실시하여 활성 영역과 분리영역을 정의하는 소자분리막(12)을 형성한 후에, 기판(10) 전면에 게이트 절연막(14)/ 도프트 폴리실리콘층(16)/ 티타늄 실리사이드층(18)/ 비반사막(20)/ 하드마스크용 절연막(22)을 순차적으로 적층한다. 그리고, 상기 하드마스크용 절연막(22) 상부면에 워드라인 영역을 정의하는 포토레지스트 패턴(24)을 형성한다. 여기서, 비반사막(20)은 SiON이며, 하드마스크용 절연막(22)은 산화막 또는 질화막으로 형성한다.Referring to FIG. 1A, after forming a device isolation film 12 that defines an active region and an isolation region by performing a shallow trench isolation (STI) process on a silicon substrate 10 as a semiconductor substrate, the substrate ( 10) The gate insulating film 14, the doped polysilicon layer 16, the titanium silicide layer 18, the anti-reflective film 20, and the hard mask insulating film 22 are sequentially stacked on the entire surface. A photoresist pattern 24 defining a word line region is formed on an upper surface of the hard mask insulating layer 22. Here, the antireflection film 20 is SiON, and the hard mask insulating film 22 is formed of an oxide film or a nitride film.
그 다음, 도 1b에 도시된 바와 같이 동일 챔버에서 상기 포토레지스트 패턴(24)에 맞추어 상기 하드마스크용 절연막(22) 및 비반사막(20)을 동시에 패터닝하여 하드마스크 패턴을 형성한다. 도면에 도시하지는 않았지만, 하드마스크 패턴을 이용하여 하부의 티타늄 실리사이드층(18)에서부터 게이트산화막(14)을 순차적으로 식각하여 반도체 소자의 워드라인을 형성하고 상기 포토레지스트 패턴(24)을 제거한다.Next, as shown in FIG. 1B, the hard mask insulating film 22 and the non-reflective film 20 are simultaneously patterned in accordance with the photoresist pattern 24 in the same chamber to form a hard mask pattern. Although not shown in the drawings, the gate oxide layer 14 is sequentially etched from the lower titanium silicide layer 18 using a hard mask pattern to form a word line of the semiconductor device, and the photoresist pattern 24 is removed.
상기와 같은 종래의 워드라인 패터닝 방법 중에서 포토레지스트 패턴 하부에 있는 하드마스크용 절연막(22)과 비반사막(20)의 식각 방법은 동일한 챔버에서 상기 막들(22,20)의 식각 선택비를 이용하지 않고 동시에 상기 막들(22,20)을 식각한다.In the conventional word line patterning method, the etching method of the hard mask insulating layer 22 and the non-reflective film 20 under the photoresist pattern does not use the etching selectivity of the films 22 and 20 in the same chamber. And simultaneously etch the films 22 and 20.
이때, 토포로지 극복을 위해 비반사막(20)을 과도 식각할 경우 C-F계 CF4/O2/Ar 또는 CF4/CHF3/Ar 등의 식각 가스와 비반사막(20) 및 티타늄실리사이드(18)의 반응에 의해 하부의 티타늄실리사이드(18)의 계면에서는 기존의 텅스텐실리사이드의 경우와 다른 Ti-N-O가 포함된 폴리머(21)가 다량 발생된다.At this time, when the non-reflective film 20 is excessively etched to overcome the topology, the etching gas such as CF-based CF 4 / O 2 / Ar or CF 4 / CHF 3 / Ar, the anti-reflective film 20, and titanium silicide 18 Due to the reaction, a large amount of polymer 21 containing Ti-NO is generated at the interface of the lower titanium silicide 18 than the conventional tungsten silicide.
이러한 비반사막(20) 패턴의 측면 부위에 생성된 폴리머(21)는 후속 티타늄실리사이드층(18)과 폴리실리콘층(16)의 계면에서 식각 마스크로 작용하여 정확한 패터닝을 수행하는데 어렵게 한다.The polymer 21 formed on the side portion of the antireflective film 20 pattern acts as an etching mask at the interface between the subsequent titanium silicide layer 18 and the polysilicon layer 16, thereby making it difficult to perform accurate patterning.
그러므로, 하드마스크 식각공정의 폴리머 발생은 워드라인 패터닝시 사이드월의 거칠기 불량과 경사진 프로파일을 유발하여 소자의 제조 수율을 저하시키는 주요 원인이 된다.Therefore, the generation of polymer in the hard mask etching process is a major cause of lowering the manufacturing yield of the device by causing sidewall roughness and inclined profile during word line patterning.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 비반사막을 식각정지막으로 하고 하드마스크만을 선택 식각한 후에 티타늄실리사이드/폴리실리콘의 식각 챔버에서 비반사막을 식각하고, 인시튜로 나머지 티타늄실리사이드층/폴리실리콘층을 선택 식각함으로써 반도체소자의 패터닝시 하드마스크의 측면 부위에서 발생하는 폴리머 생성을 최소화하는 하드마스크를 갖는 반도체소자의 식각 방법을 제공하는데 있다.An object of the present invention is to etch the anti-reflection film in the etching chamber of the titanium silicide / polysilicon after the etching of the non-reflective film to the etching stop film and selective etching only the hard mask in order to solve the above problems of the prior art, and remaining in situ By selectively etching the titanium silicide layer / polysilicon layer to provide a method of etching a semiconductor device having a hard mask to minimize the generation of polymer generated in the side portion of the hard mask during the patterning of the semiconductor device.
도 1a 내지 도 1b는 종래기술에 의한 하드마스크를 갖는 반도체소자의 식각공정을 나타낸 단면도들,1A to 1B are cross-sectional views illustrating an etching process of a semiconductor device having a hard mask according to the prior art;
도 2a 내지 도 2c는 본 발명에 따른 하드마스크를 갖는 반도체소자의 식각방법을 설명하기 위한 공정 순서도.2A to 2C are process flowcharts illustrating an etching method of a semiconductor device having a hard mask according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
100: 실리콘기판 102: 소자분리막100: silicon substrate 102: device isolation film
104: 게이트 절연막 106: 도프트 폴리실리콘층104: gate insulating film 106: doped polysilicon layer
108: 티타늄실리사이드층 110: 비반사막108: titanium silicide layer 110: antireflective film
112: 하드마스크용 절연막 114: 포토레지스트 패턴112: insulating film for hard mask 114: photoresist pattern
상기 목적을 달성하기 위하여 본 발명은 하드 마스크를 갖는 폴리사이드 구조의 반도체소자를 패터닝하는 공정에 있어서, 반도체기판 상부에 게이트 절연막을 적층하고 그 위에 도프트 폴리실리콘 및 금속실리사이드를 순차적으로 증착하는 단계와, 금속실리사이드층 상부에 순차적으로 비반사막 및 하드마스크용 절연막을 형성하는 단계와, 하드마스크용 절연막 상부에 반도체소자의 영역을 정의하기 위한 포토레지스트 패턴을 형성하는 단계와, 비반사막을 식각 정지막으로 삼아서 상기 패턴에 의해 드러난 하드마스크용 절연막만을 선택적으로 식각하는 단계와, 이후 금속실리사이드층/도프트 폴리실리콘층이 식각될 챔버에서 하드마스크용 절연막 패턴에 맞추어 하부의 비반사막을 식각하는 단계와, 비반사막의 식각 챔버와 동일한 챔버에서 적층된 금속실리사이드층과 폴리실리콘층을 패터닝하여 반도체소자 패턴을 형성하는 단계와, 포토레지스트 패턴을 제거하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for patterning a semiconductor device having a polyside structure having a hard mask, comprising: depositing a gate insulating film on a semiconductor substrate and sequentially depositing doped polysilicon and metal silicide on the semiconductor substrate; And sequentially forming an antireflective film and a hard mask insulating film over the metal silicide layer, forming a photoresist pattern for defining a region of a semiconductor device on the hard mask insulating film, and etching off the antireflective film. Selectively etching only the hardmask insulating film exposed by the pattern as a film, and then etching the lower antireflective film in accordance with the hardmask insulating film pattern in the chamber in which the metal silicide layer / doped polysilicon layer is to be etched. And, in the same chamber as the etching chamber of the anti-reflective film Patterning the layered metal silicide layer and the polysilicon layer to form a semiconductor device pattern, and removing the photoresist pattern.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 하드마스크를 갖는 반도체소자의 식각방법을 설명하기 위한 공정 순서도로서, 이를 참조하면, 본 발명의 폴리사이드 워드라인의 제조 공정은 다음과 같다.2A to 2C are process flowcharts illustrating an etching method of a semiconductor device having a hard mask according to the present invention. Referring to this, the manufacturing process of the polyside word line of the present invention is as follows.
우선, 도 2a에 도시된 바와 같이, 소자분리막(102)이 형성된 실리콘기판(100) 상부에 게이트 절연막(104)을 적층하고 그 위에 도프트 폴리실리콘층(106) 및 금속실리사이드로서 티타늄실리사이드층(108)을 순차적으로 적층한다. 그리고, 상기 티타늄실리사이드층(108) 상부에 순차적으로 비반사막(110)과 하드마스크용 절연막(112)을 형성한 후에 그 위에 워드라인 영역을 정의하는 포토레지스트 패턴(114)을 형성한다. 여기서, 비반사막(110)은 SiON이며, 하드마스크용 절연막(112)은 산화막 또는 질화막으로 형성한다.First, as shown in FIG. 2A, the gate insulating film 104 is stacked on the silicon substrate 100 on which the device isolation film 102 is formed, and a doped polysilicon layer 106 and a titanium silicide layer as a metal silicide ( 108) are sequentially stacked. In addition, after the anti-reflective film 110 and the hard mask insulating film 112 are sequentially formed on the titanium silicide layer 108, a photoresist pattern 114 defining a word line region is formed thereon. Here, the antireflective film 110 is SiON, and the hard mask insulating film 112 is formed of an oxide film or a nitride film.
그 다음, 상기 비반사막(110)을 식각 정지막으로 삼아서 상기 포토레지스트 패턴(114)에 의해 드러난 하드마스크용 절연막(112)만을 선택적으로 식각한다. 이때, 상기 하드마스크용 절연막(112)과 비반사막(110)의 식각 선택비는 3:1 이상으로 조정하고 CxHyFz 가스(CHF3, CH3F, C2F6또는 C4F8)를 사용한다. 또한, 상기 하드마스크용 절연막(112)의 식각 공정시 비반사막(110)의 식각 잔여물을 방지하기 위하여 과도식각을 20∼80%로 실시하는 것이 바람직하다.Thereafter, only the hard mask insulating layer 112 exposed by the photoresist pattern 114 is selectively etched using the anti-reflective film 110 as an etch stop film. At this time, the etching selectivity of the hard mask insulating film 112 and the non-reflective film 110 is adjusted to 3: 1 or more and using CxHyFz gas (CHF 3 , CH 3 F, C 2 F 6 or C 4 F 8 ) do. In addition, in order to prevent the etching residue of the non-reflective film 110 during the etching process of the hard mask insulating film 112, it is preferable to perform the transient etching to 20 to 80%.
이로 인해, 상기 식각 공정시 포토레지스트 패턴(114)의 얇더라도 상기 하드마스크용 절연막(112)을 정확하게 포토레지스트 패턴(114)에 정렬하여 식각할 수 있다.Therefore, even when the photoresist pattern 114 is thin during the etching process, the hard mask insulating layer 112 may be accurately aligned with the photoresist pattern 114 to be etched.
이어서, 도 2b에 도시된 바와 같이, 상기 식각 공정과는 다른 반응 챔버(티타늄 실리사이드/폴리실리콘층 식각용)에서 패터닝된 하드마스크용 절연막 패턴(112)에 맞추어 비반사막(110)을 식각한다. 이때, 상기 비반사막(110)의 식각 공정은 식각 단차를 극복하기 위하여 과도식각을 20%이상 실시하는 것이 바람직하다. 본 발명에 따라 하드마스크용 절연막(112)과 비반사막(110)을 구별하여 식각할 경우 비반사막 패턴(110)의 측벽 부분(111), 즉 티타늄실리사이드층이 노출된 부분에 폴리머 발생이 억제된다.Subsequently, as shown in FIG. 2B, the antireflective film 110 is etched according to the insulating layer pattern 112 for hard mask patterned in a reaction chamber (for titanium silicide / polysilicon layer etching) different from the etching process. In this case, the etching process of the anti-reflective film 110 is preferably performed 20% or more of the transient etching to overcome the etching step. According to the present invention, when the hard mask insulating film 112 and the non-reflective film 110 are distinguished and etched, the generation of polymer is suppressed in the sidewall portion 111 of the non-reflective film pattern 110, that is, the portion where the titanium silicide layer is exposed. .
도 2c에 도시된 바와 같이, 상기 비반사막(110)의 식각 공정이 진행된 동일한 반응챔버에서 인시튜(in-situ)로 상기 티타늄실리사이드층(108)과 폴리실리콘층(106)을 동시에 선택식각하여 워드라인 패턴을 형성한다. 그리고, 상기 포토레지스트 패턴(114)을 제거한다.As shown in FIG. 2C, the titanium silicide layer 108 and the polysilicon layer 106 are simultaneously etched in-situ in the same reaction chamber in which the non-reflective film 110 is etched. A word line pattern is formed. In addition, the photoresist pattern 114 is removed.
그러므로, 본 발명은 하드마스크의 산화막 내지 질화막을 식각한 후에 티타늄실리사이드/폴리실리콘 식각 챔버에서 비반사용 SiON막의 식각 공정을 진행하여 이를 제거하고, 인시튜로 티타늄실리사이드/폴리실리콘층을 식각하기 때문에 하드마스크 및 비반사 동시 식각으로 인해 발생되는 폴리머 생성을 최소화하여 워드라인층(티타늄실리사이드/폴리실리콘) 패터닝 공정의 정확성을 높인다.Therefore, in the present invention, after etching the oxide or nitride film of the hard mask, the non-reflective SiON film is etched and removed from the titanium silicide / polysilicon etching chamber, and the titanium silicide / polysilicon layer is etched in situ. Minimize polymer production due to simultaneous mask and antireflection etch to increase the accuracy of the wordline layer (titanium silicide / polysilicon) patterning process.
상기한 바와 같이 본 발명은, 포토레지스트 패턴에 대한 식각 선택비를 보강하기 위하여 하드마스크 및 비반사막을 이용할 경우 F계 가스의 조합에 의해서 하드마스크만을 선택적으로 패터닝한 후에 비반사막을 티타늄실리사이드/폴리실리콘의 식각 단계에서 제거한다.As described above, in the present invention, when the hard mask and the anti-reflective film are used to reinforce the etching selectivity with respect to the photoresist pattern, the non-reflective film may be titanium silicide / poly after selectively patterning only the hard mask by the combination of the F-based gas. Removed at the etching stage of silicon.
따라서, 본 발명은 하드마스크 패턴의 폴리머 생성을 최소화하고 하드마스크의 식각시 포토레지스트에 대한 선택비를 높일 수 있어 포토레지스트 장벽 식각에 대한 마진을 확보할 뿐만 아니라 정확한 반도체소자의 마스크 패턴을 얻을 수 있어 그 제조 공정의 수율을 높일 수 있다.Therefore, the present invention can minimize the generation of polymer of the hard mask pattern and increase the selectivity for the photoresist during the etching of the hard mask, thereby securing a margin for the photoresist barrier etching and obtaining an accurate mask pattern of the semiconductor device. Thereby, the yield of the manufacturing process can be improved.
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