KR20010058959A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20010058959A KR20010058959A KR1019990066335A KR19990066335A KR20010058959A KR 20010058959 A KR20010058959 A KR 20010058959A KR 1019990066335 A KR1019990066335 A KR 1019990066335A KR 19990066335 A KR19990066335 A KR 19990066335A KR 20010058959 A KR20010058959 A KR 20010058959A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 92
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 239000011229 interlayer Substances 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 23
- 230000001681 protective effect Effects 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 10
- 239000007789 gas Substances 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 5
- 229910017855 NH 4 F Inorganic materials 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 239000002904 solvent Substances 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 description 26
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910004541 SiN Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 누설 전류 발생을 억제하고 콘택 저항을 감소시켜 소자의 동작 특성 및 수율을 향상시키는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that suppresses leakage current generation and reduces contact resistance to improve operating characteristics and yield of the device.
종래의 기술에 따른 반도체 소자의 제조 방법중 콘택홀 형성 방법은 도 1a에서와 같이, 반도체 기판(11)상에 열산화 공정으로 제 1 산화막을 성장시킨 다음, 상기 제 1 산화막상에 다결정 실리콘층과 하드 마스크(Hard Mask)층인 제 1 질화막(14)을 차례로 형성한다.In the method for forming a semiconductor device according to the related art, a method of forming a contact hole includes growing a first oxide film on a semiconductor substrate 11 by a thermal oxidation process as shown in FIG. 1A, and then forming a polycrystalline silicon layer on the first oxide film. And the first nitride film 14 which is a hard mask layer are formed in this order.
여기서, 상기 제 1 질화막(14)은 후공정에서 산화막 식각에 대한 보호막으로 사용되며 SiN, SiON 및 실리콘(Si)이 다량 함유된 SiON중 하나로 형성한다.Here, the first nitride film 14 is used as a protective film for oxide etching in a later process and is formed of one of SiON containing SiN, SiON, and silicon (Si) in a large amount.
그리고, 상기 제 1 질화막(14)상에 제 1 감광막을 도포하고, 상기 제 1 감광막을 워드 라인(Word Line)이 형성될 부위에만 남도록 선택적으로 노광 및 현상한다.Then, a first photosensitive film is coated on the first nitride film 14, and the first photosensitive film is selectively exposed and developed so that only the portion where the word line is to be formed remains.
이어, 상기 선택적으로 노광 및 현상된 제 1 감광막을 마스크로 상기 제 1 질화막(14), 다결정 실리콘층 및 제 1 산화막을 선택적으로 식각하여 게이트 산화막(12)과 워드 라인(13)을 형성한 후, 상기 제 1 감광막을 제거한다.Subsequently, the first nitride film 14, the polycrystalline silicon layer, and the first oxide film are selectively etched using the selectively exposed and developed first photoresist film to form a gate oxide film 12 and a word line 13. , The first photosensitive film is removed.
그 다음, 상기 워드 라인(13)을 포함한 반도체 기판(11)상에 제 2 질화막을 형성하고, 상기 제 2 질화막을 에치 백(Etch Back)하여 상기 워드 라인(13)과 제 1 질화막(14)양측의 반도체 기판(11)상에 제 2 질화막 측벽(15)을 형성한다.Next, a second nitride film is formed on the semiconductor substrate 11 including the word line 13, and the word nitride 13 is etched back by etching the second nitride film. The second nitride film sidewall 15 is formed on the semiconductor substrate 11 on both sides.
도 1b에서와 같이, 상기 제 2 질화막 측벽(15)을 포함한 반도체 기판(11)상에 층간 산화막(16)을 형성한다.As shown in FIG. 1B, an interlayer oxide film 16 is formed on the semiconductor substrate 11 including the second nitride film sidewall 15.
그리고, 상기 층간 산화막(16)상에 제 2 감광막(17)을 도포한 후, 상기 제 2 감광막(17)을 콘택홀이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.After the second photoresist film 17 is coated on the interlayer oxide film 16, the second photoresist film 17 is selectively exposed and developed to be removed only at a portion where a contact hole is to be formed.
이어, 상기 선택적으로 노광 및 현상된 제 2 감광막(17)을 마스크로 상기 층간 산화막(16)과 제 1 질화막(14)을 선택적으로 식각하여 다수 개의 콘택홀(18)을 형성한다.Subsequently, the interlayer oxide layer 16 and the first nitride layer 14 are selectively etched using the selectively exposed and developed second photoresist layer 17 to form a plurality of contact holes 18.
그러나 종래의 반도체 소자의 제조 방법은 층간 산화막과 워드 라인의 하드 마스크층인 질화막을 식각하여 반도체 기판과 워드 라인에 콘택홀을 동시에 형성하므로 상기 층간 산화막 두께가 균일하지 않고 상기 질화막이 실리콘에 대해 식각 선택비가 없기 때문에 콘택홀 특성 악화 및 반도체 기판이 손상되는 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device, since the contact hole is simultaneously formed in the semiconductor substrate and the word line by etching the interlayer oxide film and the nitride film as the hard mask layer of the word line, the thickness of the interlayer oxide film is not uniform and the nitride film is etched with respect to silicon. Since there is no selectivity, there is a problem that the contact hole characteristics deteriorate and the semiconductor substrate is damaged.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 워드 라인을 포함한 전면에 Al2O3막을 형성한 다음 콘택홀을 형성하여 콘택홀 특성 악화 및 반도체 기판의 손상 방지하므로 소자의 동작 특성 및 수율을 향상시키는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, by forming an Al2O3 film on the entire surface including a word line and then forming a contact hole to prevent deterioration of contact hole characteristics and damage to the semiconductor substrate, thereby improving the operation characteristics and yield of the device. It is an object of the present invention to provide a method for manufacturing a device.
도 1a와 도 1b는 종래의 기술에 따른 반도체 소자의 제조 방법중 콘택홀 형성 방법을 나타낸 공정 단면도1A and 1B are cross-sectional views illustrating a method of forming a contact hole in a method of manufacturing a semiconductor device according to the related art.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 제조 방법중 콘택홀 형성 방법을 나타낸 공정 단면도2A through 2E are cross-sectional views illustrating a method of forming a contact hole in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
11: 반도체 기판 12: 게이트 산화막11: semiconductor substrate 12: gate oxide film
13: 워드 라인 14: 제 1 질화막13: word line 14: first nitride film
15: 제 2 질화막 측벽 16: 층간 산화막15: second nitride film sidewall 16: interlayer oxide film
17: 제 2 감광막 18: 콘택홀17: second photosensitive film 18: contact hole
31: Al2O3층 32: 제 2 다결정 실리콘층31: Al2O3 layer 32: Second polycrystalline silicon layer
본 발명의 반도체 소자의 제조 방법은 기판을 마련하는 단계, 상기 기판상에 게이트 절연막을 내재하고 상부 부위에 하드 마스크층과 그 양측에 절연막 측벽을 갖는 다수 개의 워드 라인을 형성하는 단계, 상기 워드 라인을 포함한 반도체 기판상에 기판 보호 절연층을 형성하는 단계, 상기 기판 보호 절연층상에 층간 절연막과 도전층을 형성하는 단계, 상기 워드 라인상의 기판 보호 절연층을 식각 종말점으로 하여 콘택홀이 형성될 부위의 도전층과 층간 절연막을 식각하는 단계, 상기 식각된 도전층과 층간 절연막을 마스크로 상기 워드 라인상의 기판 보호 절연층을식각하는 단계, 상기 식각된 도전층, 층간 절연막 및 기판 보호 절연층을 마스크로 상기 워드 라인상의 하드 마스크층을 식각하여 상기 워드 라인에 콘택홀을 형성하고 상기 기판상의 기판 보호 절연층을 식각 종말점으로 상기 식각된 도전층을 마스크로 상기 층간 절연막을 식각하는 단계, 상기 식각된 도전층과 층간 절연층을 마스크로 상기 기판상의 기판 보호 절연층을 식각하여 상기 기판에 콘택홀을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of manufacturing a semiconductor device of the present invention includes the steps of: providing a substrate, forming a plurality of word lines having a gate insulating film on the substrate, a plurality of word lines having a hard mask layer on an upper portion thereof, and insulating film sidewalls on both sides thereof; Forming a substrate protective insulating layer on a semiconductor substrate including a semiconductor substrate, forming an interlayer insulating layer and a conductive layer on the substrate protective insulating layer, and forming a contact hole using the substrate protective insulating layer on the word line as an etching end point. Etching the conductive layer and the interlayer insulating film of the substrate; etching the substrate protective insulating layer on the word line using the etched conductive layer and the interlayer insulating film as a mask; masking the etched conductive layer, the interlayer insulating film, and the substrate protective insulating layer Etching a hard mask layer on the word line to form a contact hole in the word line. Etching the interlayer insulating film using the etched conductive layer as a mask as an end point of etching the plate protective insulating layer, and etching a substrate protective insulating layer on the substrate using the etched conductive layer and the interlayer insulating layer as a mask to contact the substrate. And forming a hole.
상기와 같은 본 발명에 따른 반도체 소자의 제조 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention as follows.
본 발명의 실시 예에 따른 반도체 소자의 제조 방법중 콘택홀 형성 방법은 도 2a에서와 같이, 반도체 기판(11)상에 열산화 공정으로 제 1 산화막을 성장시킨 다음, 상기 제 1 산화막상에 제 1 다결정 실리콘층과 하드 마스크층인 제 1 질화막(14)을 차례로 형성한다.In the method for forming a contact hole in the method of manufacturing a semiconductor device according to the embodiment of the present invention, as shown in FIG. 1 polycrystalline silicon layer and the first nitride film 14 which is a hard mask layer are formed in order.
여기서, 상기 제 1 질화막(14)은 후공정에서 산화막 식각에 대한 보호막으로 사용되며 SiN, SiON 및 실리콘이 다량 함유된 SiON중 하나로 형성한다.Here, the first nitride film 14 is used as a protective film for oxide etching in a later step and is formed of one of SiON containing SiN, SiON, and silicon.
그리고, 상기 제 1 질화막(14)상에 제 1 감광막을 도포하고, 상기 제 1 감광막을 워드 라인이 형성될 부위에만 남도록 선택적으로 노광 및 현상한다.Then, a first photosensitive film is coated on the first nitride film 14, and the first photosensitive film is selectively exposed and developed so that only the portion where the word line is to be formed remains.
이어, 상기 선택적으로 노광 및 현상된 제 1 감광막을 마스크로 상기 제 1 질화막(14), 제 1 다결정 실리콘층 및 제 1 산화막을 선택적으로 식각하여 게이트 산화막(12)과 워드 라인(13)을 형성한 후, 상기 제 1 감광막을 제거한다.Subsequently, the first nitride layer 14, the first polycrystalline silicon layer, and the first oxide layer are selectively etched using the selectively exposed and developed first photoresist layer to form a gate oxide layer 12 and a word line 13. After that, the first photosensitive film is removed.
그 다음, 상기 워드 라인(13)을 포함한 반도체 기판(11)상에 제 2 질화막을형성하고, 상기 제 2 질화막을 에치 백하여 상기 워드 라인(13)과 제 1 질화막(14)양측의 반도체 기판(11)상에 제 2 질화막 측벽(15)을 형성한다.Next, a second nitride film is formed on the semiconductor substrate 11 including the word line 13, the second nitride film is etched back, and the semiconductor substrates on both the word line 13 and the first nitride film 14 are formed. The second nitride film sidewall 15 is formed on (11).
그리고, 상기 제 2 질화막 측벽(15)을 포함한 반도체 기판(11)상에 Al2O3층(31)을 형성한다.An Al 2 O 3 layer 31 is formed on the semiconductor substrate 11 including the second nitride film sidewall 15.
도 2b에서와 같이, 상기 Al2O3층(31)상에 층간 산화막(16)과 제 2 다결정 실리콘층(32)을 형성한다.As shown in FIG. 2B, an interlayer oxide film 16 and a second polycrystalline silicon layer 32 are formed on the Al 2 O 3 layer 31.
여기서, 상기 제 2 다결정 실리콘층(32) 대신에 티타늄(Ti)/질화티타늄(TiN)층으로 형성할 수 있다.In this case, the second polycrystalline silicon layer 32 may be formed of a titanium (Ti) / titanium nitride (TiN) layer.
그리고, 상기 제 2 다결정 실리콘층(32)상에 제 2 감광막(17)을 도포한 후, 상기 제 2 감광막(17)을 콘택홀이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.After the second photoresist film 17 is coated on the second polycrystalline silicon layer 32, the second photoresist film 17 is selectively exposed and developed to be removed only at a portion where a contact hole is to be formed.
이어, 상기 제 1 질화막(14)상의 Al2O3층(31)을 식각 종말점으로 그리고 상기 선택적으로 노광 및 현상된 제 2 감광막(17)을 마스크로 상기 제 2 다결정 실리콘층(32)과 층간 산화막(16)을 선택적으로 식각한다.Subsequently, the second polycrystalline silicon layer 32 and the interlayer oxide layer 16 are formed by using the Al 2 O 3 layer 31 on the first nitride layer 14 as an etching end point and using the selectively exposed and developed second photosensitive layer 17 as a mask. Selectively etch).
여기서, 상기 층간 산화막(16)을 He, Ne, Ar 및 Xe 등의 불활성 가스와 혼합된 C-F 계열의 가스 또는 C-H-F 계열의 가스 그리고 Cl2 가스중 하나의 가스를 사용하여 식각한다.The interlayer oxide layer 16 is etched using one of a C-F-based gas, a C-H-F-based gas, and a Cl 2 gas mixed with an inert gas such as He, Ne, Ar, and Xe.
도 2c에서와 같이, 상기 제 2 감광막(17)을 제거하고, H2O2/H2SO4/DI 혼합 용액을 사용하거나 NH4F/HF/DI 또는 솔벤트(Solvent) 등을 사용한 제 1 세정 공정에 의해 상기 제 1 질화막(14)상에 노출된 Al2O3층(31)을 식각한다.As shown in FIG. 2C, the second photosensitive layer 17 is removed, and the first nitride layer is formed by using a H 2 O 2 / H 2 SO 4 / DI mixed solution or a first cleaning process using NH 4 F / HF / DI, solvent, or the like. The Al 2 O 3 layer 31 exposed on (14) is etched.
여기서, 상기 제 1 세정 공정은 상기 제 2 감광막(17) 제거 후에 하는 공정이다.The first cleaning step is a step performed after the second photosensitive film 17 is removed.
도 2d에서와 같이, 상기 선택적으로 식각된 제 2 다결정 실리콘층(32), 층간 산화막(16) 및 Al2O3층(31)을 마스크로 상기 제 1 질화막(14)을 식각하므로 상기 워드 라인(13)에 콘택홀을 형성시키고, 상기 반도체 기판(11)상의 Al2O3층(31)을 식각 종말점으로 그리고 제 2 다결정 실리콘층(32)을 마스크로 상기 층간 산화막(16)을 식각한다.As shown in FIG. 2D, the first nitride layer 14 is etched using the selectively etched second polycrystalline silicon layer 32, the interlayer oxide layer 16, and the Al 2 O 3 layer 31 as the word line 13. The interlayer oxide layer 16 is etched by forming a contact hole in the Al 2 O 3 layer 31 on the semiconductor substrate 11 as an etching end point and using the second polycrystalline silicon layer 32 as a mask.
도 2e에서와 같이, 상기 노출된 Al2O3층(31)을 H2O2/H2SO4/DI 혼합 용액을 사용하거나 NH4F/HF/DI 또는 솔벤트 등을 사용한 제 2 세정 공정에 의해 제거하여 상기 반도체 기판(11)에 콘택홀을 형성한다.As shown in FIG. 2E, the exposed Al 2 O 3 layer 31 is removed by using a H 2 O 2 / H 2 SO 4 / DI mixed solution or by a second cleaning process using NH 4 F / HF / DI, solvent, or the like, to the semiconductor substrate 11. A contact hole is formed.
여기서, 상기 제 2 세정 공정은 후공정에서 금속층의 형성 공정 전에 하는 공정이다.The second cleaning step is a step performed before the metal layer formation step in a later step.
본 발명의 반도체 소자의 제조 방법은 워드 라인을 포함한 전면에 Al2O3막을 형성한 다음 콘택홀을 형성하므로, 콘택홀 형성시 필드 산화막의 식각 방지 및 반도체 기판의 손상을 방지하여 누설 전류 발생을 억제하고 콘택 저항을 감소시켜 소자의 동작 특성 및 수율을 향상시키는 효과가 있다.In the method of manufacturing a semiconductor device of the present invention, since the Al 2 O 3 film is formed on the entire surface including the word line, and then the contact hole is formed, the formation of the contact hole prevents the etching of the field oxide film and the damage of the semiconductor substrate to prevent the occurrence of leakage current and to prevent the contact. Reducing the resistance has the effect of improving the operating characteristics and yield of the device.
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KR100607348B1 (en) * | 2004-09-10 | 2006-07-28 | 주식회사 하이닉스반도체 | Method of forming a metal line in a semiconductor device |
KR100709564B1 (en) * | 2004-10-27 | 2007-04-20 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
KR101015143B1 (en) * | 2003-07-12 | 2011-02-16 | 주식회사 하이닉스반도체 | Method for reducing plasma damage to a gate oxide of semiconductor device |
KR20220138665A (en) * | 2021-04-06 | 2022-10-13 | 연세대학교 산학협력단 | Method for forming high-efficiency hydrogen barrier control film through artificial composition control in thin film based on atomic layer deposition |
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KR100464391B1 (en) * | 1997-07-23 | 2005-02-28 | 삼성전자주식회사 | Method of forming contact holes of a semiconductor device comprising a process of dry etching for SiON layer |
KR100461334B1 (en) * | 1997-12-31 | 2005-05-03 | 주식회사 하이닉스반도체 | Contact hole formation method of semiconductor device |
JPH11195704A (en) * | 1998-01-05 | 1999-07-21 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
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KR101015143B1 (en) * | 2003-07-12 | 2011-02-16 | 주식회사 하이닉스반도체 | Method for reducing plasma damage to a gate oxide of semiconductor device |
KR100607348B1 (en) * | 2004-09-10 | 2006-07-28 | 주식회사 하이닉스반도체 | Method of forming a metal line in a semiconductor device |
KR100709564B1 (en) * | 2004-10-27 | 2007-04-20 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
KR20220138665A (en) * | 2021-04-06 | 2022-10-13 | 연세대학교 산학협력단 | Method for forming high-efficiency hydrogen barrier control film through artificial composition control in thin film based on atomic layer deposition |
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