KR20040051229A - Method for fabrication of semiconductor device with tungsten-silicide gate electrode - Google Patents
Method for fabrication of semiconductor device with tungsten-silicide gate electrode Download PDFInfo
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- KR20040051229A KR20040051229A KR1020020079124A KR20020079124A KR20040051229A KR 20040051229 A KR20040051229 A KR 20040051229A KR 1020020079124 A KR1020020079124 A KR 1020020079124A KR 20020079124 A KR20020079124 A KR 20020079124A KR 20040051229 A KR20040051229 A KR 20040051229A
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- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 title claims abstract description 43
- 229910021342 tungsten silicide Inorganic materials 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 31
- 230000002093 peripheral effect Effects 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 텅스텐실리사이드 게이트전극을 구비하는 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a tungsten silicide gate electrode.
최근에 반도체 소자가 고집적화됨에 따라 소스 및 드레인영역으로 이용되는 불순물영역과 게이트전극의 폭이 감소되고 있다. 이에 따라, 반도체소자는 불순물영역의 접촉 저항 및 게이트전극의 시트저항(Sheet resistance; Rs)이 증가하여 동작 속도가 저하되는 문제점이 발생되었다.Recently, as semiconductor devices have been highly integrated, the widths of impurity regions and gate electrodes used as source and drain regions have been reduced. Accordingly, the semiconductor device has a problem in that an operating speed decreases due to an increase in contact resistance of an impurity region and sheet resistance (Rs) of a gate electrode.
그러므로, 반도체소자 내의 소자들의 배선을 알루미늄 합금 및 텅스텐 등의 저저항 물질로 형성하거나, 또는, 게이트전극과 같이 폴리실리콘막으로 형성하는 경우에 실리사이드층(silicide)을 형성하여 저항을 감소시킨다.Therefore, when the wirings of the elements in the semiconductor element are formed of a low resistance material such as aluminum alloy and tungsten, or formed of a polysilicon film such as a gate electrode, a silicide layer is formed to reduce the resistance.
도 1은 종래 기술에 따른 게이트전극 형성 방법을 도시한 공정 단면도이다.1 is a process cross-sectional view showing a gate electrode forming method according to the prior art.
도 1에 도시된 바와 같이, 셀지역과 주변지역이 정의된 반도체 기판(11) 상에 게이트절연막(12)을 형성하고, 게이트절연막(12) 상에 폴리실리콘막(13)과 텅스텐실리사이드막(14)을 증착한 후, 텅스텐실리사이드막(14) 상에 하드마스크용 질화막(15)을 형성한다. 질화막(15) 상에 감광막(16)을 증착하고, 노광 및 현상 공정을 이용하여 패터닝한 후, 패터닝된 감광막(16)을 마스크로 이용하여 질화막(15)을 선택적으로 식각한다.As shown in FIG. 1, a gate insulating film 12 is formed on a semiconductor substrate 11 in which a cell region and a peripheral region are defined, and a polysilicon film 13 and a tungsten silicide film ( 14), a hard mask nitride film 15 is formed on the tungsten silicide film 14. After the photosensitive film 16 is deposited on the nitride film 15 and patterned using an exposure and development process, the nitride film 15 is selectively etched using the patterned photosensitive film 16 as a mask.
도 1b에 도시된 바와 같이, 패터닝된 감광막(16)을 제거하고, 세정 공정을 실시한 후, 질화막(15)을 마스크로 이용하여 ICP(Inductively Coupled Plasma) 방법으로 SF6/Cl2/O2/N2을 베이스로 하여 텅스텐실리사이드막(14)을 식각한다.As shown in FIG. 1B, after the patterned photoresist film 16 is removed, the cleaning process is performed, and the SF 6 / Cl 2 / O 2 / The tungsten silicide film 14 is etched based on N 2 .
이때, 텅스텐실리사이드막(14) 식각시 패턴이 조밀한 셀지역이 상대적으로 조밀하지 않는 주변지역에 비해 식각속도가 현저히 떨어지고, 이로 인해 셀지역의 텅스텐실리사이드막(14)의 식각이 완료되는 시점에서 주변지역은 폴리실리콘막(13)의 일부가 식각된다.At this time, the etching speed of the tungsten silicide layer 14 is significantly lower than that of the peripheral region where the pattern is denser, and thus, the etching time of the tungsten silicide layer 14 in the cell region is completed. In the peripheral area, part of the polysilicon film 13 is etched.
도 1c에 도시된 바와 같이, 텅스텐실리사이드막(14) 식각후 드러나는 폴리실리콘막을 연속해서 식각하여 게이트전극을 형성한다. 이때, 폴리실리콘막(13) 식각시 패턴이 조밀한 셀지역이 상대적으로 조밀하지 않는 주변지역에 비해 식각속도가 현저히 떨어져, 셀지역의 폴리실리콘막(13)의 식각이 완료되는 시점에서 주변지역은 폴리실리콘막(13)은 모두 식각되고 나서도 플라즈마에 계속 노출되므로 어택(Attack; X)을 받는다. 더욱이, 도 1b에서 나타난 바와 같이, 텅스텐실리사이드막(14) 식각시 일부가 식각되어 있었으므로 어택(X)은 더욱 증가되는 문제가 있다.As illustrated in FIG. 1C, the polysilicon layer exposed after etching the tungsten silicide layer 14 is continuously etched to form a gate electrode. At this time, the etching speed of the polysilicon film 13 is significantly lower than that of the peripheral area where the cell pattern having a dense pattern is relatively dense, and the peripheral area at the time when the etching of the polysilicon film 13 of the cell area is completed is completed. The silver polysilicon film 13 is continuously exposed to the plasma even after all are etched and thus receives an attack (X). Furthermore, as shown in FIG. 1B, since part of the tungsten silicide layer 14 is etched, the attack X is further increased.
전술한 바와 같은, 폴리실리콘막 어택은 소자의 디자인룰이 100nm 이하로 줄어들면서 그 정도가 더욱 심해지고 있으며, 현재 100nm 디자인룰에서 식각속도는 주변지역에 비해 셀지역은 약 50%∼60% 정도로 매우 낮다.As described above, the polysilicon film attack becomes more severe as the device's design rule is reduced to 100 nm or less, and the etching speed of the 100 nm design rule is about 50% to 60% of the cell area compared to the surrounding area. Very low
따라서, 셀지역에 있는 조밀한 패턴을 식각하기 위해서는 주변지역에 있는 독립 패턴이 과도하게 오랜 시간동안 플라즈마에 노출되고, 이로 인해 폴리실리콘막의 변형이 발생될뿐 아니라 전기적 소자특성이 저하되는 문제가 있다.Therefore, in order to etch the dense pattern in the cell region, the independent pattern in the peripheral region is exposed to the plasma for an excessively long time, which causes not only the deformation of the polysilicon film but also the deterioration of the electrical device characteristics. .
본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 안출한 것으로, 셀지역과 주변지역간 식각속도 차이에 따른 주변지역의 과도한 플라즈마 노출을 억제하는데 적합한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device suitable for suppressing excessive plasma exposure in the surrounding area due to the difference in etching speed between the cell region and the surrounding area.
도 1a 내지 도 1c는 종래 기술에 따른 텅스텐실리사이드 게이트전극을 구비하는 반도체 소자의 제조 방법을 도시한 공정 단면도,1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device having a tungsten silicide gate electrode according to the prior art;
도 2a 내지 도 2d는 본 발명의 실시예에 따른 텅스텐실리사이드 게이트전극을 구비하는 반도체 소자의 제조 방법을 도시한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a tungsten silicide gate electrode according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 게이트절연막21 semiconductor substrate 22 gate insulating film
23 : 폴리실리콘막 24 : 텅스텐시리사이드막23 polysilicon film 24 tungsten silicide film
25 : 셀지역오픈마스크 26 : 질화막25: cell area open mask 26: nitride film
27 : 감광막패턴27: photosensitive film pattern
Y : 단차Y: step
상기 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은 셀지역과 주변지역이 정의된 반도체 기판 상에 게이트절연막을 형성하는 단계, 상기 게이트절연막 상에 폴리실리콘막과 텅스텐실리사이드막을 차례로 형성하는 단계, 상기 셀지역의 텅스텐실리사이드막을 일부 식각하여 상기 셀지역과 주변지역의 텅스텐실리사이드막간 단차를 발생시키는 단계, 및 상기 단차가 발생된 텅스텐실리사이드막과 상기 폴리실리콘막을 동일한 식각조건하에서 식각하여 상기 셀지역에 조밀한 게이트전극을 형성함과 동시에 상기 주변지역에 드문 게이트전극을 형성하는 단계를 포함함을 특징으로 한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a gate insulating film on a semiconductor substrate having a cell region and a peripheral region defined, and sequentially forming a polysilicon film and a tungsten silicide film on the gate insulating film Partially etching the tungsten silicide film in the cell region to generate a step between the tungsten silicide film in the cell region and the surrounding region, and etching the tungsten silicide film and the polysilicon film in which the step is generated under the same etching conditions. Forming a dense gate electrode at the same time and forming a rare gate electrode in the peripheral area.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명한다.Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 텅스텐실리사이드 게이트전극을 구비하는 반도체 소자의 제조 방법을 도시한 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a tungsten silicide gate electrode according to an exemplary embodiment of the present invention.
도 2a에 도시된 바와 같이, 셀지역과 주변지역이 정의된 반도체 기판(21) 상에 게이트절연막(22)을 형성한다. 이때, 게이트절연막(22)은 열산화공정을 통해 20Å∼70Å의 두께로 성장시킨 실리콘산화막이다.As shown in FIG. 2A, the gate insulating layer 22 is formed on the semiconductor substrate 21 in which the cell region and the peripheral region are defined. At this time, the gate insulating film 22 is a silicon oxide film grown to a thickness of 20 kPa to 70 kPa through a thermal oxidation process.
다음에, 게이트절연막(22) 상에 폴리실리콘막(23)과 텅스텐실리사이드막(24)을 증착한다. 이때, 셀지역에서 부분적으로 제거될 것을 고려하여 텅스텐실리사이드막(24)은 충분히 두껍게(1000Å∼1500Å) 증착하고, 폴리실리콘막(23)은 저압화학증착법(LPCVD)을 이용하여 500Å∼1000Å의 두께로 증착한 것이다.Next, a polysilicon film 23 and a tungsten silicide film 24 are deposited on the gate insulating film 22. At this time, the tungsten silicide film 24 is sufficiently thick (1000 kPa to 1500 kPa) in consideration of being partially removed from the cell region, and the polysilicon film 23 is 500 kPa to 1000 kPa using low pressure chemical vapor deposition (LPCVD). It is deposited as.
다음에, 텅스텐실리사이드막(24) 상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 셀지역을 오픈시키는 셀지역오픈마스크(25)를 형성한다.Next, a photoresist film is applied on the tungsten silicide film 24 and patterned by exposure and development to form a cell region open mask 25 for opening the cell region.
다음에, 셀지역오픈마스크(25)를 식각마스크로 하여 셀지역오픈마스크(25)에 의해 노출된 셀지역의 텅스텐실리사이드막(24)을 일부 식각하여 주변지역보다 낮게 하여 단차(Y)를 발생시킨다.Next, the tungsten silicide film 24 in the cell region exposed by the cell region open mask 25 is partially etched using the cell region open mask 25 as an etch mask to be lower than the surrounding region to generate a step Y. Let's do it.
이때, 일부 식각되는 텅스텐실리사이드막(24)은 셀지역과 주변지역에서 식각이 동시에 완료되도록 하는 두께를 갖는다.At this time, the partially etched tungsten silicide layer 24 has a thickness such that etching is simultaneously completed in the cell region and the peripheral region.
결국, 셀지역에 비해 주변지역에서 텅스텐실리사이드막(24)이 더 두껍다.As a result, the tungsten silicide film 24 is thicker in the surrounding area than in the cell area.
도 2b에 도시된 바와 같이, 셀지역오픈마스크(25)를 제거한 후, 단차(Y)가 발생된 텅스텐실리사이드막(24) 상에 하드마스크용 질화막(26)을 형성한다. 다음에, 질화막(26) 상에 감광막을 증착하고, 노광 및 현상 공정을 이용하여 패터닝하여 감광막패턴(27)을 형성한다.As shown in FIG. 2B, after removing the cell region open mask 25, a hard mask nitride layer 26 is formed on the tungsten silicide layer 24 on which the step Y is generated. Next, a photoresist film is deposited on the nitride film 26 and patterned using an exposure and development process to form a photoresist pattern 27.
도 2c에 도시된 바와 같이, 감광막패턴(27)을 마스크로 이용하여 질화막(26)을 선택적으로 식각하고, 감광막패턴(27)을 제거한 후, 세정 공정을 실시한다.As illustrated in FIG. 2C, the nitride film 26 is selectively etched using the photosensitive film pattern 27 as a mask, the photoresist pattern 27 is removed, and then a cleaning process is performed.
다음에, 질화막(26)을 마스크로 이용하여 ICP 방법으로 SF6/Cl2/O2/N2을 베이스로 하여 텅스텐실리사이드막(24)을 식각한다. 이때, 텅스텐실리사이드막(24) 식각시 패턴이 조밀한 셀지역이 상대적으로 조밀하지 않는 주변지역에 비해 식각속도가 현저히 떨어지기 때문에 주변지역의 텅스텐실리사이드막(24)이 더 빨리 식각된다.Next, using the nitride film 26 as a mask, the tungsten silicide film 24 is etched based on SF 6 / Cl 2 / O 2 / N 2 by the ICP method. At this time, since the etching speed is significantly lower than that of the peripheral region where the pattern of the tungsten silicide layer 24 is not dense, the tungsten silicide layer 24 in the peripheral region is etched faster.
하지만, 본 발명에서는 식각속도가 떨어지는 셀지역에 미리 단차(Y)를 형성해주므로써 주변지역의 두꺼운 텅스텐실리사이드막(24)은 셀지역보다 상대적으로 빠른 속도로 인해 셀지역과 비슷한 시간에 제거된다. 즉, 셀지역과 주변지역의 식각속도 차이를 미리 형성한 단차(Y)를 이용하여 극복하는 것이다.However, in the present invention, since the step (Y) is formed in advance in the cell region in which the etching rate is lowered, the thick tungsten silicide layer 24 in the peripheral region is removed at a similar time as the cell region due to the relatively higher speed than the cell region. In other words, the difference of the etching speed between the cell region and the surrounding region is overcome by using the step (Y) formed in advance.
도 2d에 도시된 바와 같이, 텅스텐실리사이드막(24) 식각후 드러나는 폴리실리콘막(23)을 식각하여 셀지역에 조밀한 게이트전극을 형성함과 동시에 주변지역에 조밀하지 않은, 즉 드문 게이트전극을 형성한다. 이때, 텅스텐실리사이드막과 폴리실리콘막을 식각하는 동일한 건식식각 조건은, SF6/Cl2/O2/N2을 식각가스로 하고, 20W∼300W의 바이어스파워와 100W∼500W의 소스파워를 인가하여 플라즈마를 발생시키며, 압력은 1mtorr∼100mtorr로 유지한다.As shown in FIG. 2D, the polysilicon layer 23 exposed after etching the tungsten silicide layer 24 is etched to form a dense gate electrode in the cell region and to form a dense gate electrode that is not dense in the peripheral region. Form. In this case, the same dry etching conditions for etching the tungsten silicide layer and the polysilicon layer are performed by using SF 6 / Cl 2 / O 2 / N 2 as an etching gas, applying a bias power of 20 W to 300 W and a source power of 100 W to 500 W. The plasma is generated, and the pressure is maintained at 1 mtorr to 100 mtorr.
위와 같은 폴리실리콘막(23) 식각시에도 미리 형성한 단차(Y)의 영향을 받기 때문에 셀지역과 주변지역에서 동일한 식각률을 나타낸다.Even when the polysilicon layer 23 is etched as described above, the same etching rate is shown in the cell region and the surrounding region because the polysilicon layer 23 is affected by the step (Y) previously formed.
결국, 미리 단차를 형성해둠으로써 패턴의 조밀 정도에 관계없이 식각이 완료되는 시점을 동일하게 하여 주변지역의 폴리실리콘막이 플라즈마에 과도하게 노출되는 것을 방지한다.As a result, by forming a step in advance, the polysilicon film in the surrounding area is prevented from being excessively exposed to the plasma by making the same time when etching is completed regardless of the degree of denseness of the pattern.
한편, 셀지역에 형성되는 게이트전극과 주변지역에 형성되는 게이트전극은 단차(Y) 만큼의 높이 차이를 갖는다.On the other hand, the gate electrode formed in the cell region and the gate electrode formed in the peripheral region have a height difference as much as the step (Y).
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 게이트 패터닝시 셀지역과 주변지역에서 동시에 식각이 완료되도록 하므로써 주변지역의 과도한 플라즈마 노출을 억제하여 게이트전극의 변형을 방지하고, 아울러 소자의 특성을 향상시킬 수 있는 효과가 있다.As described above, the present invention has the effect of preventing the deformation of the gate electrode by preventing excessive plasma exposure in the surrounding area by simultaneously completing the etching in the cell area and the surrounding area at the time of gate patterning, and improving the characteristics of the device. have.
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| KR100925029B1 (en) * | 2006-12-27 | 2009-11-03 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| US8609543B2 (en) | 2006-12-27 | 2013-12-17 | Hynix Semiconductor Inc. | Method for manufacturing semiconductor device having multi-layered hard mask layer |
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