KR100205095B1 - Method for forming bit line of semiconductor device - Google Patents
Method for forming bit line of semiconductor device Download PDFInfo
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- KR100205095B1 KR100205095B1 KR1019950041449A KR19950041449A KR100205095B1 KR 100205095 B1 KR100205095 B1 KR 100205095B1 KR 1019950041449 A KR1019950041449 A KR 1019950041449A KR 19950041449 A KR19950041449 A KR 19950041449A KR 100205095 B1 KR100205095 B1 KR 100205095B1
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- film
- etching
- bit line
- oxide film
- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 10
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 abstract description 18
- 239000010410 layer Substances 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 비트라인 형성방법에 관한 것으로, 공정을 단순화 시키며 산화막의 식각 깊이를 정확히 제어하기 위해 식각비를 조절하여 ARC막으로 사용되는 질화막 및 산화막을 동시에 식각하므로써 소자의 수율을 향상시킬 수 있도록 한 반도체 소자의 비트라인 형성방법에 관한 것이다.The present invention relates to a method for forming a bit line of a semiconductor device, which simplifies the process and improves the yield of the device by simultaneously etching the nitride film and the oxide film used as the ARC film by controlling the etching ratio to precisely control the etching depth of the oxide film. It relates to a method for forming a bit line of a semiconductor device.
Description
제1a도 내지 제1d도는 종래의 반도체 소자의 비트라인 형성방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining a bit line forming method of a conventional semiconductor device.
제2a도 내지 제2c도는 본 발명에 따른 반도체 소자의 비트라인 형성방법을 설명하기 위한 소자의 단면도.2A to 2C are cross-sectional views of a device for explaining a method of forming a bit line of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 및 11 : 실리콘 기판 2 및 22 : 산화막1 and 11: silicon substrate 2 and 22: oxide film
3 및 13 : 폴리실리콘막 4 및 14 : 텅스텐 실리사이드막3 and 13: polysilicon film 4 and 14: tungsten silicide film
5 및 15 : 질화막 6 및 16 : 감광막5 and 15: nitride film 6 and 16: photosensitive film
본 발명은 반도체 소자의 비트라인 형성방법에 관한 것으로, 특히 폴리사이드(Polycide)구조를 갖는 반도체 소자의 비트라인 형성방법에 관한 것이다.The present invention relates to a method for forming a bit line of a semiconductor device, and more particularly, to a method for forming a bit line of a semiconductor device having a polycide structure.
일반적으로 비트라인은 폴리실리콘막상에 텅스텐 실리사이드(WSix)를 증착한 폴리사이드 구조로 형성된다. 텅스텐 실리사이드(WSix)는 전기적 비저항 값이 폴리실리콘에 비해 낮고, 열적 안정성이 우수한 장점을 가지는 반면, 산화막과의 접착력이 나쁘기 때문에 대개 폴리실리콘막상에 형성되어 폴리사이드 구조로 사용된다.In general, the bit line is formed of a polyside structure in which tungsten silicide (WSix) is deposited on a polysilicon layer. Tungsten silicide (WSix) is generally formed on a polysilicon film and used as a polyside structure because the electrical resistivity value is lower than polysilicon and has the advantage of excellent thermal stability, while adhesion to the oxide film is poor.
그러면 폴리사이드 구조를 갖는 종래 반도체 소자의 비트라인 형성방법을 제1a도 내지 제1d도를 이용하여 설명하면 다음과 같다.A method of forming a bit line of a conventional semiconductor device having a polyside structure will now be described with reference to FIGS. 1A to 1D.
제1a도를 참조하면, 소정의 소자 제조 공정을 거친 실리콘 기판(1)상부에 산화막(2), 폴리실리콘막(3), 텅스텐 실리사이드막(4) 및 질화막(5)을 순차적으로 형성한다. 질화막(5) 상부에 감광막(6)을 형성한 후 소정의 마스크(도시안됨)를 이용한 사진 및 식각 공정을 실시하여 감광막(6)을 패터닝한다. 산화막(2)은 층간 절연막의 역할을 하며 질화막(5)은 사진 공정시 빛의 반사를 방지하기 위한 반사 방지막(Anti Reflection Coating; ARC)으로 사용된다.Referring to FIG. 1A, an oxide film 2, a polysilicon film 3, a tungsten silicide film 4, and a nitride film 5 are sequentially formed on a silicon substrate 1 that has undergone a predetermined device fabrication process. After the photoresist layer 6 is formed on the nitride layer 5, the photoresist layer 6 is patterned by performing a photographic and etching process using a predetermined mask (not shown). The oxide film 2 serves as an interlayer insulating film, and the nitride film 5 is used as an anti reflection coating (ARC) to prevent reflection of light during a photographic process.
제1b도는 패터닝된 감광막(6)을 마스크로 이용한 제1식각 공정으로 질화막(5), 팅스텐 실리사이드막(4) 및 폴리실리콘막(3)을 순차적으로 패터닝하여 비트라인을 형성한 상태의 단면도이다.FIG. 1B is a cross-sectional view of the nitride film 5, the tinsten silicide film 4, and the polysilicon film 3 sequentially formed in the first etching process using the patterned photosensitive film 6 as a mask to form a bit line. to be.
제1c도는 비트라인을 형성한 상태에서 계속해서 이후 산화막(2)의 선택된 영역을 식각하여 형성될 콘택 홀의 단차를 완화시키기 위해 산화막(2)을 일정 깊이 (A)만큼 식각한 상태의 단면도이다.FIG. 1C is a cross-sectional view of the oxide film 2 being etched by a predetermined depth A in order to alleviate the step difference of the contact hole to be formed by subsequently etching the selected region of the oxide film 2 while the bit line is formed.
제1d도는 감광막(6)을 제거하고 세정(Cleaning)공정을 실시한 후 건식식각 방법으로 질화막(5)을 블랭킷(Blanket)식각하는 제2식각공정을 실시한 상태의 단면도인데, 이때 산화막(2)도 소정 깊이(B)만큼 식각된다.FIG. 1D is a cross-sectional view of a second etching process of blanket etching the nitride film 5 by a dry etching method after removing the photosensitive film 6 and performing a cleaning process, wherein the oxide film 2 also It is etched by a predetermined depth (B).
그런데, 이와 같은 종래의 방법은 비트라인 형성 및 산화막을 소정의 두께로 식각하기 위한 제1식각 공정과 ARC막으로 사용된 질화막(5)을 제거하기 위한 제2식각공정이 각각 건식식각 방법으로 이루어지기 때문에 공정이 복잡해지며, 산화막(2)의 식각 깊이를 조절하기가 매우 어려운 문제점이 있다.However, in the conventional method, a dry etching method includes a first etching process for forming a bit line and an etching of an oxide film to a predetermined thickness, and a second etching process for removing the nitride film 5 used as the ARC film, respectively. Since the process becomes complicated, it is very difficult to control the etching depth of the oxide film 2.
따라서, 본 발명은 ARC막으로 사용되는 질화막 제거 및 콘택 홀의 단차를 완화를 위한 산화막이 식각 공정을 동시에 실시하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 비트라인 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a bit line of a semiconductor device capable of solving the above-mentioned drawbacks by simultaneously performing an etching process of an oxide film for removing a nitride film used as an ARC film and alleviating a step of a contact hole. .
상술한 목적을 달성하기 위한 본 발명은 소정의 소자 제조 공정을 거친 실리콘 기판상에 산화막, 폴리실리콘막, 텅스텐 실리사이드막, 반사 방지막을 순차적으로 형성하는 제1단계와, 상기 반사 방지막, 텅스텐 실리사이드막 및 폴리실리콘막의 선택된 영역을 순차적으로 식각하는 제2단계와, 상기 반사 방지막을 제거하는 동시에 상기 산화막이 일정 깊이 식각되도록 식각비를 조절하여 식각비를 조절하여 식각공정을 실시하는 제3단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is a first step of sequentially forming an oxide film, a polysilicon film, a tungsten silicide film, an antireflection film on a silicon substrate that has undergone a predetermined device manufacturing process, and the antireflection film, tungsten silicide film And a third step of sequentially etching selected regions of the polysilicon film, and a third step of performing an etching process by adjusting an etching ratio by removing an anti-reflection film and adjusting an etching ratio so that the oxide film is etched to a predetermined depth. It is characterized by.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2a도 내지 제2c도는 본 발명에 따른 반도체 소자의 비트라인 형성방법을 설명하기 위해 도시한 소자의 단면도이다.2A to 2C are cross-sectional views of a device for explaining a method of forming a bit line of a semiconductor device according to the present invention.
제2a도를 참조하면, 소정의 소자 제조 공정을 거친 실리콘 기판(11) 상부에 산화막(12), 폴리실리콘막(13), 텅스텐 실리사이드막(14) 및 질화막(15)을 순차적으로 형성한다. 질화막(15) 상부에 감광막(16)을 형성한 후 소정의 마스크(도시안됨)를 이용한 사진 및 식각 공정으로 감광막(16)을 패터닝한다. 여기서, 산화막(12)은 층간 절연막으로 사용되며, 질화막(15)은 사진 공정시 빛의 반사를 방지하기 위한 ARC막으로 사용된다.Referring to FIG. 2A, an oxide film 12, a polysilicon film 13, a tungsten silicide film 14, and a nitride film 15 are sequentially formed on the silicon substrate 11 that has undergone a predetermined device fabrication process. After the photoresist layer 16 is formed on the nitride layer 15, the photoresist layer 16 is patterned by a photolithography and an etching process using a predetermined mask (not shown). Here, the oxide film 12 is used as an interlayer insulating film, and the nitride film 15 is used as an ARC film for preventing reflection of light during the photolithography process.
제2b도는 패터닝된 감광막(16)을 마스크로 이용한 식각 공정으로 질화막(15), 텅스텐 실리사이드막(14), 폴리실리콘막(13)을 순차적으로 제거하여 비트라인을 형성한 후 감광막(16)을 제거한 상태의 단면도이다.2B illustrates an etching process using the patterned photosensitive film 16 as a mask to sequentially remove the nitride film 15, the tungsten silicide film 14, and the polysilicon film 13 to form a bit line, and then to form the photosensitive film 16. It is sectional drawing of the state removed.
제2c도는 세정 공정을 실시한 후 산화막(12)과 질화막(15)의 식각비가 3:1 이하가 되도록 하여 질화막(15)을 식각한 상태의 단면도로서, 상대적으로 얇게 형성된 질화막(15)이 제거되는 동안 상대적으로 두껍게 형성된 산화막(12)도 일정깊이(C) 식각된다. 여기서, 식각비를 조절하는 방법으로는 식각 가스로 이용되는 CF4 및 CHF3 의 조성비를 조절하는 방법과 고주파 전력(RF Power)을 500W 이하가 되도록 조절하는 방법이 있다.FIG. 2C is a cross-sectional view of the nitride film 15 being etched such that the etch ratio of the oxide film 12 and the nitride film 15 is 3: 1 or less after the cleaning process, and the relatively thin nitride film 15 is removed. The relatively thick oxide film 12 is also etched to a certain depth (C). Here, the method of adjusting the etch ratio includes a method of adjusting the composition ratio of CF4 and CHF3 used as an etching gas and a method of adjusting the RF power to 500 W or less.
참고적으로, CHF3 가스의 조성비를 높게하면 산화막(12)의 식각비가 낮아지는 반면, 고주파 전력을 높일수록 산화막(12)의 식각 속도는 증가하게 된다.For reference, when the composition ratio of the CHF3 gas is increased, the etching ratio of the oxide film 12 is lowered, whereas the etching rate of the oxide film 12 is increased as the high frequency power is increased.
본 발명은 상술한 실시예에 한정되는 것은 아니며 청구범위의 요지를 벗어나지 않는 범위내에서 여러 가지의 변형이 가능하다. 즉 본 발명의 실시예에서는 질화막(15)의 제거 및 콘택 홀의 단차를 완화시키기 위한 산화막(12)의 식각 공정을 건식식각을 이용하였으나 필요에 따라 습식식각을 이용할 수도 있다.The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the claims. That is, in the exemplary embodiment of the present invention, the etching process of the oxide film 12 to remove the nitride film 15 and to alleviate the step difference of the contact hole is performed by dry etching, but wet etching may be used if necessary.
상술한 바와 같이 ARC막으로 사용되는 질화막의 제거 및 콘택 홀의 단차를 완화시키기 위한 산화막의 식각을 동시에 행하므로써 공정의 단계가 감소되기 때문에 공정의 단순화를 꾀할 수 있으며, 산화막의 식각 깊이를 정확히 조절할 수 있어 식각 모니터링 공정에 적용하는 경우 소자의 수율을 향상시킬 수 있는 탁월한 효과가 있다.As described above, the steps of the process are reduced by simultaneously removing the nitride film used as the ARC film and etching the oxide film to alleviate the step difference of the contact hole, thereby simplifying the process and precisely controlling the etching depth of the oxide film. When applied to an etching monitoring process, there is an excellent effect of improving the yield of the device.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950041449A KR100205095B1 (en) | 1995-11-15 | 1995-11-15 | Method for forming bit line of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950041449A KR100205095B1 (en) | 1995-11-15 | 1995-11-15 | Method for forming bit line of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR970030800A KR970030800A (en) | 1997-06-26 |
| KR100205095B1 true KR100205095B1 (en) | 1999-06-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019950041449A KR100205095B1 (en) | 1995-11-15 | 1995-11-15 | Method for forming bit line of semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100564427B1 (en) * | 2000-12-20 | 2006-03-28 | 주식회사 하이닉스반도체 | Method for cleaning the contact of semiconductor device |
-
1995
- 1995-11-15 KR KR1019950041449A patent/KR100205095B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100564427B1 (en) * | 2000-12-20 | 2006-03-28 | 주식회사 하이닉스반도체 | Method for cleaning the contact of semiconductor device |
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| Publication number | Publication date |
|---|---|
| KR970030800A (en) | 1997-06-26 |
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