KR100333726B1 - Method of fabricating semiconductor device - Google Patents
Method of fabricating semiconductor device Download PDFInfo
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- KR100333726B1 KR100333726B1 KR1019980038870A KR19980038870A KR100333726B1 KR 100333726 B1 KR100333726 B1 KR 100333726B1 KR 1019980038870 A KR1019980038870 A KR 1019980038870A KR 19980038870 A KR19980038870 A KR 19980038870A KR 100333726 B1 KR100333726 B1 KR 100333726B1
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- forming
- capacitor
- metal contact
- peripheral circuit
- interlayer insulating
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
금속콘택이 형성될 비트라인상의 ARC막을 전 공정에서 미리 제거함으로써 금속콘택 형성을 용이하게 하기 위하여 셀영역과 주변회로영역으로 구분된 반도체기판상에 제1층간절연막을 형성하는 단계와, 상기 제1층간절연막상에 도전층과 ARC막을 차례로 형성하고 소정 패턴으로 패터닝하는 단계, 기판 전면에 제2층간절연막을 형성하는 단계, 상기 제1 및 제2층간절연막을 선택적으로 식각하여 셀영역에는 커패시터 콘택을 형성하고, 주변회로영역에는 금속콘택을 동시에 형성하는 단계, 상기 커패시터콘택 및 금속콘택을 포함한 기판 전면에 커패시터 하부전극 형성용 폴리실리콘층과 커패시터 형성용 희생막을 차례로 형성하는 단계, 상기 커패시터 형성용 희생막과 폴리실리콘층을 이방성식각하여 셀영역에 커패시터 패턴을 형성함과 동시에 주변회로영역의 금속콘택 측면에 폴리실리콘 스페이서를 형성하는 단계, 상기 커패시터 형성용 희생막을 제거하고, 셀영역에 커패시터 유전막 및 커패시터 상부전극을 차례로 형성하여 커패시터를 완성하는 단계, 기판 전면에 제3층간절연막을 형성하는 단계 및 상기 주변회로영역의 제3층간절연막을 선택적으로 식각하여 상기 도전층을 노출시키는 금속콘택을 완성하는 단계를 포함하여 이루어지는 반도체소자 제조방법을 제공한다.Forming a first interlayer insulating film on a semiconductor substrate divided into a cell region and a peripheral circuit region in order to facilitate metal contact formation by removing the ARC film on the bit line on which the metal contact is to be formed in advance in the entire process; Forming a conductive layer and an ARC film on the interlayer insulating film in sequence, patterning in a predetermined pattern, forming a second interlayer insulating film on the entire surface of the substrate, selectively etching the first and second interlayer insulating film to form a capacitor contact in the cell region Forming a metal contact in a peripheral circuit area at the same time; sequentially forming a polysilicon layer for forming a capacitor lower electrode and a sacrificial layer for forming a capacitor on the front surface of the substrate including the capacitor contact and the metal contact; Anisotropically etch the film and the polysilicon layer to form capacitor patterns in the cell area Forming a polysilicon spacer on the side of the metal contact of the region, removing the sacrificial layer for forming the capacitor, and completing the capacitor by sequentially forming a capacitor dielectric layer and a capacitor upper electrode in the cell region, and forming a third interlayer dielectric layer on the entire surface of the substrate. And forming a metal contact exposing the conductive layer by selectively etching the third interlayer dielectric layer in the peripheral circuit region.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 반도체소자의 금속콘택 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a metal contact of the semiconductor device.
도 1a 내지 도 1c를 참조하여 종래기술에 의한 반도체소자의 금속콘택 형성방법을 설명한다. 단, 비트라인 형성공정 이후부터 설명하기로 한다.A method of forming a metal contact of a semiconductor device according to the prior art will be described with reference to FIGS. 1A to 1C. However, it will be described after the bit line forming process.
먼저, 도 1a를 참조하면, 셀영역(A)과 주변회로영역(B)으로 구분된 반도체기판(도시하지 않음)상에 제1층간절연막(1)을 형성하고, 이위에 비트라인형성용 도전층과 비트라인 패터닝시 패턴 마스킹을 용이하게 하는 ARC(anti-reflective coating)막(3)을 차례로 형성한후, 이를 소정의 비트라인 패턴으로 패터닝하여 비트라인(2A,2B)을 형성한다.First, referring to FIG. 1A, a first interlayer insulating film 1 is formed on a semiconductor substrate (not shown) divided into a cell region A and a peripheral circuit region B, and a bit line forming conductive thereon is formed thereon. After forming the layer and the anti-reflective coating (ARC) film 3 that facilitates pattern masking during bit line patterning, the bit lines 2A and 2B are formed by patterning the anti-reflective coating (ARC) film 3 in a predetermined bit line pattern.
이어서 도 1b에 도시된 바와 같이 기판 전면에 제2층간절연막(4)을 형성한 후, 셀영역(A)의 층간절연막들(1,4)을 선택적으로 식각하여 커패시터 콘택을 형성하고, 이 커패시터 콘택을 통해 기판 소정부분과 접속되는 커패시터를 형성한다. 이때, 커패시터는 커패시터 하부전극(6)과 커패시터 유전막(7) 및 커패시터 상부전극(8)으로 형성된다. 이어서 기판 전면에 제3층간절연막(9)을 형성한 후, 주변회로영역(B)상에 금속콘택 형성용 마스크패턴(10)을 형성한다.Subsequently, as shown in FIG. 1B, the second interlayer insulating film 4 is formed on the entire surface of the substrate, and then the interlayer insulating films 1 and 4 of the cell region A are selectively etched to form capacitor contacts. A capacitor is formed to be connected to a predetermined portion of the substrate through the contact. In this case, the capacitor is formed of the capacitor lower electrode 6, the capacitor dielectric layer 7, and the capacitor upper electrode 8. Subsequently, after forming the third interlayer insulating film 9 on the entire surface of the substrate, the mask pattern 10 for forming a metal contact is formed on the peripheral circuit region B.
다음에 도 1c에 도시된 바와 같이 상기 마스크패턴(10)을 마스크로 이용하여 주변회로영역(B)의 층간절연막들(9,4)을 선택적으로 식각하여 주변회로영역의 비트라인(2B)을 노출시키기 위한 금속콘택(20)을 형성한다.Next, as illustrated in FIG. 1C, the interlayer insulating layers 9 and 4 of the peripheral circuit region B may be selectively etched using the mask pattern 10 as a mask to form the bit line 2B of the peripheral circuit region. The metal contact 20 for exposure is formed.
상기한 종래기술의 경우, 도 1c에 도시된 바와 같이 비트라인에 금속콘택 형성시 비트라인상의 ARC막(3)이 폴리머의 발생으로 인해 제거하기가 어렵다. 따라서 제거되지 못한 이 ARC막으로 인해 소자 페일(fail)이 유발되게 된다.In the prior art described above, as shown in FIG. 1C, when the metal contact is formed on the bit line, the ARC film 3 on the bit line is difficult to remove due to the generation of a polymer. Therefore, this failing ARC film causes device fail.
본 발명은 상술한 문제점을 해결하기 위한 것으로, 금속콘택이 형성될 비트라인상의 ARC막을 전 공정에서 미리 제거함으로써 금속콘택 형성을 용이하게 하는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of fabricating a semiconductor device that facilitates metal contact formation by removing the ARC film on the bit line on which a metal contact is to be formed in advance.
도 1a 내지 도 1c는 종래기술에 의한 반도체소자의 금속콘택 형성방법을 도시한 공정순서도,1A to 1C are process flowcharts showing a metal contact forming method of a semiconductor device according to the prior art;
도 2a 내지 도 2e는 본 발명에 의한 반도체소자의 금속콘택 형성방법을 도시한 공정순서도.2A to 2E are process flowcharts showing a metal contact forming method of a semiconductor device according to the present invention;
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1 : 제1층간절연막 2A, 2B : 비트라인1: first interlayer insulating film 2A, 2B: bit line
3 : ARC막 4 : 제2층간절연막3: ARC film 4: Second interlayer insulating film
11 : 커패시터콘택 및 금속콘택 형성용 마스크패턴11: mask pattern for forming capacitor contact and metal contact
12 : 폴리실리콘층 12' : 폴리실리콘 스페이서12 polysilicon layer 12 'polysilicon spacer
13 : 커패시터 형성용 희생막 14 : 커패시터 유전막13: sacrificial film for capacitor formation 14: capacitor dielectric film
15 : 커패시터 상부전극 16 : 제3층간절연막15 capacitor upper electrode 16 third interlayer insulating film
17 : 금속콘택 형성용 마스크패턴 20 : 금속콘택17: mask pattern for forming a metal contact 20: metal contact
30 : 커패시터패턴 형성용 마스크패턴30: mask pattern for forming the capacitor pattern
상기 목적을 달성하기 위한 본 발명의 반도체소자 제조방법은, 셀영역과 주변회로영역으로 구분된 반도체기판상에 형성된 제1층간절연막상에 도전층과 반사방지막을 차례로 형성하고 소정 패턴으로 패터닝하는 단계; 기판 전면에 제2층간절연막을 형성하는 단계; 상기 제1 및 제2층간절연막을 선택적으로 식각하여 셀영역에는 커패시터 콘택을 형성하고, 주변회로영역에는 금속콘택을 동시에 형성하는 단계; 상기 커패시터콘택 및 금속콘택을 포함한 기판 전면에 커패시터 하부전극 형성용 폴리실리콘층과 커패시터 형성용 희생막을 차례로 형성하는 단계; 상기 커패시터 형성용 희생막과 폴리실리콘층을 이방성식각하여 셀영역에 커패시터 패턴을 형성함과 동시에 주변회로영역의 금속콘택 측면에 폴리실리콘 스페이서를 형성하는 단계; 상기 커패시터 형성용 희생막을 제거하고, 셀영역에 커패시터 유전막 및 커패시터 상부전극을 차례로 형성하여 커패시터를 완성하는 단계; 기판 전면에 제3층간절연막을 형성하는 단계 및 상기 주변회로영역의 제3층간절연막을 선택적으로 식각하여 상기 도전층을 노출시키는 금속콘택을 완성하는 단계를 포함하여 구성된다.A semiconductor device manufacturing method of the present invention for achieving the above object, the step of forming a conductive layer and an anti-reflection film in sequence on a first interlayer insulating film formed on a semiconductor substrate divided into a cell region and a peripheral circuit region and patterning in a predetermined pattern ; Forming a second interlayer insulating film over the entire substrate; Selectively etching the first and second interlayer insulating films to form a capacitor contact in a cell region and simultaneously forming a metal contact in a peripheral circuit region; Sequentially forming a polysilicon layer for forming a capacitor lower electrode and a sacrificial layer for forming a capacitor on an entire surface of the substrate including the capacitor contact and the metal contact; Anisotropically etching the capacitor forming sacrificial layer and the polysilicon layer to form a capacitor pattern in the cell region and to form a polysilicon spacer on the metal contact side of the peripheral circuit region; Removing the capacitor forming sacrificial layer, and forming a capacitor dielectric layer and a capacitor upper electrode in the cell region in order to complete the capacitor; And forming a third interlayer dielectric layer on the entire surface of the substrate and selectively etching the third interlayer dielectric layer in the peripheral circuit region to complete a metal contact exposing the conductive layer.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 도 2e에 본 발명에 의한 반도체소자의 금속콘택 형성방법을 도시하였다.2A to 2E illustrate a method of forming a metal contact of a semiconductor device according to the present invention.
먼저, 도 2a를 참조하면, 셀영역(A)과 주변회로영역(B)으로 구분된 반도체기판(도시하지 않음)상에 제1층간절연막(1)을 형성하고, 이위에 비트라인형성용 도전층과 비트라인 패터닝시 패턴 마스킹을 용이하게 하는 ARC(anti-reflective coating)막(3)으로서 예컨대 질화막을 차례로 형성한후, 이를 소정의 비트라인 패턴으로 패터닝하여 비트라인(2A,2B)을 형성한다. 이어서 기판 전면에 제2층간절연막(4)으로서 예컨대 산화막을 형성한 후, 셀영역(A)상에 커패시터 콘택 형성용 마스크패턴(11)을 형성한다. 이때 주변회로영역(B)의 금속콘택도 동시에 정의할 수 있도록 마스크패턴(11)을 형성한다. 즉, 제2층간절연막(4)상에 감광막(11)을 도포하고 이를 선택적으로 노광 및 현상하여 셀영역(A)의 커패시터 콘택영역과 주변회로영역(B)의 금속콘택 영역을 동시에 오픈시키는 감광막패턴(11)을 형성한다.First, referring to FIG. 2A, a first interlayer insulating film 1 is formed on a semiconductor substrate (not shown) divided into a cell region A and a peripheral circuit region B, and a bit line forming conductive layer is formed thereon. An anti-reflective coating (ARC) film 3, which facilitates pattern masking during layer and bit line patterning, for example, a nitride film is sequentially formed, and then patterned into a predetermined bit line pattern to form bit lines 2A and 2B. do. Subsequently, an oxide film, for example, is formed as the second interlayer insulating film 4 on the entire surface of the substrate, and then a mask pattern 11 for forming a capacitor contact is formed on the cell region A. In this case, the mask pattern 11 is formed to simultaneously define the metal contact of the peripheral circuit region B. That is, the photosensitive film 11 is coated on the second interlayer insulating film 4, and the photosensitive film 11 is selectively exposed and developed to simultaneously open the capacitor contact region of the cell region A and the metal contact region of the peripheral circuit region B at the same time. The pattern 11 is formed.
이어서 도 2b를 참조하면, 상기 감광막패턴(11)을 마스크로 이용하여 층간절연막(1,4)을 선택적으로 식각하여 셀영역(A)에는 커패시터콘택을 형성하고, 주변회로영역(B)에는 금속콘택을 형성한다. 이때, 주변회로영역(B)의 비트라인(2B)상의 ARC막(3)이 일정두께 식각된다. 이어서 감광막패턴을 제거하고, 기판 전면에 커패시터 하부전극 형성용 도전층으로서, 예컨대 폴리실리콘(12)을 증착하고, 그 상부에 커패시터 형성용 희생막으로서 PSG산화막(13)을 형성한다.Subsequently, referring to FIG. 2B, the interlayer insulating layers 1 and 4 are selectively etched using the photoresist pattern 11 as a mask to form capacitor contacts in the cell region A, and metal in the peripheral circuit region B. Form a contact. At this time, the ARC film 3 on the bit line 2B of the peripheral circuit region B is etched by a predetermined thickness. Subsequently, the photosensitive film pattern is removed, and a polysilicon 12 is deposited on the entire surface of the substrate as a conductive layer for forming a capacitor lower electrode, and a PSG oxide film 13 is formed as a sacrificial film for forming a capacitor thereon.
다음에 도 2c를 참조하면, 상기 PSG산화막(13)상에 커패시터패턴 형성용 마스크패턴(30)을 형성한 후, 이를 마스크로 이용하여 PSG산화막(13)과 폴리실리콘층(12)을 이방성식각한다. 이때, 주변회로영역(B)에 형성된 금속콘택의 측면에 폴리실리콘 스페이서(12')가 형성되게 된다.Next, referring to FIG. 2C, after forming a mask pattern 30 for forming a capacitor pattern on the PSG oxide layer 13, the PSG oxide layer 13 and the polysilicon layer 12 are anisotropically etched using the mask pattern 30 as a mask. do. At this time, the polysilicon spacer 12 ′ is formed on the side surface of the metal contact formed in the peripheral circuit region B. FIG.
이어서 도 2d를 참조하면, 상기 마스크패턴(30)과 PSG산화막(13)을 제거한 후, 셀영역(A)에 통상의 실린더형 커패시터 제조공정을 통해 커패시터 하부전극(12)과 커패시터 유전막(14) 및 커패시터 상부전극(15)으로 이루어진 커패시터를 완성한다. 이어서 기판 전면에 제3층간절연막(16)을 형성하고, 주변회로영역(B)상에 금속콘택 형성용 마스크패턴(17)을 형성한다. 상기 제3층간절연막은 폴리실리콘과의 식각선택비가 높은 물질로 형성하는 것이 바람직하다.Subsequently, referring to FIG. 2D, after removing the mask pattern 30 and the PSG oxide layer 13, the capacitor lower electrode 12 and the capacitor dielectric layer 14 are formed in the cell region A through a conventional cylindrical capacitor manufacturing process. And a capacitor consisting of the capacitor upper electrode 15. Subsequently, a third interlayer insulating film 16 is formed on the entire surface of the substrate, and a mask pattern 17 for forming a metal contact is formed on the peripheral circuit region B. The third interlayer insulating film may be formed of a material having a high etching selectivity with polysilicon.
다음에 도 2e를 참조하면, 상기 마스크패턴(17)을 이용하여 제3층간절연막(16)을 식각하여 주변회로영역(B)의 비트라인(2B)을 노출시키는 금속콘택(20)을 완성한다.Next, referring to FIG. 2E, the third interlayer insulating layer 16 is etched using the mask pattern 17 to complete the metal contact 20 exposing the bit line 2B of the peripheral circuit region B. .
상기와 같이 진행되는 본 발명의 반도체소자 제조공정에 있어서, 금속콘택 식각시 커패시터콘택 형성시 폴리실리콘 스페이서(12')가 형성되어 있으므로 금속콘택 오정렬시에도 폴리실리콘과 층간절연막의 높은 식각선택비로 인해 자기정렬이 가능하다. 또한, 종래에는 ARC막이 금속콘택 식각시 제거되지 않는 문제가 발생하였으나, 본 발명에서는 커패시터패턴 식각공정시(도 2c참조) 셀영역의 층간절연막들(1,4)이 식각되는 동안 주변회로영역이 과도식각되어 주변회로영역의 ARC막이 제거되게 된다. 또한, 주변회로영역상의 ARC막은 커패시터콘택 형성을 위한 식각시(도 2b), 커패시터패턴 형성을 위한 식각시(도 2c), 그리고 금속콘택 형성을 위한 식각시(도 2e) 모두 식각에 노출되므로 완전히 제거되게 된다.In the semiconductor device manufacturing process of the present invention as described above, the polysilicon spacer 12 ′ is formed when the capacitor contact is formed when the metal contact is etched, and thus, due to the high etching selectivity of the polysilicon and the interlayer insulating layer even when the metal contact is misaligned. Self-alignment is possible. In addition, in the related art, the ARC film is not removed during the etching of the metal contact. However, in the present invention, the peripheral circuit area is removed while the interlayer insulating films 1 and 4 of the cell region are etched during the capacitor pattern etching process (see FIG. 2C). Over-etching removes the ARC film in the peripheral circuit area. In addition, since the ARC film on the peripheral circuit region is exposed to etching during etching (FIG. 2B) for forming a capacitor contact, etching (FIG. 2C) for forming a capacitor pattern, and etching (FIG. 2E) for forming a metal contact. Will be removed.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
본 발명에 의하면, 반도체소자 제조공정중 금속콘택 식각시 비트라인상의 ARC막이 완전히 제거되지 않음으로써 발생할 수 있는 소자 페일을 방지할 수 있고, 금속콘택 식각시 오정렬을 폴리실리콘 스페이서를 이용하여 해결할 수 있다.According to the present invention, it is possible to prevent device failures that may occur because the ARC layer on the bit line is not completely removed during the metal contact etching process in the semiconductor device manufacturing process, and the misalignment during the metal contact etching may be solved using the polysilicon spacer. .
Claims (6)
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| KR100884338B1 (en) * | 2002-09-18 | 2009-02-18 | 주식회사 하이닉스반도체 | Method for forming metal of srmiconductor device |
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