KR20030056793A - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
- Publication number
- KR20030056793A KR20030056793A KR1020010087092A KR20010087092A KR20030056793A KR 20030056793 A KR20030056793 A KR 20030056793A KR 1020010087092 A KR1020010087092 A KR 1020010087092A KR 20010087092 A KR20010087092 A KR 20010087092A KR 20030056793 A KR20030056793 A KR 20030056793A
- Authority
- KR
- South Korea
- Prior art keywords
- hard mask
- layer
- photoresist pattern
- forming
- pattern
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010924 continuous production Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자에 관한 것으로 특히, 하드 마스크를 이용하여 패터닝을 할 때, 상기 하드 마스크를 정의하는 감광막을 제거하지 않고 계속 이어지는 패턴 식각 공정에서 이용하여 공정을 단순화한 반도체 소자의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of forming a semiconductor device, which is simplified in a subsequent pattern etching process without removing a photosensitive film defining the hard mask when patterning using a hard mask. will be.
이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 형성 방법을 설명하면 다음과 같다.Hereinafter, a method of forming a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래의 반도체 소자의 비트 라인 형성 방법을 나타낸 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a bit line of a conventional semiconductor device.
도 1a와 같이, 기판 상에 절연막, 배리어 금속막층, 금속층, 하드 마스크층, 감광막을 차례로 증착한 후, 사진 공정(photo process)을 통해 상기 감광막을 패터닝하여 하드 마스크를 정의하는 감광막 패턴으로 형성한다.As shown in FIG. 1A, an insulating film, a barrier metal film layer, a metal layer, a hard mask layer, and a photoresist film are sequentially deposited on a substrate, and then the photoresist film is patterned through a photo process to form a photoresist pattern defining a hard mask. .
상기 감광막 패턴을 이용하여 상기 하드 마스크층을 식각하여 하드 마스크를 형성한다.The hard mask layer is etched using the photoresist pattern to form a hard mask.
이 때, 상기 하드 마스크층은 절연막 성분의 재료를 사용한다.At this time, the hard mask layer uses a material of an insulating film component.
도 1b와 같이, 상기 감광막 패턴을 제거한 후, 하드 마스크을 포함한 절연막에 세정 공정을 진행한다.After removing the photosensitive film pattern as shown in FIG. 1B, a cleaning process is performed on the insulating film including the hard mask.
도 1c와 같이, 상기 하드 마스크 패턴대로 금속층, 배리어 금속막층을 제거하여 비트라인 및 배리어 금속막을 형성한다.As shown in FIG. 1C, the metal layer and the barrier metal film layer are removed according to the hard mask pattern to form a bit line and a barrier metal film.
이 때, 상기 금속층은 W(텅스텐) 성분이며, 상기 배리어 금속막층은 Ti/TiN이다.At this time, the metal layer is a W (tungsten) component, the barrier metal film layer is Ti / TiN.
그러나, 상기와 같은 종래의 반도체 소자의 형성 방법은 다음과 같은 문제점이 있다.However, the conventional method of forming a semiconductor device as described above has the following problems.
0.15㎛ 이하급 공정 기술을 적용하는 소자에서 비트라인을 텅스텐(W)으로 사용할 경우 비트라인 형성 후속 공정의 안정성을 확보하기 위해서 텅스텐 필름 위에 절연막이 있는 구조, 즉 하드 마스크를 형성하여 비트라인을 형성하는 경우가 많다. 이 때, 상기 비트라인 상부에 절연막을 증착하는 데, 이러한 절연막의 역할은 텅스텐을 식각할 때 하드 마스크뿐만 아니라 이후에 형성되는 캐패시터와 비트라인과의 절연 역할도 같이 하게 된다.When using bit line as tungsten (W) in devices applying 0.15㎛ or less process technology, bit line is formed by forming a structure with an insulating film on the tungsten film, that is, a hard mask to ensure the stability of the subsequent process. Many times. In this case, an insulating film is deposited on the bit line, and the role of the insulating film serves to insulate not only the hard mask but also the capacitor and bit line formed thereafter when etching tungsten.
상기 절연막을 식각시 손실이 많을 경우 후속 공정의 공정 마진이 없어지며, 불량을 유발할 가능성이 높다. 그렇다고, 절연막의 두께를 너무 높이면 절연막 식각시 소정 영역에 완전히 제거되어야 하는 부분에 절연막 성분이 남아있기 때문에 콘택 불량이 생길 수 있다.When the insulating film is etched with a large amount of loss, the process margin of a subsequent process is lost, which is likely to cause a defect. However, if the thickness of the insulating film is too high, contact failure may occur because the insulating film component remains in a portion that must be completely removed in a predetermined region during the etching of the insulating film.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 하드 마스크를 이용하여 패터닝을 할 때, 상기 하드 마스크를 정의하는 감광막을 제거하지 않고 계속 이어지는 패턴 식각 공정에서 이용하여 공정을 단순화한 반도체 소자의 형성 방법을 제공하는 데, 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. When patterning using a hard mask, the semiconductor device is simplified in a subsequent pattern etching process without removing the photoresist layer defining the hard mask. It is an object to provide a forming method.
도 1a 내지 도 1c는 종래의 반도체 소자의 비트 라인 형성 방법을 나타낸 공정 단면도1A to 1C are cross-sectional views illustrating a method of forming a bit line of a conventional semiconductor device.
도 2a 및 도 2b는 본 발명의 반도체 소자의 비트 라인 형성 방법을 나타낸 공정 단면도2A and 2B are cross-sectional views illustrating a method of forming a bit line of a semiconductor device of the present invention.
도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of drawings
21 : 반도체 기판 22 : 절연막21 semiconductor substrate 22 insulating film
23 : 배리어 금속막층 23a : 배리어 금속막23 barrier metal film layer 23a barrier metal film
24 : 금속층 24a : 비트 라인24: metal layer 24a: bit line
25 : 하드 마스크 26 : 감광막 패턴25: hard mask 26: photosensitive film pattern
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 형성 방법은 하드 마스크를 정의하는 감광막 패턴을 증착한 후 사진 공정을 통해 상기 하드 마스크층을 선택적으로 제거하여 하드 마스크를 형성한 후, 상기 감광막 패턴을 제거하지 않고 남겨 계속하여 하부에 증착된 금속층, 배리어 금속막층 등을 상기 감광막 패턴대로 식각하여 감광막 패턴 제거 후 필요한 세정 공정을 생략함을 특징으로 한다.In the method of forming the semiconductor device according to the present invention for achieving the above object, after depositing a photoresist pattern defining a hard mask, the hard mask layer is selectively removed by a photolithography process to form a hard mask. After removing the pattern, the metal layer, the barrier metal film layer, etc. deposited on the lower portion are etched according to the photoresist pattern, thereby eliminating the necessary cleaning process after removing the photoresist pattern.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 형성 방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 및 도 2b는 본 발명의 반도체 소자의 비트라인 형성 방법을 나타낸 공정 단면도이다.2A and 2B are cross-sectional views illustrating a method of forming a bit line of a semiconductor device of the present invention.
도 2a는 기판(21)상에 절연막(22), 배리어 금속막층(23), 금속층(24), 하드 마스크층, 감광막을 차례로 증착한 후, 사진 공정(photo process)을 통해 상기 감광막을 패터닝하여 하드 마스크(25)를 정의하는 감광막 패턴(26)으로 형성한다.FIG. 2A illustrates that an insulating film 22, a barrier metal film layer 23, a metal layer 24, a hard mask layer, and a photoresist film are sequentially deposited on a substrate 21, and then the photoresist film is patterned through a photo process. The photoresist pattern 26 is used to define the hard mask 25.
상기 감광막 패턴(26)을 이용하여 상기 하드 마스크층을 식각하여 하드 마스크(25)를 형성한다.The hard mask layer is etched using the photoresist pattern 26 to form a hard mask 25.
상기 절연막(22) 성분은 HLD(High temperature Low pressure Deposition) 방식으로 증착된다.The insulating layer 22 component is deposited by a high temperature low pressure deposition (HLD) method.
또한, 상기 하드 마스크층은 절연막 성분으로, TEOS(Tetra Ethyl Ortho Silicate)와 같은 물질을 사용한다.In addition, the hard mask layer is formed of an insulating film component, such as TEOS (Tetra Ethyl Ortho Silicate).
또한, 상기 금속층(24)은 W(텅스텐) 성분이며, 상기 배리어 금속막층(23)은 Ti/TiN이다.In addition, the metal layer 24 is a W (tungsten) component, the barrier metal film layer 23 is Ti / TiN.
이어, 상기 감광막 패턴(26)을 제거하지 않고 남겨, 상기 감광막 패턴(26)대로 상기 금속층(24), 배리어 금속막층(23)을 연속하여 식각한다. 이와 같은 식각 공정을 통해 상기 절연막(22) 상부에 배리어 금속막(23a), 비트라인(24a), 하드 마스크(25)가 차례로 증착된 형태로 패터닝된다.Subsequently, the metal layer 24 and the barrier metal film layer 23 are continuously etched with the photosensitive film pattern 26 without removing the photosensitive film pattern 26. Through the etching process, the barrier metal layer 23a, the bit line 24a, and the hard mask 25 are sequentially patterned on the insulating layer 22.
도 2a에 나타난 공정은 즉, 감광막에 대한 노광 공정을 완료한 후 산화막 에처(etcher)에서 감광막을 먼저 식각하여, 감광막 패턴(26)을 형성하고, 종래 요구되었던 감광막 패턴(26) 제거 공정과 세정공정을 생략하고, 바로 금속 에처(metal etcher)에서 금속층(24)과 배리어 금속막층(23)에 대한 패터닝을 행하는 것이다.In the process shown in FIG. 2A, that is, the photoresist is first etched in an oxide filmer after completing the exposure process to the photoresist, thereby forming the photoresist pattern 26, and removing and cleaning the photoresist pattern 26 previously required. The step is omitted, and the patterning of the metal layer 24 and the barrier metal film layer 23 is performed in a metal etcher.
도 2b와 같이, 패터닝이 완료된 후, 상기 감광막 패턴(26)을 제거하고, 비트라인(24a) 및 배리어 금속막(23a)에 대한 세정 공정을 한다.As shown in FIG. 2B, after the patterning is completed, the photoresist pattern 26 is removed, and the bit line 24a and the barrier metal layer 23a are cleaned.
상기 감광막 패턴(26)의 제거는 DPS(Decoupled Plasma Source - 금속 에처)에 같이 장착이 되어 있는 감광막 제거 챔버(Chamber)에서 연속으로(in-situ)로 제거하며 식각후 1회 세정을 한다.Removal of the photoresist pattern 26 is performed in-situ in a photoresist removal chamber (Chamber), which is mounted in a decoupled plasma source (DPS), and is cleaned once after etching.
상기 도면을 참조하여 감광막 패턴을 그대로 두고, 하부의 금속층 및 배리어 금속막까지 식각을 행하는 방법은 게이트 전극을 형성할 때나, 콘택 홀을 형성할 때도 이용이 가능하다.The method of etching to the lower metal layer and the barrier metal film while leaving the photoresist pattern intact with reference to the drawings may be used when forming a gate electrode or forming a contact hole.
기판상에 차례로 증착된 산화막, 게이트 전극층, 하드 마스크층을 선택적으로 제거하여 게이트 패턴을 정의하는 반도체 소자 형성 방법은 다음과 같다.A method of forming a semiconductor device in which a gate pattern is defined by selectively removing an oxide film, a gate electrode layer, and a hard mask layer sequentially deposited on a substrate is as follows.
즉, 하드 마스크를 정의하는 감광막 패턴을 증착한 후 사진 공정을 통해 상기 하드 마스크층을 선택적으로 제거하여 하드 마스크를 형성한 후, 상기 감광막 패턴을 제거하지 않고 남겨, 계속하여 게이트 전극층 및 산화막을 상기 감광막 패턴대로 동시에 식각하여 게이트 전극 및 게이트 산화막을 동시에 형성한다.That is, after depositing a photoresist pattern defining a hard mask and selectively removing the hard mask layer through a photographic process to form a hard mask, the photoresist pattern is left without removing the gate electrode layer and the oxide film. The gate electrode and the gate oxide film are simultaneously formed by etching the photoresist pattern simultaneously.
이 때, 상기 하드 마스크층은 TEOS로 이루어짐을 특징으로 한다.At this time, the hard mask layer is characterized in that made of TEOS.
또한, 하부 배선이 형성된 기판상에 차례로 증착된 배리어 금속막층, 절연막, 하드 마스크층을 선택적으로 제거하여 콘택 영역을 정의하는 반도체 소자 형성방법은 다음과 같다.In addition, a method of forming a semiconductor device for defining a contact region by selectively removing the barrier metal film layer, the insulating film, and the hard mask layer sequentially deposited on the substrate on which the lower wiring is formed is as follows.
즉, 하드 마스크를 정의하는 감광막 패턴을 증착한 후 사진 공정을 통해 상기 하드 마스크층을 선택적으로 제거하여 하드 마스크를 형성한 후, 상기 감광막 패턴을 제거하지 않고 남겨, 계속하여 절연막 및 배리어 금속막층을 상기 감광막 패턴대로 동시에 식각하여 콘택 영역을 형성한다.That is, after depositing a photoresist pattern defining a hard mask and selectively removing the hard mask layer through a photographic process to form a hard mask, the photoresist layer is left without removing the photoresist pattern. The photoresist layer is simultaneously etched to form a contact region.
상기에서 기술한 하드 마스크는 비트라인을 형성한 후나, 게이트 전극을 형성한 후, 또는 콘택 영역을 형성한 후에도 남겨, 이후 소자 내 캐패시터를 형성할 때, 감광막 대용으로 사용이 가능하다.The above-described hard mask may be left after forming the bit line, after forming the gate electrode, or after forming the contact region, and may be used as a substitute for the photoresist when forming a capacitor in the device.
종래의 반도체 소자를 형성할 때는, 절연막 식각이 완료 후에 마스크로 사용한 감광막을 제거한 다음 세정 공정을 거쳐 금속 식각 장비에서 텅스텐을 식각하였으나, 본 발명의 반도체 소자의 형성할 때는 절연막 식각 후 감광막을 제거하지 않고, 금속 식각 장비에서 남아있는 감광막 패턴을 이용하여 하드 마스크를 형성하는 단계와 연속 공정으로 금속층을 식각함으로써 비트라인을 형성한다. 즉, 공정의 단순화된다.When forming a conventional semiconductor device, the photoresist film used as a mask is removed after the insulating film is finished, and then tungsten is etched by the metal etching equipment through a cleaning process. Instead, the bit line is formed by forming a hard mask using the remaining photoresist pattern in the metal etching equipment and etching the metal layer in a continuous process. That is, the process is simplified.
상기와 같은 본 발명의 반도체 소자의 형성 방법은 다음과 같은 효과가 있다.The method of forming the semiconductor device of the present invention as described above has the following effects.
첫째, 종래의 반도체 소자 형성 방법과 비교하여 패터닝 형성 과정에 있어서, 감광막 패턴 제거 공정과 세정 공정 등을 생략할 수 있어, 공정이 간소화된다.First, in the patterning process, the photoresist pattern removing process, the cleaning process, and the like can be omitted in comparison with the conventional method of forming a semiconductor device, thereby simplifying the process.
둘째, 하드 마스크의 손실을 줄일 수 있어, 비트라인 식각 이후의 공정의 안정성도 확보할 수 있다.Second, it is possible to reduce the loss of the hard mask, thereby securing the stability of the process after bit line etching.
셋째, 하드 마스크로 이용되는 절연막 상에 감광막 패턴을 그대로 남겨 공정을 진행하므로, 절연막 자체의 증착 두께를 낮추면서 하부 금속층의 식각시 절연막의 손실을 줄일 수 있다.Third, since the process is performed while leaving the photoresist pattern on the insulating film used as the hard mask, the loss of the insulating film can be reduced when the lower metal layer is etched while lowering the deposition thickness of the insulating film itself.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010087092A KR20030056793A (en) | 2001-12-28 | 2001-12-28 | Method for forming semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010087092A KR20030056793A (en) | 2001-12-28 | 2001-12-28 | Method for forming semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20030056793A true KR20030056793A (en) | 2003-07-04 |
Family
ID=32214952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010087092A KR20030056793A (en) | 2001-12-28 | 2001-12-28 | Method for forming semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20030056793A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101017804B1 (en) * | 2008-07-29 | 2011-02-28 | 주식회사 하이닉스반도체 | Semiconductor Device and Method for Manufacturing the same |
-
2001
- 2001-12-28 KR KR1020010087092A patent/KR20030056793A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101017804B1 (en) * | 2008-07-29 | 2011-02-28 | 주식회사 하이닉스반도체 | Semiconductor Device and Method for Manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100340879B1 (en) | Method for forming fine patterns and method for forming gate electrodes in semiconductor device using the same | |
| KR100482029B1 (en) | Method for forming mim capacitor | |
| KR20030056793A (en) | Method for forming semiconductor device | |
| KR100333726B1 (en) | Method of fabricating semiconductor device | |
| US6613680B2 (en) | Method of manufacturing a semiconductor device | |
| KR100313957B1 (en) | Method for fabricating of capacitor | |
| KR100379531B1 (en) | method for manufacturing of semiconductor device | |
| KR20010046749A (en) | Method for fabricating node contact in semiconductor device | |
| KR100912958B1 (en) | Method for fabricating fine pattern in semiconductor device | |
| JP2003086572A (en) | Method for forming bit line of semiconductor device | |
| KR100752171B1 (en) | Method of Fabricating Semiconductor Device | |
| KR100638743B1 (en) | Method for manufacturing capacitor | |
| KR100523605B1 (en) | Method for forming capacitor of semiconductor device | |
| KR100284311B1 (en) | Method of manufacturing semiconductor device for improving via contact resistance | |
| KR100192548B1 (en) | Manufacturing method of capacitor | |
| KR100349365B1 (en) | Method for forming metal wiring of semiconductor device | |
| KR20040069786A (en) | Semiconductor metal wiring and its manufacturing method | |
| KR20010063078A (en) | Method for manufacturing of capacitor | |
| KR20040001845A (en) | Method for forming pattern of semiconductor device | |
| KR20050073363A (en) | Method of forming a contact hole in a semiconductor device | |
| KR20030045375A (en) | Method for depositing material by using mask for etching process | |
| KR20010076684A (en) | Method for manufacturing of semiconductor device | |
| KR20030056904A (en) | Method for Fabricating cylinder-Shape Capacitor | |
| KR20030002835A (en) | Method for etching semiconductor device using high selective ratio | |
| KR20010061546A (en) | Method for contact etching in ferroelectric memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |