KR100186504B1 - Manufacturing method of poly plug in semiconductor device - Google Patents
Manufacturing method of poly plug in semiconductor device Download PDFInfo
- Publication number
- KR100186504B1 KR100186504B1 KR1019960020647A KR19960020647A KR100186504B1 KR 100186504 B1 KR100186504 B1 KR 100186504B1 KR 1019960020647 A KR1019960020647 A KR 1019960020647A KR 19960020647 A KR19960020647 A KR 19960020647A KR 100186504 B1 KR100186504 B1 KR 100186504B1
- Authority
- KR
- South Korea
- Prior art keywords
- poly plug
- film
- forming
- semiconductor device
- manufacturing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 폴리 플러그의 안정성을 개선하여 소자의 신뢰성을 향상시키는데 적당하도록 한 반도체 소자의 폴리 플러그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a poly plug of a semiconductor device, which is suitable for improving the reliability of a device by improving stability of the poly plug.
본 발명의 반도체 소자의 폴리 플러그 제조방법은 반도체 기판상에 도프트 글래스막을 형성하여 고온 열처리로 평탄화시키는 공정과, 상기 도프트 글래스막을 포함한 전면에 감광막을 형성하는 공정과, 상기 감광막을 노광 및 현상 공정으로 패터닝하여 상기 반도체 기판의 표면이 노출되게 콘택홀을 형성하는 공정과, 상기 콘택홀 내부에 폴리 플러그를 형성하는 공정과, 상기 폴리 플러그를 포함한 전면에 제 1 절연막을 형성하는 공정과, 상기 콘택홀 상측의 제 1 절연막을 선택적을 식각하는 공정을 포함하여 이루어짐을 특징으로 한다.The method of manufacturing a poly plug of a semiconductor device according to the present invention comprises the steps of forming a doped glass film on a semiconductor substrate and flattening it by high temperature heat treatment, forming a photosensitive film on the entire surface including the doped glass film, and exposing and developing the photosensitive film. Forming a contact hole by patterning the semiconductor substrate to expose the surface of the semiconductor substrate; forming a poly plug inside the contact hole; forming a first insulating film on the entire surface including the poly plug; And selectively etching the first insulating film on the upper side of the contact hole.
Description
제 1 도 (a) - (c)는 종래의 반도체 소자의 폴리 플러그 제조방법을 나타낸 공정단면도1 (a) to (c) are cross-sectional views showing a conventional method for manufacturing a poly plug of a semiconductor device.
제 2 도 (a) - (f)는 본 발명의 반도체 소자의 폴리 플러그 제조방법을 나탄낸 공정 단면도2 (a) to 2 (f) are cross-sectional views illustrating a method for manufacturing a poly plug of a semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 반도체 기판 22 : 도프트 글래스막21 semiconductor substrate 22 doped glass film
23 : 제 1 감광막 24 : 제 1 콘택홀23: first photosensitive film 24: first contact hole
25 : 폴리 실리콘막 26 : 폴리 플러그25: polysilicon film 26: poly plug
27 : 절연막 28 : 제 2 감광막27: insulating film 28: second photosensitive film
29 : 제 2 콘택홀29: second contact hole
본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 폴리 플러그(Poly Plug)의 안정성을 개선하여 소자의 신뢰성을 향상시키는데 적당하도록 한 반도체 소자의 폴리 플러그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a poly plug of a semiconductor device, which is suitable for improving the reliability of a device by improving the stability of a poly plug.
이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 폴리 플러그 제조방법을 설명하면 다음과 같다.Hereinafter, a method for manufacturing a poly plug of a conventional semiconductor device will be described with reference to the accompanying drawings.
제 1 도 (a) - (c)는 종래의 반도체 소자의 폴리 플러그 제조방법을 나타낸 공정단면도이다.1 (a)-(c) are process cross-sectional views showing a conventional method for manufacturing a poly plug of a semiconductor device.
먼저, 제 1 도 (a)에서와 같이 반도체 기판(11)상에 도프트 글래스(Doped Grass)막(12)을 증착하여 고온열처리를 통해 평탄화를 이룬다음 감광막(13)을 전면에 도포하여 스텝퍼(Stepper)를 이용한 노광 및 현상공정으로 콘택홀(Contact Hole)영역을 패터닝(Pattering)한 다음, 식각공정인 에쳐(Etcher)를 이용하여 콘택홀(14)을 형성한다.First, as shown in FIG. 1A, a doped grass film 12 is deposited on the semiconductor substrate 11 to be planarized by high temperature heat treatment, and then the photosensitive film 13 is applied to the entire surface of the stepper. The contact hole region is patterned by an exposure and development process using a stepper, and then the contact hole 14 is formed by using an etching process, which is an etching process.
이어서, 제 1 도 (b)에서와 같이 상기 감광막(13)을 제거하고 상기 콘택홀(14)을 포함한 전면에 폴리 실리콘막(15)을 증착한다.Subsequently, as illustrated in FIG. 1B, the photoresist layer 13 is removed and a polysilicon layer 15 is deposited on the entire surface including the contact hole 14.
그리고, 제 1 도 (c)에서와 같이 에치백(Etch Back) 공정을 이용하여 상기 콘택홀(14)내에 폴리 플러그(16)를 형성한 후, 고온 열처리를 하여 폴리 플러그(16)을 완성한다.Then, the poly plug 16 is formed in the contact hole 14 using an etch back process as shown in FIG. 1 (c), and then the high temperature heat treatment is performed to complete the poly plug 16. .
그러나 이와같은 종래의 반도체 소자의 폴리 플러그 제조방법은 고온 열처리시 에치백된 막 표면이 노출됨에 따라 표면에 이물질이 발생하여 반도체 기판의 간격이 좁을 경우 배선공정의 쇼트(Short)를 유발시켜 그로 인해 장비의 공정처리 능력 및 소자의 신뢰성을 저하하는 문제점이 있었다.However, in the conventional method of manufacturing a poly plug of a semiconductor device, foreign matters are generated on the surface as the surface of the etched back surface is exposed during high temperature heat treatment, and when the gap of the semiconductor substrate is narrow, it causes short circuit of the wiring process. There was a problem of degrading the processability of the equipment and the reliability of the device.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 폴리 플러그 위에 절연막을 형성한 후, 열처리 공정을 수행하여 폴리 플러그의 안정성을 향상시키는데 적당하도록 한 반도체 소자의 폴리 플러그 제조방법을 제공하는 데 그 목적이 있다.The present invention has been made to solve the above problems and to provide a method for manufacturing a poly plug of a semiconductor device suitable for improving the stability of the poly plug by forming an insulating film on the poly plug, and then performing a heat treatment process. There is a purpose.
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 폴리 플러그 제조방법은 반도체 기판상에 도프트 글래스막을 형성하여 고온 열처리로 평탄화시키는 공정과, 상기 도프트 글래스막을 포함한 전면에 감광막을 형성하는 공정과, 상기 감광막을 노광 및 현상 공정으로 패터닝하여 상기 반도체 기판의 표면이 노출되게 콘택홀을 형성하는 공정과, 상기 콘택홀 내부에 폴리 플러그를 형성하는 공정과, 상기 폴리 플러그를 포함한 전면에 제 1 절연막을 형성하는 공정과, 상기 콘택홀 상측의 제 1 절연막을 선택적을 식각하는 공정을 포함하여 이루어짐을 특징으로 한다.Poly plug manufacturing method of a semiconductor device of the present invention for achieving the above object is a step of forming a doped glass film on a semiconductor substrate to planarize by high temperature heat treatment, and a step of forming a photosensitive film on the entire surface including the doped glass film And forming a contact hole so that the surface of the semiconductor substrate is exposed by patterning the photoresist in an exposure and development process, forming a poly plug in the contact hole, and a first surface on the front surface including the poly plug. And forming a dielectric film and selectively etching the first dielectric film over the contact hole.
이하, 첨부된 도면을 참조하여 본 발명의 폴리 플러그 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a method for manufacturing a poly plug according to the present invention will be described in detail with reference to the accompanying drawings.
제 2 도 (a) - (f)는 본 발명의 반도체 소자의 폴리 플러그 제조방법을 나타낸 공정단면도이다.2 (a) to 2 (f) are cross-sectional views illustrating a method for manufacturing a poly plug of a semiconductor device of the present invention.
먼저, 제 2 도 (a)에서와 같이 반도체 기판(21)상에 도프트 글래스막(22)을 증착하여 고온열처리를 통해 평탄화를 이룬 다음 제 1 감광막(23)을 전면에 도포하여 스텝퍼(Stepper)를 이용한 노광 및 현상공정으로 콘택홀(Contact Hole)영역을 패터닝한다.First, as shown in FIG. 2A, the doped glass film 22 is deposited on the semiconductor substrate 21 to be flattened by high temperature heat treatment, and then the first photosensitive film 23 is applied to the entire surface of the stepper. The contact hole region is patterned by an exposure and development process using
그리고 식각공정인 에쳐(Etcher)를 이용하여 상기 반도체 기판(21)의 표면이 노출되도록 제 1 콘택홀(24)을 형성한다.The first contact hole 24 is formed to expose the surface of the semiconductor substrate 21 by using an etchant, an etching process.
이어서, 제 2 도 (b)에서와 같이 상기 제 1 콘택홀(24)을 포함한 전면에 폴리 실리콘막(25)을 형성한다.Next, as shown in FIG. 2B, a polysilicon film 25 is formed on the entire surface including the first contact hole 24.
이어서, 제 2 도 (c)에서와 같이 상기 공정 후 에치백(Etch Back) 공정으로 상기 제 1 감광막(23)의 표면이 노출되도록 상기 폴리 실리콘막(25)을 선택적으로 제거하여 상기 제 1 콘택홀(24)내에 폴리 플러그(26)를 형성하다.Subsequently, as illustrated in FIG. 2C, the polysilicon layer 25 is selectively removed to expose the surface of the first photoresist layer 23 by an etch back process, followed by the first contact. A poly plug 26 is formed in the hole 24.
이때 상기 폴리 실리콘막(25)은 인(P)을 함유하고 인 함유농도 2.0 - 6.0 *E20 atoAt this time, the polysilicon film 25 contains phosphorus (P) and contains a phosphorus concentration of 2.0-6.0 * E20 ato
m/cm으로 한다.It is m / cm.
이어서, 제 2 도 (d)에서와 같이 상기 폴리 플러그(26)를 포함한 전면에 절연막(27)을 형성한 후, 고온 열처리를 실시한다.Subsequently, an insulating film 27 is formed on the entire surface including the poly plug 26 as shown in FIG. 2 (d), and then a high temperature heat treatment is performed.
이때 상기 절연막(27)은 상기 도프트 글래스막(22)과 식각 선택비가 다른 물질이며 식각 선택비는 1 : 2 이상으로 한다.In this case, the insulating layer 27 is a material different from the dopant glass layer 22 in the etching selectivity, and the etching selectivity is 1: 2 or more.
그리고 고온 열처리 온도는 700 - 1000℃로 한다.And high temperature heat processing temperature shall be 700-1000 degreeC.
또한, 상기 절연막(27)의 두께는 50 - 1000 Å으로 형성하고, 상압, 저압, 저압 플라지마 화학기상증착법으로 증착한다.Further, the insulating film 27 is formed to have a thickness of 50 to 1000 kPa, and is deposited by atmospheric pressure, low pressure, and low pressure plasma chemical vapor deposition.
이어 제 2 도 (e)에서와 같이 상기 절연막(27)상에 제 2 감광막(28)을 도포하고 사진식각 공정인 스텝퍼를 이용한 노광 및 현상공정으로 제 2 콘택홀(29)을 패터닝(Patterning)한다.Next, as shown in FIG. 2E, the second photoresist layer 28 is coated on the insulating layer 27, and the second contact hole 29 is patterned by an exposure and development process using a stepper, which is a photolithography process. do.
그리고, 제 2 도 (f)에서와 같이 불산을 이용하여 선택적으로 상기 절연막(27)을 제거하고 다시 잔존하는 상기 제 2 감광막(28)을 제거하므로 폴리 플러그(30)를 완성한다.Then, as shown in FIG. 2 (f), the poly plug 30 is completed by selectively removing the insulating layer 27 and removing the remaining second photosensitive layer 28 again using hydrofluoric acid.
상기 절연막(27)은 상기 폴리 실리콘막(25)과 불산 등의 식각 선택비가 다른 물질이고, 식각 선택비 10 : 1 이상으로 한다.The insulating layer 27 is made of a material having a different etching selectivity from the polysilicon film 25 and hydrofluoric acid, and the like.
이상 설명한 바와 같이 본 발명의 반도체 소자의 폴리 플러그 제조방법은 절연막을 증착하여 고온 열처리를 하는데 열처리시 반도체 기판 간격을 좁혀도 이물질이 억제되고 이로 인해 열처리 장비의 공정 처리 능력이 증대된다.As described above, in the method of manufacturing a poly plug of the semiconductor device of the present invention, a high temperature heat treatment is performed by depositing an insulating film. Even when the semiconductor substrate is shortened during heat treatment, foreign matters are suppressed, thereby increasing the processing capability of the heat treatment equipment.
또한, 불산을 이용한 선택적 식각을 함으로써 절연막과 도프트 글래스막과의 선택비에 따라 콘택홀부 모서리의 경사각도를 낮출 수 있는 효과가 있다.In addition, by selectively etching with hydrofluoric acid it is possible to reduce the inclination angle of the edge of the contact hole according to the selectivity between the insulating film and the doped glass film.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960020647A KR100186504B1 (en) | 1996-06-10 | 1996-06-10 | Manufacturing method of poly plug in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960020647A KR100186504B1 (en) | 1996-06-10 | 1996-06-10 | Manufacturing method of poly plug in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR980005405A KR980005405A (en) | 1998-03-30 |
| KR100186504B1 true KR100186504B1 (en) | 1999-04-15 |
Family
ID=19461346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960020647A KR100186504B1 (en) | 1996-06-10 | 1996-06-10 | Manufacturing method of poly plug in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100186504B1 (en) |
-
1996
- 1996-06-10 KR KR1019960020647A patent/KR100186504B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR980005405A (en) | 1998-03-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH09205145A (en) | Integrated circuit and its manufacture | |
| KR19980080906A (en) | Metallization Method in Semiconductor Devices | |
| US6001541A (en) | Method of forming contact openings and contacts | |
| EP0355339A2 (en) | Process for making self-aligned contacts | |
| KR100186504B1 (en) | Manufacturing method of poly plug in semiconductor device | |
| KR20030000592A (en) | method for manufacturing of semiconductor device with STI/DTI structure | |
| KR100333726B1 (en) | Method of fabricating semiconductor device | |
| KR100367695B1 (en) | Method for forming via contact in semiconductor device | |
| KR0161878B1 (en) | Formation method of contact hole in semiconductor device | |
| KR0162144B1 (en) | Formation method of contact hole in semiconductor device | |
| KR100248626B1 (en) | Method of fabricating semiconductor device | |
| KR100912958B1 (en) | Method for fabricating fine pattern in semiconductor device | |
| KR100430688B1 (en) | Method of forming contact hole of semiconductor device | |
| KR0182176B1 (en) | Method for forming meatal contact hall of semiconductor device | |
| KR100205095B1 (en) | Method for forming bit line of semiconductor device | |
| KR100306905B1 (en) | Contact hole formation method | |
| KR100396685B1 (en) | Interconnection of semiconductor device and manufacturing method thereof | |
| KR0168358B1 (en) | Method of forming fine contact hole of semiconductor device | |
| KR100256809B1 (en) | Method for forming contact hole in semiconductor device | |
| KR100223265B1 (en) | Method for forming a contact of a semiconductor device | |
| KR100314738B1 (en) | Method for forming gate electrode in semiconductor device | |
| KR100328824B1 (en) | Manufacturing method for capacitor | |
| KR100249175B1 (en) | Method for fabricating of capacitor | |
| JPH05129253A (en) | Production of semiconductor device | |
| KR100313942B1 (en) | Method for Forming Contact Hole of Semiconductor Device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20101125 Year of fee payment: 13 |
|
| LAPS | Lapse due to unpaid annual fee |