KR100365746B1 - Method for manufacturing semiconductor device for improving contact resistance - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of reducing contact resistance by preventing over-etching of a lower conductive layer having high topology. CONSTITUTION: A thick lower conductive layer(21) and the first interlayer dielectric(22) are sequentially formed on a substrate. After selectively etching the first interlayer dielectric, a thin lower conductive layer(23) is formed at the etched portion. The second interlayer dielectric(24) is formed on the resultant structure. The second and first interlayer dielectric are dry-etched to expose the thick lower conductive layer(21) and the bottom of the thin lower conductive layer(23). Then, The second and first interlayer dielectric are wet-etched to expose the sidewalls of the thin lower conductive layer(23). An upper conductive layer(27) contacts the exposed thick and thin lower conductive layer(21,23).

Description

Semiconductor Device Manufacturing Method for Improving Contact Resistance

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, when a contact is simultaneously formed in a plurality of lower layer conductors having different topologies, the lower layer conductor having a higher topology is etched excessively and the upper layer conductor The contact forming method which prevents a contact area with a small thing becomes small.

1 is a cross-sectional view of a state in which an upper conductor is contacted to a plurality of lower conductors having different topologies according to the prior art, in which 1 is a lower thick conductor, 2 is a first interlayer insulating film, and 3 is a lower thin film conductor. 4 denotes a second interlayer insulating film, and 5 denotes an upper conductor. Herein, the thin film and the thick film mean a relative thickness.

As shown in the drawing, conventionally, after forming the lower thick conductor 1 and the first interlayer insulating film 2, the lower thin film conductor 3 and the second interlayer insulating film 4 are formed, and then the lower thick film. After forming a contact hole for simultaneously exposing a predetermined portion of the conductor 1 and the lower thin film conductor 3 (partial etching of the interlayer insulating film), the upper conductive material 5 is deposited, and the upper conductive material 5 is formed. And the step of connecting the lower thick film conductor 1 and the lower thin film conductor 1 to each other were completed.

However, since the top and bottom thin film conductors have different topologies, the bottom thin film conductor is excessively etched when the interlayer insulating films 4 and 2 for forming the contact holes are etched. As a result, the contact resistance is poor or increased, which degrades the normal operation of the device.

Of course, in the case of forming the contact hole, when the lower conductive material overetched is a relatively thick film, the contact area is smaller than the thin film, but the contact resistance is the same.

The present invention devised to solve the above problems is a semiconductor device manufacturing method for reducing the contact resistance of the lower layer conductor having a higher topology when the same upper layer conductor is simultaneously contacted to a plurality of lower layer conductors having different topologies. The purpose is to provide.

In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device for simultaneously contacting an upper conductor to a first lower conductor and a second lower conductor having different topologies on a wafer, the method comprising: A first step of sequentially forming a lower conductive material and a first interlayer insulating film; Forming a groove by etching a portion of the first interlayer insulating film in a region where the second lower layer conductor is to be formed, wherein the groove is formed so that the bottom surface of the groove is substantially equal to the surface height of the first lower layer conductor; Step 2; A third step of forming a second lower layer conductor on the first interlayer insulating film in the groove portion, the second lower layer conductor being thinner than the first lower layer conductor; Forming a second interlayer insulating film on the entire surface of the resultant material; A fifth step of forming a contact hole by etching the second and first interlayer insulating layers so that the first lower layer conductor and the second lower layer conductor deposited on the bottom surface of the groove are exposed by using an upper layer contact mask; ; And a sixth step of contacting the upper conductor with each of the exposed first and second layer conductors by depositing an upper conductor.

Preferably, in the fifth step of forming the contact hole in the present invention, the seventh step of dry etching so that the second lower layer conductor deposited on the bottom surface of the groove is exposed, and the sidewall of the second lower layer conductor is Wet etching so that the exposure is characterized in that consisting of an eighth step.

In the case where the second lower conductive layer is a thin film having a relatively thin thickness compared to the first lower conductive layer, when the present invention is applied, the contact area between the first lower conductive layer and the upper conductive layer is lower than that of the prior art. Since it is greatly improved, the contact resistance can be greatly improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the attached drawings 2A to 2D.

2A to 2D are a process chart for forming a contact according to a preferred embodiment of the present invention. First, a lower thick conductor 21 and a first interlayer insulating film 22 are sequentially formed as shown in FIG. 2A, and then the first interlayer is formed. The portion of the insulating layer 22 is etched (on the design rule) where the lower thin film conductor is to be formed, and the target is etched to a height substantially equal to the surface height of the lower thick film conductor 21.

Subsequently, as shown in FIG. 2B, the lower thin film conductor 23 is formed on the etched portion of the first interlayer insulating film 22, and the second interlayer insulating film 24 is formed on the entire structure.

Subsequently, as shown in FIG. 2C, a photoresist layer 25 pattern, which is an upper conductive contact mask, is formed, and the second interlayer insulating layer 24 and the first interlayer insulating layer are formed using the photoresist 25 pattern as an etch mask. (22) is dry-etched to form contact holes 26 exposing predetermined portions of the bottom surface of the lower thick conductor 21 and the lower thin film conductor 23.

Subsequently, the second interlayer insulating film 24 and the first interlayer insulating film 22 are wet-etched to remove the photosensitive film 25 and expose sidewalls of the lower thin film conductor 23. The upper layer 27 is brought into contact with the lower thick conductor 21 and the lower thin film conductor 23 exposed by depositing and patterning the whole 27, and the lower thin film conductor 23 by wet etching. The sidewalls of are exposed to increase the contact area with the upper conductive layer 27 deposited in the subsequent process.

As described above, the present invention, as described above, improves reliability of a device by reducing contact resistance by preventing excessively etched conductors of a plurality of lower layer conductors from being excessively etched to reduce contact area with upper conductors. It works.

1 is a cross-sectional view of a state in which an upper conductor is contacted to a plurality of lower conductors having different topologies according to the prior art;

2A through 2D are contact forming process diagrams in accordance with a preferred embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

21: lower thick film conductor 22: first interlayer insulating film

23: lower layer thin film conductor 24: second interlayer insulating film

25: photosensitive film 26: contact hole

27: upper layer conductor

Claims (2)

A method of manufacturing a semiconductor device for simultaneously contacting an upper conductor with a first lower conductor having a different topography on a wafer, A first step of sequentially forming a first lower layer conductor and a first interlayer insulating film on a substrate on which a predetermined process is completed; Forming a groove by etching a portion of the first interlayer insulating layer in a region where the second lower layer conductor is to be formed, wherein the groove is formed such that the bottom surface of the groove is substantially equal to the surface height of the first lower layer conductor; Step 2; A third step of forming a second lower layer conductor on the first interlayer insulating film in the groove portion, the second lower layer conductor being thinner than the first lower layer conductor; Forming a second interlayer insulating film on the entire surface of the resultant material; A fifth step of forming a contact hole by etching the second and first interlayer insulating layers so that the first lower layer conductor and the second lower layer conductor deposited on the bottom surface of the groove are exposed by using an upper layer contact mask; ; And A sixth step of contacting the upper conductor with each of the exposed first and second layer conductors by depositing an upper conductor A semiconductor device manufacturing method comprising a. The method of claim 1, The fifth step of forming the contact hole, A seventh step of dry etching the second lower layer conductor deposited on the bottom surface of the groove to be exposed; And And an eighth step of performing wet etching to expose sidewalls of the second lower layer conductor.