KR100224778B1 - Fabrication method for semiconductor chip - Google Patents
Fabrication method for semiconductor chip Download PDFInfo
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- KR100224778B1 KR100224778B1 KR1019960070411A KR19960070411A KR100224778B1 KR 100224778 B1 KR100224778 B1 KR 100224778B1 KR 1019960070411 A KR1019960070411 A KR 1019960070411A KR 19960070411 A KR19960070411 A KR 19960070411A KR 100224778 B1 KR100224778 B1 KR 100224778B1
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- forming
- contact hole
- barrier layer
- metal wiring
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 반도체 기판 상부에 제1절연막을 형성하고 상기 제1절연막 상부에 식각장벽층을 형성하며 상기 식각장벽층 및 제1절연막을 식각하여 제1콘택홀을 형성한 다음, 상기 식각장벽층 상부에 제1금속배선을 형성하는 동시에 제1콘택홀을 매립하는 콘택플러그를 형성하고 상기 반도체 기판의 전체표면 상부에 제2절연막을 형성하여 상기 제2절연막을 식각하여 상기 콘택플러그를 노출시키는 제2콘택홀을 형성한 후, 상기 콘택플러그에 접속하여 상기 제 2콘택홀을 매립하는 제2금속배선을 형성하여 후속 공정을 용이하게 실시함으로써 반도체 소자의 수율 및 생산성을 향상시키며, 반도체 소자의 고집적화를 가능하게 하는 효과가 있다.The present invention relates to a method for fabricating a semiconductor device, the method comprising forming a first insulating layer on a semiconductor substrate, forming an etch barrier layer on the first insulating layer, and etching the etch barrier layer and the first insulating layer to form a first contact hole. And forming a contact plug for filling the first contact hole at the same time as forming the first metal wiring on the etch barrier layer and forming a second insulating film on the entire surface of the semiconductor substrate to etch the second insulating film. To form the second contact hole exposing the contact plug, and then to the contact plug to form a second metal wiring to fill the second contact hole, thereby facilitating subsequent steps, thereby increasing the yield and productivity of the semiconductor device. It is possible to improve the efficiency and to enable high integration of the semiconductor device.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는 반도체 디바이스의 제조공정에 있어서 금속콘택 형성시 반도체 기판 상부에 제1금속배선클 형성함과 동시에 콘택플러그를 형성하고, 그 상부에 자기정렬방식으로 제2콘택홀을 형성하고 그에 접속되는 제2금속배선을 형성함으로써 후속 공정을 용이하게 실시할 수 있도록 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. More particularly, in the manufacturing process of a semiconductor device, at the time of forming a metal contact, a contact plug is formed at the same time as the first metal wiring claw is formed on a semiconductor substrate, and a magnet is formed thereon. The present invention relates to a technique for forming a second contact hole in an alignment manner and forming a second metal wiring connected thereto so that subsequent steps can be easily performed.
일반적으로, 반도체소자 제조 공정에서 원하는 패턴을 형성하기 위해 예정된 층을 증착하고, 그 상부에 감광막패턴을 형성하여 식각공정으로 원하는 층을 형성한다.In general, a predetermined layer is deposited to form a desired pattern in a semiconductor device manufacturing process, and a photosensitive film pattern is formed thereon to form a desired layer by an etching process.
그리고, 반도체 기판의 셀 지역에 트랜지스터 등의 액티브 소자를 형성한 다음, 그 상부에서 도전층의 저항을 최소화 하기 위하여 메탈 배선을 사용한다.Then, an active element such as a transistor is formed in the cell region of the semiconductor substrate, and then metal wiring is used to minimize the resistance of the conductive layer thereon.
상기 메탈 배선은 메탈 콘택을 형성한 다음, 메탈층을 증착하고 그 상부에 감광막을 도포하고, 마스크를 이용한 노광 및 현상 공정으로 감광막패턴을 형성하고 이 감광막패턴을 마스크로 이용하여 하부에 노출되는 메탈층을 식각하여 메탈 배선을 형성한다.The metal wiring may form a metal contact, deposit a metal layer, apply a photoresist film thereon, form a photoresist pattern by an exposure and development process using a mask, and use the photoresist pattern as a mask to expose a metal below. The layer is etched to form metal wiring.
한편, 반도체 소자의 고집적화에 따라 반도체 소자의 내부에서 상하의 금속 배선을 연결하는 콘택홀은 자체의 크기와 주변배선과의 간격이 감소되고, 콘택 홀의 지름과 깊이의 비인 에스팩트비(aspect ratio)가 증가함으로써 후속 공정을 실시하는데 문제점이 있다.On the other hand, according to the high integration of the semiconductor device, the contact hole connecting the upper and lower metal wires inside the semiconductor device reduces its size and the distance between the peripheral wiring, and the aspect ratio, which is the ratio of the diameter and depth of the contact hole, is increased. There is a problem in carrying out subsequent processes by increasing.
이에, 본 발명은 상기한 문제점을 해결하기 위한 것으로 반도체 기판 상부에 금속배선을 형성함과 동시에 콘택플러그를 형성한 상태에서 자기정렬방식으로 제2콘택홀을 형성한 다음 제2금속배선을 형성함으로써 후속공정을 용이하게 실시하여 반도체 소자의 수율 및 생산성을 향상시키며, 반도체 소자의 고집적화를 가능하게 하는 반도체 소자의 제조방법을 제공하는 데 그목적이 있다.Accordingly, the present invention is to solve the above problems by forming a metal wiring on the semiconductor substrate and at the same time by forming a second contact hole in a self-aligning manner in the form of a contact plug and then forming a second metal wiring It is an object of the present invention to provide a method for manufacturing a semiconductor device that facilitates subsequent steps to improve the yield and productivity of the semiconductor device and enables high integration of the semiconductor device.
제1a도 내지 제1f도는 본 발명의 일실시에에 따른 반도체 소자의 제조공정도 .1A to 1F are manufacturing process diagrams of a semiconductor device according to one embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 반도체 기판 12 : 제1절연막10 semiconductor substrate 12 first insulating film
14 : 식각장벽층 16 : 제1콘택홀14: etching barrier layer 16: the first contact hole
18 : 제1금속배선 20 : 콘택플러그18: first metal wiring 20: contact plug
22 : 제2절연막 24 : 감광막패턴22: second insulating film 24: photosensitive film pattern
26 : 제2콘택홀 28 : 제2금속배선26: second contact hole 28: second metal wiring
상기 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 제조방법은, 반도체 기판 상부에 제1절연막을 형성하는 공정과, 상기 제1절연막 상부에 식각장벽층을 형성하는 공정과, 상기 식각장벽층 및 제1절연막을 식각하여 제1콘택홀을 형성하는 공정과, 상기 식각장벽층 상부에 제1금속배선을 형성하는 동시에 제1콘택홀을 매립 하는 콘택플러그를 형성하는 공정과, 상기 반도체 기판의 전체표면 상부에 제2절연막을 형성하는 공정과, 상기 제2절연막을 식각하여 상기 콘택플러그를 노출시키는 제2콘택홀을 형성 하는 공정과, 상기 콘택플러그에 접속하여 상기 제2콘택홀을 매립하는 제2금속배선을 형성하는 공정을 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a process of forming a first insulating film on a semiconductor substrate, a process of forming an etch barrier layer on the first insulating film, the etching barrier layer and Etching the first insulating layer to form a first contact hole, forming a first metal wiring on the etch barrier layer and forming a contact plug to fill the first contact hole, and the entire semiconductor substrate Forming a second insulating film over the surface, forming a second contact hole to expose the contact plug by etching the second insulating film, and filling the second contact hole by connecting the contact plug. It characterized in that it comprises a step of forming a two-metal wiring.
이하 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
먼저, 반도체 기판(10) 상부에 일정 두께의 제1절연막(12)과 식각장벽층(14) 를 순차적으로 형성한다.First, the first insulating layer 12 and the etching barrier layer 14 having a predetermined thickness are sequentially formed on the semiconductor substrate 10.
여기서, 상기 제1절연막(12)은 다결정 실리콘으로 구성되고, 식각장벽층(14) 은 질화막으로 이루어져 있다. (제1a도 참조)Here, the first insulating layer 12 is made of polycrystalline silicon, and the etching barrier layer 14 is made of a nitride film. (See also Figure 1a)
다음, 콘택마스크를 이용하여 콘택부분으로 예정되어 노출되는 콘택홀(16)이 형성되도록 식각하여 상기 식각장벽층(14)과 제1절연막(12)을 제거한 다음, 식각장벽층패턴 및 제1절연막패턴을 형성한다. (제1b도 참조)Next, the etch barrier layer 14 and the first insulating layer 12 are removed by etching to form a contact hole 16 that is predetermined and exposed as a contact portion using a contact mask, and then the etch barrier layer pattern and the first insulating layer are removed. Form a pattern. (See also Figure 1b)
그 다음, 상기 구조의 전표면에 금속배선으로 이루어진 도전층(도시 않됨)을 일정 두께로 형성한 다음 마스크로 식각하여 제1금속배선(18)을 형성함과 동시에 상기 제 1콘택홀(16)을 매립하는 콘택플러그(20)을 형성한다. (제1c도 참조)Subsequently, a conductive layer (not shown) made of metal wirings is formed on the entire surface of the structure to a predetermined thickness and then etched with a mask to form the first metal wirings 18 and the first contact hole 16. Forming contact plug 20 to fill the. (See also Figure 1c)
다음, 상기 구조의 전표면에 일정 두께의 제2절연막(22)과 감광막을 도포한 후, 노광마스크를 이용하여 노광 및 현상공정을 거쳐 감광막패턴(24)을 형성한다. (제1d도참조)Next, after the second insulating film 22 and the photosensitive film having a predetermined thickness are coated on the entire surface of the structure, the photosensitive film pattern 24 is formed through an exposure and development process using an exposure mask. (See also 1d)
그 다음, 상기 감광막패턴(24)를 마스크로 식각하여 상기 콘택플러그(20)가 노출되는 제2콘택홀(26)을 형성한 다음, 상기 구조의 전표면에 도전층으로 상기 제2콘택홀(26)과 접속되는 제2금속배선(28)를 형성하여 본 발명의 제조공정을 완료한다.Thereafter, the photoresist pattern 24 is etched using a mask to form a second contact hole 26 through which the contact plug 20 is exposed, and then the second contact hole as a conductive layer on the entire surface of the structure. A second metal wiring 28 connected to 26 is formed to complete the manufacturing process of the present invention.
여기서, 상기 제 2콘택홀(26)은 상기 제1절연막(12) 상부에 상기 식각장벽층 (14)이 형성되어 있기 때문에 약간의 정렬이 어긋나도 상기 콘택플러그(20) 부분외에는 콘택이 형성되지 않아 자기정렬 콘택이 형성되게 된다. (제1e도 및 제1f도 참조)Here, since the etch barrier layer 14 is formed on the first insulating layer 12 in the second contact hole 26, no contact is formed outside the contact plug 20 even if a slight misalignment occurs. As a result, self-aligned contacts are formed. (See Figures 1e and 1f)
상기한 바와같이 본 발명에 따른 반도체 소자의 제조방법은 후속공정을 용이 하게 실시하게 함으로써 반도체 소자의 수율 및 생산성을 향상시키며, 반도체 소자의 고집적화를 가능하게 하는 효과가 있다.As described above, the method for manufacturing a semiconductor device according to the present invention has an effect of improving the yield and productivity of the semiconductor device by easily performing the subsequent steps, and enabling high integration of the semiconductor device.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960070411A KR100224778B1 (en) | 1996-12-23 | 1996-12-23 | Fabrication method for semiconductor chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960070411A KR100224778B1 (en) | 1996-12-23 | 1996-12-23 | Fabrication method for semiconductor chip |
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| Publication Number | Publication Date |
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| KR19980051509A KR19980051509A (en) | 1998-09-15 |
| KR100224778B1 true KR100224778B1 (en) | 1999-10-15 |
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| KR1019960070411A KR100224778B1 (en) | 1996-12-23 | 1996-12-23 | Fabrication method for semiconductor chip |
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