KR20000045910A - Manufacturing method of fuse box of semiconductor device - Google Patents
Manufacturing method of fuse box of semiconductor device Download PDFInfo
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- KR20000045910A KR20000045910A KR1019980062530A KR19980062530A KR20000045910A KR 20000045910 A KR20000045910 A KR 20000045910A KR 1019980062530 A KR1019980062530 A KR 1019980062530A KR 19980062530 A KR19980062530 A KR 19980062530A KR 20000045910 A KR20000045910 A KR 20000045910A
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- South Korea
- Prior art keywords
- fuse box
- forming
- metal wiring
- interlayer insulating
- insulating film
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 22
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 238000002161 passivation Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 52
- 239000010409 thin film Substances 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 239000010937 tungsten Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 5
- 238000000151 deposition Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 소자 제조 공정 중 퓨즈 박스 제조 방법에 관한 것으로, 특히 반도체 소자의 퓨즈 박스 형성시 퓨즈 박스 가아드링(Guard Ring) 지역에 기존의 금속 콘택 그리고 그 위에 금속패턴이 적층으로 형성되는 구조를 없애 퓨즈 박스 구조가 칩에 차기하는 면적을 줄이는 동시에 칩의 신뢰성 특성을 향상시키기 위한 반도체 소자의 퓨즈 박스 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a fuse box during a semiconductor device manufacturing process. In particular, the present invention relates to a structure in which an existing metal contact and a metal pattern are stacked on the fuse box guard ring region when the fuse box is formed. The present invention relates to a method for manufacturing a fuse box of a semiconductor device for reducing the area occupied by a fuse box structure on a chip and improving the reliability characteristics of the chip.
반도체소자의 집적도가 증가함에 따라 퓨즈 박스가 칩의 전체 면적에서 차지하는 면적을 줄여야 하는 문제가 발생하고, 퓨즈 박스의 구조를 단순화 시켜야 하는 문제가 발생된다.As the degree of integration of semiconductor devices increases, a problem arises in that the fuse box occupies a total area of the chip, and a problem in that the structure of the fuse box is simplified.
종래에는 퓨즈 박스 제조시에 퓨즈가 형성되는 부분 주위에 제1금속콘택, 제1금속배선, 제2금속콘택 및 제2금속배선을 차례로 형성시키는 방법을 주로 이용하였다.Conventionally, a method of sequentially forming a first metal contact, a first metal wiring, a second metal contact, and a second metal wiring around a portion where a fuse is formed in manufacturing a fuse box is mainly used.
도 1a 내지 도 1j는 종래기술에 따른 반도체소자의 퓨즈박스 제조공정을 도시한 단면도들이다.1A to 1J are cross-sectional views illustrating a fuse box manufacturing process of a semiconductor device according to the related art.
도 1a를 참조하면, 실리콘기판(1)에 제1층간절연막(2)과 제2층간절연막(3)을 형성한 단면도이다.Referring to FIG. 1A, a cross-sectional view of forming a first interlayer insulating film 2 and a second interlayer insulating film 3 on a silicon substrate 1 is shown.
도 1b를 참조하면, 퓨즈 박스에서 칩 내부로 수분 침투를 방지하기 위한 제1금속콘택 패턴, 즉 상기 제1층간절연막(2)과 제2층간절연막(3)을 식각한다.Referring to FIG. 1B, a first metal contact pattern, that is, the first interlayer insulating layer 2 and the second interlayer insulating layer 3, is etched to prevent moisture from penetrating into the chip from the fuse box.
도 1c를 참조하면, 제1금속배선(4)박막을 적층한다.Referring to FIG. 1C, a first metal wiring 4 thin film is stacked.
도 1d를 참조하면, 상기 제1금속배선(4) 박막 상부에 광막을 도포하고 이를 제1금속배선 마스크를 이용한 노광 및 현상공정으로 패터닝하여 감광막패턴을 형성하고 이를 마스크로하여 상기 제1금속배선(4)박막을 식각하여 제1금속배선(4)을 형성한다. 그리고, 상기 감광막패턴을 제거한다.Referring to FIG. 1D, a photo film is coated on the thin film of the first metal wiring 4 and patterned by an exposure and development process using a first metal wiring mask to form a photoresist pattern, and the first metal wiring is formed as a mask. (4) The thin film is etched to form the first metal wiring 4. Then, the photoresist pattern is removed.
도 1e를 참조하면, 상기 공정 후 제1금속배선(4)과 제2금속배선을 절연시키기 위한 제3층간절연막(5)을 적층시킨다.Referring to FIG. 1E, after the process, a third interlayer insulating film 5 for insulating the first metal wiring 4 and the second metal wiring is stacked.
도 1f를 참조하면, 상기 공정 후 제2금속배선 콘택마스크(도시안됨), 즉 비아콘택마스크를 이용한 식각공정으로 상기 제3층간절연막(5)을 식각하여 상기 제1금속배선(4)을 노출시키는 콘택홀을 형성한다.Referring to FIG. 1F, after the process, the third interlayer insulating layer 5 is etched by an etching process using a second metal wiring contact mask (not shown), that is, a via contact mask to expose the first metal wiring 4. Contact holes are formed.
도 1g를 참조하면, 상기 제1금속배선(4)에 접속되는 제2금속배선(6)박막을 전체표면상부에 적층시킨다.Referring to FIG. 1G, a thin film of the second metal wiring 6 connected to the first metal wiring 4 is laminated on the entire surface.
도 1h를 참조하면, 제2금속배선 마스크(도시안됨)를 식각공정으로 상기 제2금속배선(6)박막을 식각하여 상기 제1금속배선(4)에 접속되는 제2금속배선(6)을 형성한다.Referring to FIG. 1H, the second metal wiring 6 is connected to the first metal wiring 4 by etching the second metal wiring 6 thin film by etching the second metal wiring mask (not shown). Form.
도 1i를 참조하면, 상기 공정 후 패턴 전체에 패시베이션(Passivation)막(7)을 적층시킨다.Referring to FIG. 1I, a passivation film 7 is laminated on the entire pattern after the process.
도 1j를 참조하면, 퓨즈막 위의 산화막을 적절하게 남기기 위한 감광막을 이용하여 상기 패시베이션막(7), 제3층간절연막(5), 제2층간절연막(3)을 차례로 식각시킨다. 이때, 상기 제2층간절연막(3) 식각 공정은 퓨즈 위에 적당히 남은 산화막을 조절하여 일부만을 식각한다.Referring to FIG. 1J, the passivation film 7, the third interlayer insulating film 5, and the second interlayer insulating film 3 are sequentially etched using a photosensitive film for properly leaving an oxide film on the fuse film. At this time, in the etching process of the second interlayer insulating film 3, only a portion of the oxide film is etched by adjusting the oxide film remaining on the fuse.
이와 같이 상기의 패턴으로 퓨즈 박스를 형성하는 경우 퓨즈 박스의 면적이 커져 결국에는 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, in the case of forming the fuse box in the above pattern, the area of the fuse box is increased, which makes it difficult to integrate the semiconductor device.
본 발명의 목적은 상기한 종래기술의 문제점을 해결하기 위하여, 칩의 신뢰성 특성을 향상시키는 동시에 퓨즈 박스가 칩에 차지하는 면적을 줄여 반도체소자의 고집적화를 가능하게 하는 반도체소자의 퓨즈박스 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a fuse box of a semiconductor device, which enables high integration of semiconductor devices by improving the reliability characteristics of the chip and reducing the area occupied by the fuse box on the chip. It is.
도 1a 내지 도 1j는 종래기술에 따른 반도체 소자의 퓨즈 박스 제조 방법을 도시한 단면도들,1A to 1J are cross-sectional views illustrating a method of manufacturing a fuse box of a semiconductor device according to the prior art;
도 2a 내지 도 2l는 본 발명의 실시예에 따른 반도체 소자의 퓨즈 박스 제조 방법을 도시한 단면도들.2A to 2L are cross-sectional views illustrating a method of manufacturing a fuse box of a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 실리콘 기판 2 : 제1층간절연막DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 First interlayer insulation film
3 : 제2층간절연막 4 : 제1금속배선박막3: second interlayer insulating film 4: first metal wiring thin film
5 : 제3층간절연막 6 : 제2금속배선박막5: third interlayer insulating film 6: second metal wiring thin film
7 : 패시베이션막 8 : 다결정실리콘막7: passivation film 8: polycrystalline silicon film
상기 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 퓨즈박스 제조 방법은, 실리콘 기판에 제1층간절연막을 형성하고 그 상부에 퓨즈박스 마스크를 이용하여 퓨즈 박스가 형성될 부분에만 도전체를 형성하는 단계와, 전 표면상부에 제2층간절연막을 형성하는 단계와, 퓨즈박스 마스크를 이용하여 상기 제2층간절연막을 식각하는 단계와, 상기 제2층간절연막의 식각 측벽에 제1금속배선 박막으로 스페이서를 형성하는 단계와, 전체표면상부에 제3층간절연막을 형성하는 단계와, 상기 퓨즈박스 마스크를 이용한 식각공정으로 상기 제3층간절연막을 일정두께 식각하여 퓨즈박스 영역에 상기 제3층간절연막을 남기는 단계와, 상기 제1층간절연막 상부 구조물 측벽에 제2금속배선 박막으로 스페이서를 형성하는 단계와, 전체표면상부에 패시베이션막을 형성하고 상기 퓨즈박스 마스크를 이용한 식각공정으로 패터닝하여 퓨즈박스를 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a fuse box of a semiconductor device according to the present invention includes forming a first interlayer insulating film on a silicon substrate and forming a conductor only on a portion where a fuse box is to be formed using a fuse box mask thereon. Forming a second interlayer dielectric layer over the entire surface; etching the second interlayer dielectric layer using a fuse box mask; and forming a first metal interconnect thin film on an etch sidewall of the second interlayer dielectric layer. Forming a third interlayer insulating film over the entire surface, and etching the third interlayer insulating film to a predetermined thickness by an etching process using the fuse box mask to leave the third interlayer insulating film in the fuse box region. Forming a spacer on the sidewalls of the first interlayer insulating film upper structure, and forming a spacer on the entire surface of the first interlayer insulating film; And forming a fuse box by patterning the etching process using the fuse box mask.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2l은 본 발명의 실시예에 따른 반도체소자의 퓨즈박스 제조공정을 도시한 단면도들이다.2A to 2L are cross-sectional views illustrating a process of manufacturing a fuse box of a semiconductor device according to an exemplary embodiment of the present invention.
먼저, 도 2a를 참조하면, 실리콘기판(1)에 제1층간절연막(2)과 다결정실리콘막(8)을 차례로 적층한다. 여기서 상기 다결정실리콘막(8)을 적층시키는 이유는 후속공정에서 퓨즈 박스가 형성될 부분에 제2층간절연막 식각공정, 즉 제1금속배선 콘택공정시 상기 제1층간절연막(2)이 식각되는 현상을 방지하는 식각정지층으로 사용된다.First, referring to FIG. 2A, a first interlayer insulating film 2 and a polysilicon film 8 are sequentially stacked on the silicon substrate 1. The reason why the polysilicon layer 8 is stacked is a phenomenon in which the first interlayer dielectric layer 2 is etched during the second interlayer dielectric layer etching process, that is, the first metal wiring contact process, in the portion where the fuse box is to be formed in a subsequent process. Used as an etch stop layer to prevent
그 다음, 도 2b를 참조하면 상기 공정 후 퓨즈 박스가 형성될 부분에만 다결정실리콘막(8)을 남기게 하기 위한 감광막 패턴으로 다결정실리콘막(8)을 식각시킨다.Next, referring to FIG. 2B, the polysilicon film 8 is etched with a photoresist pattern for leaving the polysilicon film 8 only in the portion where the fuse box is to be formed after the process.
그리고, 도 2c를 참조하면, 상기 전표면 상부에 제2층간절연막(3)을 적층한다.Referring to FIG. 2C, a second interlayer insulating film 3 is stacked on the entire surface.
도 2d를 참조하면, 상기 공정 후 퓨즈 박스가 형성될 부분의 제2층간절연막(3)을 식각하는 제1금속배선 콘택 식각 공정을 실시한다. 이때, 상기 다결정실리콘4막(8) 위에 있는 제2층간절연막(3)만 식각되고 상기 다결정실리콘막(8)은 남게 된다.Referring to FIG. 2D, after the process, the first metal wiring contact etching process of etching the second interlayer insulating film 3 in the portion where the fuse box is to be formed is performed. At this time, only the second interlayer insulating film 3 on the polysilicon 4 film 8 is etched and the polysilicon film 8 remains.
그 다음, 도 2e 및 도 2f를 참조하면 전체표면상부에 제1금속배선(4)박막을 형성한다. 상기 제1금속배선(4) 박막을 이방성식각하여 상기 제2층간절연막(3)의 측벽에 제1금속배선(4)박막으로 스페이서를 형성한다. 이때, 상기 다결정실리콘막(8)도 식각되어 상기 제1층간절연막(2)을 노출시킨다.2E and 2F, a first metal wiring 4 thin film is formed over the entire surface. The thin film of the first metal wiring 4 is anisotropically etched to form a spacer on the sidewall of the second interlayer insulating film 3 with the thin film of the first metal wiring 4. At this time, the polysilicon film 8 is also etched to expose the first interlayer insulating film 2.
그리고, 도 2g 및 도 2h를 참조하면 전체표면상부에 제3층간절연막(5)을 적층하고 퓨즈 박스가 형성될 부분의 제3층간절연막(5) 식각 공정 즉, 제2금속배선 콘택 식각 공정을 실시한다. 이때, 상기 제2금속배선 콘택식각공정은 상기 제1층간절연막(2) 상부에 일정두께의 제3층간절연막이 남도록 실시한다.2G and 2H, the third interlayer dielectric layer 5 is laminated on the entire surface and the third interlayer dielectric layer 5 etching process, that is, the second metal wiring contact etching process, is performed. Conduct. In this case, the second metal wiring contact etching process may be performed such that a third interlayer insulating film having a predetermined thickness remains on the first interlayer insulating film 2.
그 다음, 도 2i 및 도 2j를 참조하면 상기 패턴 위에 제2금속배선(6)박막을 적층하고 이를 이방성식각하여 상기 제1층간절연막(2) 상부 구조물 측벽에 제2금속배선(6)박막으로 스페이서를 형성한다. 이때, 상기 스페이서는 상기 제1금속배선(4) 스페이서와 연결되고, 상기 제1금속배선(4) 스페이서는 상기 다결정실리콘막(8)과 연결된 형상으로 형성된다.Next, referring to FIGS. 2I and 2J, a second metal wiring 6 thin film is stacked on the pattern and anisotropically etched to form a second metal wiring 6 thin film on the sidewall of the upper structure of the first interlayer insulating film 2. Form a spacer. In this case, the spacer is connected to the first metal wiring 4 spacer, and the first metal wiring 4 spacer is formed in a shape connected to the polycrystalline silicon film 8.
그리고, 전체표면상부에 패시베이션막(7)을 적층하고 나서 퓨즈 박스가 형성될 부분의 패시베이션막(7)을 식각함으로써 퓨즈박스를 형성한다. 이때, 상기 패시베이션막(7) 식각 공정시 퓨즈 상부에 적당히 남은 제3층간절연막(5)이 일정두께 식각된다.Then, the passivation film 7 is laminated on the entire surface, and then the passivation film 7 of the portion where the fuse box is to be formed is etched to form a fuse box. At this time, during the passivation film 7 etching process, the third interlayer insulating film 5 that is appropriately left on the fuse is etched to a predetermined thickness.
상기와 같이 본 발명은 퓨즈 박스의 구조를 단순화시켜 퓨즈 박스가 칩에 차지하는 면적을 줄일 수 있으며 동시에 칩의 신뢰성 특성을 향상시킬 수 있다.As described above, the present invention can simplify the structure of the fuse box to reduce the area occupied by the fuse box on the chip and at the same time improve the reliability characteristics of the chip.
상기한 바와 같이 본 발명에 따른 반도체소자의 퓨즈박스 제조방법은, 퓨즈 박스 형성시 퓨즈 박스 가아드링 지역에 기존의 제1금속배선 콘택 및 제1금속배선 적층으로 형성되는 구조를 없애 퓨즈 박스 구조가 칩에 차지하는 면적을 줄이는 동시에 칩의 신뢰성 특성을 향상시킬 수 있는 효과가 있다.As described above, in the method of manufacturing a fuse box of a semiconductor device according to the present invention, the fuse box structure is eliminated by eliminating a structure in which the first metal wiring contact and the first metal wiring stack are formed in the fuse box guard ring region when the fuse box is formed. It has the effect of reducing the area occupied by the chip and at the same time improving the reliability characteristics of the chip.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980062530A KR20000045910A (en) | 1998-12-30 | 1998-12-30 | Manufacturing method of fuse box of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980062530A KR20000045910A (en) | 1998-12-30 | 1998-12-30 | Manufacturing method of fuse box of semiconductor device |
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| Publication Number | Publication Date |
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| KR20000045910A true KR20000045910A (en) | 2000-07-25 |
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| KR1019980062530A KR20000045910A (en) | 1998-12-30 | 1998-12-30 | Manufacturing method of fuse box of semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020017589A (en) * | 2000-08-31 | 2002-03-07 | 박종섭 | Fuse box and method for forming the same |
| KR100819551B1 (en) * | 2006-10-20 | 2008-04-07 | 삼성전자주식회사 | Semiconductor device having moistureproof dam and methods of fabricating the same |
-
1998
- 1998-12-30 KR KR1019980062530A patent/KR20000045910A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020017589A (en) * | 2000-08-31 | 2002-03-07 | 박종섭 | Fuse box and method for forming the same |
| KR100819551B1 (en) * | 2006-10-20 | 2008-04-07 | 삼성전자주식회사 | Semiconductor device having moistureproof dam and methods of fabricating the same |
| US7659601B2 (en) | 2006-10-20 | 2010-02-09 | Samsung Electronics Co., Ltd. | Semiconductor device having moisture-proof dam and method of fabricating the same |
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