KR20000044471A - Method for forming contact hole of semiconductor device and structure of contact hole - Google Patents
Method for forming contact hole of semiconductor device and structure of contact hole Download PDFInfo
- Publication number
- KR20000044471A KR20000044471A KR1019980060969A KR19980060969A KR20000044471A KR 20000044471 A KR20000044471 A KR 20000044471A KR 1019980060969 A KR1019980060969 A KR 1019980060969A KR 19980060969 A KR19980060969 A KR 19980060969A KR 20000044471 A KR20000044471 A KR 20000044471A
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- Prior art keywords
- contact hole
- forming
- semiconductor device
- interlayer insulating
- etching
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000011229 interlayer Substances 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000004888 barrier function Effects 0.000 abstract 5
- 239000011521 glass Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 장치에 관한 것으로, 특히 반도체 장치의 콘택홀 형성방법 및 그 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device and a structure thereof.
반도체 장치의 고집적화 및 고속화에 따라, 반도체 메모리 셀을 구성하는 패턴들의 면적에 있어서도 고집적화가 요구되고 있다. 즉, 배선의 넓이와 배선과 배선 사이의 간격이 감소됨은 물론이고, 반도체 기판에 형성되어 있는 고립된 소자 영역들을 전기적으로 연결하기 위한 콘택의 면적 또한 점차 미세화되고 있는 실정이다. 그 중에서도 콘택은 우선 콘택홀내에 전도성 물질을 채워넣음으로써 형성되어지는데 상기 콘택홀을 형성하기 위해서는 얼라인 마진(align margin), 소자분리 마진(isolation margin) 등이 고려되어야 한다.Background Art With the high integration and high speed of semiconductor devices, high integration is also required in the area of patterns constituting semiconductor memory cells. That is, the area of the wiring and the distance between the wiring and the wiring are reduced, as well as the area of the contact for electrically connecting the isolated device regions formed in the semiconductor substrate is gradually miniaturized. In particular, the contact is formed by first filling a conductive material in the contact hole. In order to form the contact hole, an alignment margin and an isolation margin must be considered.
한편, 이러한 콘택홀은 건식식각공정에 의해 형성되는 것이 일반적인데, 반도체 장치의 집적도가 증가됨에 따라 콘택홀의 종횡비가 점차 증가되고 있다. 이처럼 콘택홀의 종횡비가 증가됨에 따라 식각공정을 진행함에 있어서 여러 가지 어려움을 겪고 있으며, 상기 콘택홀을 도전막으로 채우는 과정에서도 보이드(void)등과 같은 문제점이 야기되고 있다. 따라서, 본 분야에서는 콘택홀의 종횡비를 보다 줄여보고자, 층간절연막들을 얇게 증착하는 방법을 시도하였다.On the other hand, such a contact hole is generally formed by a dry etching process, the aspect ratio of the contact hole is gradually increased as the degree of integration of the semiconductor device is increased. As the aspect ratio of the contact hole increases, various difficulties are encountered in the etching process, and a problem such as voids is caused even when the contact hole is filled with a conductive film. Therefore, in this field, in order to further reduce the aspect ratio of the contact hole, a method of thinly depositing the interlayer insulating films is attempted.
도 1은 종래 방법에 따라 콘택홀이 형성되어 있는 반도체 장치의 단면도이다. 도면을 참조하면, 반도체 기판(10) 상에 제1도전막(12), 층간절연막(14) 및 제2도전막(16)이 형성되어 있다. 그리고, 상기 제2도전막(16)과 접촉하는 콘택을 형성하기 위한 콘택홀(18)이 형성되어 있다.1 is a cross-sectional view of a semiconductor device in which contact holes are formed according to a conventional method. Referring to the drawings, the first conductive film 12, the interlayer insulating film 14, and the second conductive film 16 are formed on the semiconductor substrate 10. In addition, a contact hole 18 for forming a contact in contact with the second conductive film 16 is formed.
그러나, 상기 도 1에서 보여지듯이, 층간절연막(14)의 두께를 얇게 형성하게 되면 콘택홀을 형성하기 위한 식각공정시 층간절연막이 과도식각(over etch)되어 하부의 제1도전막(12)이 노출되는 문제점이 있다. 그 결과, 상기 콘택홀(18)에 후속의 공정을 통해 채워지게될 도전막(콘택)과 상기 제1도전막(12)이 서로 전기적으로 단락(short)되어 반도체 장치에 오동작을 유발시키게 된다.However, as shown in FIG. 1, when the thickness of the interlayer insulating layer 14 is formed to be thin, the interlayer insulating layer is overetched during the etching process for forming the contact hole so that the lower first conductive layer 12 is etched. There is a problem that is exposed. As a result, the conductive film (contact) to be filled in the contact hole 18 through a subsequent process and the first conductive film 12 are electrically shorted with each other to cause a malfunction in the semiconductor device.
따라서 본 발명의 목적은, 콘택홀 형성을 위한 층간절연막 식각시, 상기 층간절연막의 과도식각을 방지할 수 있는 콘택홀 형성방법 및 그 구조를 제공함에 있다.Accordingly, an object of the present invention is to provide a method and a structure for forming a contact hole capable of preventing excessive etching of the interlayer insulating layer during the etching of the interlayer insulating layer for forming the contact hole.
본 발명의 다른 목적은, 콘택홀 형성을 위한 식각공정으로 인해 하부 도전막이 노출되지 않는 콘택홀 형성방법 및 그 구조를 제공함에 있다.Another object of the present invention is to provide a method for forming a contact hole and a structure in which a lower conductive layer is not exposed due to an etching process for forming a contact hole.
상기의 목적들을 달성하기 위해서 본 발명에서는, 반도체 장치의 콘택홀 형성방법에 있어서: 반도체 기판에 제1도전막 및 제1층간절연막을 형성하는 단계와; 상기 제1층간절연막 상부에 후속의 식각공정시 상기 제1층간절연막의 식각을 방지하기 위한 식각저지막을 형성하는 단계와; 상기 식각저지막 상부에 제2도전막 및 제2층간절연막을 형성한 뒤, 상기 식각저지막이 형성되어 있는 영역을 식각하는 단계를 포함함을 특징으로 하는 반도체 장치의 콘택홀 형성방법을 제공한다.In order to achieve the above objects, the present invention provides a method of forming a contact hole in a semiconductor device comprising the steps of: forming a first conductive film and a first interlayer insulating film in a semiconductor substrate; Forming an etch stop layer on the first interlayer dielectric layer to prevent etching of the first interlayer dielectric layer during a subsequent etching process; And forming a second conductive layer and a second interlayer insulating layer on the etch stop layer, and then etching a region where the etch stop layer is formed.
또한 상기의 목적들을 달성하기 위해서 본 발명에서는, 반도체 장치의 콘택홀 구조에 있어서; 콘택홀 하부에 층간절연막의 과도한 식각을 방지하기 위한 식각저지막을 구비함을 특징으로 하는 반도체 장치의 콘택홀 구조를 제공한다.In addition, in order to achieve the above objects, in the present invention, in the contact hole structure of the semiconductor device; A contact hole structure of a semiconductor device is provided below the contact hole, wherein an etch stop layer is provided to prevent excessive etching of the interlayer insulating layer.
도 1은 종래 방법에 따라 콘택홀이 형성되는 있는 반도체 장치의 단면도이다.1 is a cross-sectional view of a semiconductor device in which contact holes are formed according to a conventional method.
도 2a 및 도 2b는 본 발명의 바람직한 실시예에 따른 콘택홀이 형성되어 있는 반도체 장치의 단면도들이다.2A and 2B are cross-sectional views of a semiconductor device in which a contact hole is formed according to a preferred embodiment of the present invention.
이하, 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 및 도 2b는 본 발명의 바람직한 실시예에 따른 콘택홀 형성방법 및 그 구조를 설명하기 위한 반도체 장치의 단면도들이다.2A and 2B are cross-sectional views of a semiconductor device for explaining a contact hole forming method and a structure thereof according to a preferred embodiment of the present invention.
먼저, 도 2a를 참조하면, 반도체 기판(100) 상에 제1층간절연막(102)을 증착한 뒤, 제1도전막(104)을 형성한다. 이어서, 상기 제1도전막(104)이 형성되어 있는 제1층간절연막(102) 상에 제2층간절연막(106)을 증착한다. 이때, 상기 제1층간절연막(102) 및 제2층간절연막(106)은 피에스지(PSG:Phosphorus Silicon Glass), 비피에스지(BPSG:Boron Phosphorus Silicon Glass) 또는 유에스지(USG:Undoped Silicon Glass)등으로 형성하는 것이 바람직하다.First, referring to FIG. 2A, after the first interlayer insulating film 102 is deposited on the semiconductor substrate 100, the first conductive film 104 is formed. Subsequently, a second interlayer insulating film 106 is deposited on the first interlayer insulating film 102 on which the first conductive film 104 is formed. In this case, the first interlayer insulating film 102 and the second interlayer insulating film 106 may be PSG (Phosphorus Silicon Glass), BPSG (Boron Phosphorus Silicon Glass) or USG (Undoped Silicon Glass). It is preferable to form.
계속해서, 상기 제2층간절연막(106) 상에 SiN 또는 SiON과 같이 상기 제2층간절연막(106)과 식각선택비가 우수한 절연막을 증착한다. 그리고 나서, 상기 절연막을 패터닝하여 콘택홀이 형성되어질 영역에 식각저지막(108)을 형성한다. 이러한 식각저지막(108)은 콘택홀을 형성하기 위한 후속의 식각공정시에 상기 제2절연막(106)이 식각되는 것을 저지하여 제1도전막(104)이 노출되는 것을 방지하게 된다.Subsequently, an insulating film having excellent etching selectivity with the second interlayer insulating film 106, such as SiN or SiON, is deposited on the second interlayer insulating film 106. Then, the insulating layer is patterned to form an etch stop layer 108 in the region where the contact hole is to be formed. The etch stop layer 108 prevents the second insulating layer 106 from being etched during a subsequent etching process for forming a contact hole, thereby preventing the first conductive layer 104 from being exposed.
도 2b를 참조하면, 상기 식각저지막(108)이 형성되어 있는 상기 결과물에 제3층간절연막(110) 및 제2도전막(112)을 형성한 뒤, 사진 및 식각공정을 실시하여 소정의 영역에 콘택홀(114)을 형성한다.Referring to FIG. 2B, a third interlayer insulating film 110 and a second conductive film 112 are formed on the resultant on which the etch stop film 108 is formed, and then a photograph and an etching process are performed. A contact hole 114 is formed in the hole.
상기한 바와 같이 본 발명에 따르면, 콘택홀이 형성되어질 영역에 미리 식각저지막을 형성한다. 그 결과, 콘택홀을 형성하기 위한 사진 및 식각공정시 층간절연막의 과도 식각이 방지되어 하부의 도전막이 노출되는 문제점이 해소되어 후속의 콘택형성시 상기 하부 도전막과의 전기적 단락이 방지되는 효과가 있다.As described above, according to the present invention, the etch stop layer is formed in advance in the region where the contact hole is to be formed. As a result, the problem of preventing excessive etching of the interlayer insulating film during the photolithography and etching process to form the contact hole and exposing the lower conductive film is solved. have.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980060969A KR20000044471A (en) | 1998-12-30 | 1998-12-30 | Method for forming contact hole of semiconductor device and structure of contact hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980060969A KR20000044471A (en) | 1998-12-30 | 1998-12-30 | Method for forming contact hole of semiconductor device and structure of contact hole |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000044471A true KR20000044471A (en) | 2000-07-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980060969A KR20000044471A (en) | 1998-12-30 | 1998-12-30 | Method for forming contact hole of semiconductor device and structure of contact hole |
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| KR (1) | KR20000044471A (en) |
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1998
- 1998-12-30 KR KR1019980060969A patent/KR20000044471A/en not_active Application Discontinuation
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