KR0165373B1 - Semiconductor memory device & its fabrication method - Google Patents

Abstract

Disclosed are a semiconductor memory device and a method of manufacturing the same, which simultaneously form a first contact hole and a second contact hole in one insulating film. The memory device of the present invention comprises a gate electrode formed on a semiconductor substrate, a drain and a source formed on the semiconductor substrate, a pad polysilicon (second embodiment) formed on the drain and the source, on the drain and the source (first embodiment). Example) Bits formed in the first insulating film, the first contact hole and the second contact hole respectively having the first contact hole and the second contact hole on the pad polysilicon (second embodiment) respectively on the drain and the source A line and a conductive layer, an oxide film formed on the bit line, a spacer formed to surround sidewalls of the oxide film and the bit line, a capacitor formed on a portion of the first insulating film around the conductive layer and on the periphery, and formed on the semiconductor substrate. A second insulating film, a metal contact hole continuously formed in the first and second insulating films of the peripheral circuit portion, and a metal wiring layer formed by filling the metal contact hole.

According to the present invention, since the first contact hole and the second contact hole are simultaneously formed in the first insulating film, process shortening and process cost are reduced. In addition, the formation of voids in the metal A1 filling the metal contact holes is prevented by reducing the thickness of the insulating film.

Description

Semiconductor memory device and manufacturing method thereof

1A to 1D are diagrams illustrating step-by-step views of a semiconductor memory device and a method of manufacturing the same according to the related art.

2 is a plan view illustrating a first contact hole, a second contact hole, a capacitor, and an active region of the present invention.

3A through 3E are diagrams illustrating, in steps, a semiconductor memory device and a method of manufacturing the same according to the first embodiment of the present invention.

4A through 4D are diagrams illustrating, in steps, a semiconductor memory device and a method of manufacturing the same according to the second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1,50,90: semiconductor substrate 15,64,102: first insulating film

19,70a, 108a: bit line 17,66,104: first contact hole

23,68,106: Second contact hole 33: void

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device capable of reducing a manufacturing process and a method of manufacturing the same.

The degree of integration of the elements constituting the semiconductor device is increasing at a very high speed. Accordingly, the size of the elements in the semiconductor device is getting smaller and smaller. In order to form certain elements constituting the semiconductor memory device (for example, transistors or capacitors of a memory cell), a process of depositing an oxide film, an insulating film or a metal layer on a semiconductor substrate, and a mask forming process for etching these films or layers is necessary. It must go through a complicated process of steps. Increasing the degree of integration, however, means that more stringent design rules should be applied in the process of forming such devices. Therefore, each time one step of the process is added to complete a device, the complexity increases, and the manufacturing process cost increases. Therefore, it is necessary to reduce the manufacturing process steps.

Current memory manufacturing methods include forming a transistor on a substrate, forming an insulating film thereon, forming a capacitor on the insulating film, and then forming a metal wiring with the peripheral circuit. At this time, the insulating film is formed from several layers from the beginning to the completion of the process, mainly when forming a bit line, a capacitor and a metal wiring (Symposium On VLSI Technology, 1994. pp149-150). Such insulating films are formed of a thin film but must have a certain thickness in order to maintain insulation. Due to the thickness of the insulating film thus formed, voids may sometimes be formed in the conductive layer filling the holes formed in the insulating film.

A method of manufacturing a semiconductor memory device using a conventional technique will be described in detail with reference to the accompanying drawings.

1A to 1D are diagrams illustrating step-by-step views of a semiconductor memory device and a method of manufacturing the same according to the related art.

FIG. 1A illustrates a step of forming a transistor and then defining a bit line contact hole forming region thereon. Specifically, after the field oxide film 3 is formed on the semiconductor substrate 1, the gate oxide film 5, the gate electrode 7, and the gate protection film 13 are formed. Next, conductive impurities opposite to the substrate are ion-implanted on the entire surface of the semiconductor substrate to form regions of the drain 9 and the source 11. The first insulating layer 15 is deposited on the entire surface of the semiconductor substrate including the resultant, and then patterned by applying the first photoresist layer PR1 on the first insulating layer 15. The first insulating layer 15 is dry etched using the patterned first photoresist layer as an etching mask.

1B illustrates forming a bit line and a second insulating layer. Specifically, the dry etching proceeds along the dotted line shown in FIG. 1A and eventually forms a direct contact hole (hereinafter referred to as a first contact hole) 17 on the drain region 9. Next, the first photoresist film PR1 is removed. Subsequently, a doped polysilicon layer filling the first contact hole 17 is deposited on the entire surface of the semiconductor substrate 1 having the resultant, and then patterned to form a bit line 19. After the second insulating film 21 is deposited on the first insulating film 15 on which the bit line 19 is formed, the second photoresist film PR2 is coated again. The second photoresist film PR2 is patterned such that a portion corresponding to the source region 11 of the second insulating film 21 is exposed.

FIG. 1C shows a step of forming a capacitor and a third insulating film. Specifically, when the entire surface of the resultant product of FIG. 1b is dry-etched using the patterned second photoresist film PR2 as an etching mask, the second and first insulating films are sequentially etched to bury the buried contact on the source region 11. A hole (hereinafter referred to as a second contact hole) 23 is formed. Subsequently, after the patterned second photoresist film PR2 is removed, a capacitor 25 in contact with the semiconductor substrate 1 is formed on the second insulating film 21. Next, a third insulating film 27 is deposited on the entire surface of the resultant material, and then a third photoresist film PR3 is coated on the third insulating film 27. The third photoresist film PR3 is patterned to form a photomask. After the entire surface of the substrate 1 is dry-etched using this photomask, the third photoresist film PR3 is removed. The third insulating film 27 is formed of a BPSG film.

FIG. 1D illustrates a step of forming a metallization layer between the peripheral circuit and the substrate. Specifically, the third, second and first insulating layers 27 and 21 15 are sequentially etched by the dry etching, and as a result, metal contact holes 29 are formed on the semiconductor substrate 1. do. A metal (eg, A1) is embedded in the metal contact hole 29 to form an electrical connection between the substrate and the peripheral circuit part to complete a memory manufacturing process. At this time, a void 33 is formed in the embedded metal due to the depth of the metal contact hole.

A semiconductor memory device using the related art and a method of manufacturing the same respectively form a first contact hole on a drain region for forming a bit line or a second contact hole on a source region for capacitor formation. Therefore, a separate insulating film must be formed to form each hole. Therefore, as the first contact hole and the second contact hole are separately formed, the complexity and the unit cost of the manufacturing process are increased. In general, the first, second and third insulating films of the prior art are formed using Borophospho silica glass (hereinafter referred to as BPSG).

Typically, in the memory manufacturing process, a second insulating layer is added to insulate the capacitor and the bit line. In this case, the BPSG used is usually reflowed at about 850 ° C., so a heat cycle is added to the punch-through of the transistor. Decreases the punch-through characteristics.

The addition of the second insulating film also deepens the depth of the metal contact hole formed from the peripheral ash. As a result, the metal (A1) layer filling this deep hole forms an overhang at the contact hole opening to form a void inside the metal. The formation of such voids also results in breakage of the metallization layer.

An object of the present invention is to reduce the thickness of the insulating film required to form the memory in order to solve the above-mentioned problems, shorten the process and lower the cost of the process, and also to fill the metal contact hole formed in the peripheral circuit SUMMARY To provide a semiconductor memory device having a first contact hole and a second contact hole simultaneously formed in a first insulating layer to prevent the formation of voids in a metal.

Another object of the present invention is to provide a method of manufacturing a semiconductor memory bonded to the above memory.

In order to achieve the above object, a semiconductor memory device according to a first embodiment of the present invention is provided.

A gate electrode formed on the semiconductor substrate;

A drain and source region formed adjacent to the gate electrode;

A first insulating film formed on an entire surface of the resultant product on which the gate electrode is formed;

First and second contact holes exposing the drain and source regions formed in the first insulating layer;

A bit line connected to the drain through the first contact hole formed on the first insulating layer;

An insulating cap layer formed on the bit line and an insulating spacer formed on the bit line side;

And a capacitor in contact with the source through the second contact hole formed on the first insulating layer.

The first and second insulating layers are plasma oxide films based not only on BPSG but also on undoped silica glass (hereinafter referred to as USP), high temperature oxide (hereinafter referred to as HTO) and silane (SiH ₄ ). (Hereinafter referred to as PE-SiH ₄ ) and a plasma oxide film (hereinafter referred to as PE-TEOS) based on TEOS (TEOS).

The semiconductor memory device includes a second insulating film formed on the semiconductor substrate, a metal contact hole formed on the first and second insulating films, a metal contact hole formed on the metal contact hole, and the second insulating film in addition to the resultant at a peripheral circuit portion thereof. It may be further provided. Also, as a result of the second embodiment of the present invention for achieving the above object, a semiconductor memory device having a pad polysilicon layer (100, 100a) is further provided on the drain and the source as shown in FIG. have.

In order to achieve the above object another semiconductor memory manufacturing method according to the present invention,

Forming a gate electrode on the semiconductor substrate;

Forming a drain and a source region in the semiconductor substrate adjacent to the gate electrode;

Forming a first insulating film on the entire surface of the semiconductor substrate;

Forming a first contact hole exposing the drain region and a second contact hole exposing the source region in the first insulating layer;

Forming a bit line connected to the drain region through the first contact hole and a first conductive layer connected to the source region through the second contact hole on the first insulating layer;

Forming an insulating cap layer on the bit line and forming a spacer on the bit line side;

And forming a capacitor on the first insulating layer adjacent to the bit line and connected to the first conductive layer.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor memory, the method including: forming doped pad polysilicon on the drain and source regions in the first embodiment;

And forming a first contact hole on the pad polysilicon layer of the drain region and a second contact hole on the pad polysilicon of the source region in the first insulating layer.

Forming a second insulating film on the entire surface of the semiconductor substrate in the peripheral circuit portion of the memory in addition to the result of each of the first and second embodiments;

Sequentially etching the second insulating film and the first insulating film to form a metal contact hole; And

The method may further include forming a metal wiring layer in the metal contact hole.

The active region on the semiconductor substrate is set in diagonal form. This widens the effective area of the capacitor.

The first and second insulating films may be formed using any one selected from the group consisting of USP, HTO, PE-SiH ₄ and PE-TEOS as well as BPSG. In addition, the bit line may be formed of only doped polysilicon, but may be formed of polyside by adding tungsten silicide.

In the memory manufacturing process, the first contact hole and the second contact hole are simultaneously formed in the same insulating layer. Therefore, it is possible to shorten the manufacturing process, lower the process cost, and prevent the formation of voids in the metal filling the contact holes when forming the metal contact between the peripheral circuit and the substrate.

Hereinafter, embodiments of the present invention will be described in detail with the accompanying drawings.

2 is a plan view illustrating a first contact hole, a second contact hole, a capacitor, and an active region of the present invention. Where 2a represents an active region and 2b represents a capacitor. 2c represents a first contact hole and 2d represents a second contact hole. In addition, G.L represents a gate line and B.L represents a bit line. The active region 2a is formed diagonally.

3A through 3E are diagrams illustrating, in steps, a semiconductor memory device and a method of manufacturing the same according to the first embodiment of the present invention.

3A shows a step of forming a first insulating film. Specifically, active and inactive regions are formed on the semiconductor substrate 50. The field oxide film 52 is formed in the inactive region. An active region is formed between the field oxide films 52. As shown in FIG. 2, the active region 2a may be formed diagonally. Forming the active region in this way can increase the effective area of the capacitor formed later. Following the formation of the field oxide film 52, a gate oxide film 54 is deposited on the active region. The polyside gate electrode 56 is formed on this gate oxide film 52. The polyside gate electrode 56 is formed of doped polycrystalline silicon and silicide formed thereon. The doped polysilicon of the gate electrode 56 is used as a mask when forming the drain region 58 and the source region 60 on the active region on the semiconductor substrate 50. Subsequently, a gate insulating layer 62 is formed on the polyside gate electrode 56. Subsequently, a first insulating layer 64 is formed on the entire surface of the semiconductor substrate 50 including the resultant. The fourth photoresist film PR4 is coated on the first insulating film 64. The fourth photoresist film PR4 is patterned to expose the surface of the first insulating film 64 corresponding to the source and drain regions 58 and 60. When the entire surface of the semiconductor substrate 50 is dry etched, the exposed portion of the first insulating layer 64 is etched along the dotted line.

The first insulating layer 64 is preferably formed using any one selected from the group consisting of BPSG, HTO, USG, PE-SiH ₄ and PE-TEOS.

3B illustrates forming first and second contact holes and a bit line oxide film. Specifically, the first contact hole 66 is formed on the drain region 58 and the second contact hole 68 is formed on the source region 60 as a result of the entire etching of the resultant of FIG. 3A. After forming the first contact hole 66 and the second contact hole 68, the fourth photoresist film PR4 is removed. The doped polysilicon 70 is deposited on the entire surface of the resultant product. The bit line oxide layer 72 is deposited on the doped polycrystalline silicon 70 formed by filling the first contact hole 66 and the second contact hole 68. The fifth photoresist film PR5 is coated on the bit line oxide layer 72 and then patterned to form a photomask on a portion where the bit line is to be formed. Dry etching the entire surface of the resultant. In this case, the etching endpoint is taken as the interface of the first insulating layer 64. The doped polysilicon layer 70 deposited by filling the first contact hole 66 and the second contact hole 68 may be formed as a polyside structure by forming a tungsten silicide layer thereon.

3C shows a step of forming a bit line and an oxide film. Specifically, as a result of the front side etching of the resultant of FIG. 3B, the bit line 70a is formed and the oxide film 72a is formed thereon. Next, in order to prevent the bit line 72a from being electrically connected to the capacitor, an oxide film must be formed on the sidewall of the bit line 70. To this end, the oxide film 74 is uniformly deposited on the entire surface of the semiconductor substrate. At this time, the oxide film 74 is deposited using HTO or TEOS. In order to leave the oxide film 74 symmetrically on the sidewall of the bit line 70a, it is necessary to uniformly anisotropically etch the entire surface of the oxide film 74. To this end, reactive ion etching (hereinafter referred to as RIE) is performed on the entire surface of the semiconductor substrate 50 on which the oxide film 74 is deposited. Only the portion shown by the dotted line by the RIE leaves the oxide film, which becomes the bit line oxide spacer 74a. The oxide film spacer 74a is formed to surround the entire sidewall of the bit line 70a.

FIG. 3d illustrates a step of forming a capacitor and a second insulating film. Specifically, the capacitor 76 is formed on the entire surface of the conductive layer 70b in which the second contact hole 68 is embedded and on the portion of the first insulating layer 64 around the capacitor layer in a conventional manner. Subsequently, a second insulating film 78 is deposited on the entire surface of the resultant material, and then a sixth photoresist film PR6 is applied and patterned thereon.

3E illustrates a step of forming a metal contact layer between the peripheral circuit portion and the substrate. In detail, the metal contact hole 80 is formed by sequentially etching the second insulating layer 78 and the first insulating layer 64 using the patterned sixth photoresist layer PR6 as an etching mask. Subsequently, after the sixth photoresist film PR6 is removed, a metal (eg, A1) is deposited on the entire surface of the resultant, and then patterned to form a metal wiring layer 82 in the metal contact hole 80. The subsequent process proceeds to a conventional process to complete the memory manufacturing.

4 through 4D are diagrams illustrating the semiconductor memory device and the method of manufacturing the same according to the second embodiment of the present invention.

4A illustrates forming a pad polysilicon layer. Specifically, the steps of forming the gate electrode 94 and the drain and source regions 96 and 98 on the semiconductor substrate 90 are performed in the same manner as in the first embodiment. Subsequently, the doped polysilicon layer is deposited on the semiconductor substrate 90, and then patterned to form pad polysilicon layers 100 and 100a on the drain region 96 and the source region 98.

4B illustrates a step of defining the contact hole forming region. Specifically, the first insulating film 102 is deposited on the entire surface of the resultant product of FIG. 4A. Subsequently, a seventh photoresist film PR7 is applied and patterned on the first insulating film 102. The first insulating layer 102 is anisotropically etched using the patterned seventh photoresist layer PR7 as an etching mask. As a result of anisotropic etching, first and second contact holes 104 and 106 are formed on the pad polysilicon layers 100 and 100a. Subsequently, the seventh photoresist film PR7 is removed.

4C illustrates filling the first contact hole and the second contact hole with a conductive material. Specifically, a doped polysilicon layer 108 is deposited on the resultant. At this time, the doped polysilicon is filled in the first and second contact holes 104 and 106 formed in FIG. 4b. Subsequently, an oxide film 110 is deposited on the doped polysilicon, an eighth photoresist film PR8 is applied thereon, and then patterned. The eighth photoresist film PR8 is patterned to include the first contact hole 104. The oxide film 110 and the doped polysilicon layer 108 are sequentially etched using the patterned eighth photoresist film PR8 as an etching mask. At this time, the end point is taken as the interface of the first insulating film (102). After the etching is finished, the patterned eighth photoresist layer PR8 is removed. As a result of the etching, the bit line 108a, the bit line oxide layer 110, and the conductive layer 108b of FIG. 4d are formed. The formation of the oxide spacer 111, the capacitor 112, the metal contact hole 116 and the metal wiring layer 118 and subsequent processes shown in FIG. 4D are the same as those in the first embodiment.

As described above, the present invention forms the first and second contact holes in the same insulating film in one photo process. Therefore, the separate insulating film deposition process used to form the conventional second contact hole may be omitted. This results in a shortening of the memory manufacturing process and also facilitates the memory manufacturing process and increases the manufacturing yield. In addition, when forming a metal contact with the semiconductor substrate in the peripheral circuit, there is an advantage of preventing the formation of voids in the metal A1 filling the contact holes by making the depth of the contact holes shallow.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit of the present invention.

Claims (6)

A gate electrode formed on the semiconductor substrate; A drain and source region formed adjacent to the gate electrode; A first insulating film formed on an entire surface of the resultant product on which the gate electrode is formed; First and second contact holes exposing the drain and source regions formed in the first insulating layer; A bit line connected to the drain through the first contact hole formed on the first insulating layer; An insulating cap layer formed on the bit line and an insulating spacer formed on the bit line side; And a capacitor connected to the source through the second contact hole formed on the first insulating layer. The metal layer of claim 1, wherein the second insulating layer formed on the first insulating layer, the metal contact holes formed in the first and second insulating layers, and the metal formed on the second insulating layer contacted with the semiconductor substrate through the metal contact hole. A semiconductor memory device, further comprising a wiring layer. The semiconductor memory device of claim 1, wherein the active region is formed diagonally. 2. The semiconductor memory device according to claim 1, wherein a pad polysilicon layer is formed on said drain and source regions. Forming a gate electrode on the semiconductor substrate; Forming a drain and a source region in the semiconductor substrate adjacent to the gate electrode; Forming a first insulating film on the entire surface of the semiconductor substrate; Forming a first contact hole exposing the drain region and a second contact hole exposing the source region in the first insulating layer; Forming a bit line connected to the drain region through the first contact hole and a first conductive layer connected to the source region through the second contact hole on the first insulating layer; Forming an insulating cap layer on the bit line and forming a spacer on the bit line side; And forming a capacitor on the first insulating layer adjacent to the bit line and connected to the first conductive layer. The method of claim 5, further comprising forming a pad conductive layer on the drain and source regions.