KR930010082B1 - Making method of contact hole - Google Patents
Making method of contact hole Download PDFInfo
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- KR930010082B1 KR930010082B1 KR1019910015312A KR910015312A KR930010082B1 KR 930010082 B1 KR930010082 B1 KR 930010082B1 KR 1019910015312 A KR1019910015312 A KR 1019910015312A KR 910015312 A KR910015312 A KR 910015312A KR 930010082 B1 KR930010082 B1 KR 930010082B1
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- oxide layer
- silicon oxide
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- bit line
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- 238000000034 method Methods 0.000 title claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 17
- 238000004140 cleaning Methods 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000003860 storage Methods 0.000 claims description 6
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 abstract 2
- 235000011114 ammonium hydroxide Nutrition 0.000 abstract 2
- 238000002407 reforming Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- HXYCHJFUBNTKQR-RNFRBKRXSA-N (2R,3R)-heptane-1,2,3-triol Chemical compound CCCC[C@@H](O)[C@H](O)CO HXYCHJFUBNTKQR-RNFRBKRXSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- VZSXFJPZOCRDPW-UHFFFAOYSA-N carbanide;trioxorhenium Chemical compound [CH3-].O=[Re](=O)=O VZSXFJPZOCRDPW-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 150000002923 oximes Chemical class 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- -1 silicon oxime Chemical class 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제 1 도 내지 제 9 도는 본 발명의 콘택제조방법을 적용하여 DRAM셀을 제조하는 단계를 도시한 단면도.1 to 9 are cross-sectional views showing steps of manufacturing a DRAM cell by applying the contact manufacturing method of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2A 및 2B : 소오스 및 드레인1: substrate 2A and 2B: source and drain
3 : 소자분리산화막 4 : 게이트 산화막3: device isolation oxide film 4: gate oxide film
7 : 스페이서 옥사이드층 8 : 하부실리콘 옥사이드층7: spacer oxide layer 8: lower silicon oxide layer
9 : BPSG층 10 : 상부실리콘 옥사이드층9: BPSG layer 10: upper silicon oxide layer
11 : 비트라인 12 : 비트라인 마스크 옥사이드층11 bit line 12 bit line mask oxide layer
13 : 비트라인 스페이서 옥사이드 14 : 캐핑 옥사이드13 bit line spacer oxide 14 capping oxide
15 : 전하저장전극용 도전층15: conductive layer for charge storage electrode
본 발명은 반도체 제조공정의 고집적 소자용 콘택 제조방법에 관한 것으로, 특히 64M DRAM급 이상 뿐만아니라 SRAM등의 ULSI에 사용할 수 있는 고집적 소자용 콘택제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated device contact in a semiconductor manufacturing process, and more particularly to a method for manufacturing a contact for a highly integrated device that can be used for ULSI such as SRAM as well as 64M DRAM or more.
디바이스의 집적도가 높아질수록 셀면적이 감소하게 되며 64M DRAM 이상의 고집적 디바이스에서는 기존의 방식과는 아주 다른 새로운 셀구조가 요구된다. 셀면적을 축소시키기 위해서는 디자인 룰 감소에 따라 워드라인과 비트라인의 라인과 스페이스 및 캐패시터 면적이 감소되고, 콘택사이즈를 작게할 수 밖에 없다.The higher the device density, the smaller the cell area. Highly integrated devices of more than 64M DRAM require a new cell structure that is very different from the traditional method. In order to reduce the cell area, the line, space and capacitor area of word lines and bit lines are reduced and contact size is reduced as the design rule decreases.
또한, 집적도가 높아질수록 문제가 되는 것은 기존의 다이렉트 콘택방법으로는 64M DRAM급 이상에서는 워드라인과 워드라인, 비트라인과 비트라인 사이의 간격이 너무 작어 사용하기 힘들다. 그래서 대부분의 회사에서는 자기 정렬콘택 방법을 사용하고 있으나 콘택식각때 에스펙트비(Aspect Ratio)가 아주 커서 식각공정의 어려움, 단차에 의한 배선라인의 단선 또는 저항증가 등의 문제점 때문에 실제 공정 마진이 매우 적다.In addition, the higher the degree of integration, the more problematic is the conventional direct contact method is difficult to use because the distance between the word line and word line, bit line and bit line is too small in 64M DRAM or more. Therefore, most companies use self-aligned contact method, but the aspect ratio during contact etching is very large, so the actual process margin is very high due to the difficulty of etching process, disconnection of wiring line due to step or increase of resistance. little.
따라서, 본 발명의 목적은 상부의 도전층을 하부의 도전층에 콘택하기 위하여 콘택홈을 형성할때 에스펙트비가 아주커서 식각공정의 어려움, 단차에 의한 배선라인의 단선 또는 저항증가등이 발생되는 문제점을 해결하기 위하여 콘택이 될부분의 요홈에 예정된 두께의 BPSG층을 채워서 콘택이외의 부분에 비트라인이 통과할때 비트라인 하부의 단차가 줄어들게되어 불필요한 비트라인을 식각할때 비트라인 식각공정이 쉽고 또한 비트라인 콘택부분이 아닌 곳의 액티브 영역이 식각영향을 받지 않아 비트라인의 단성방지 및 저항을 감소시킬 수 있는 고집적 소자용 콘택제조방법을 제공하는데 있다.Accordingly, an object of the present invention is that when the contact groove is formed in order to contact the upper conductive layer to the lower conductive layer, the aspect ratio is very large, so that the difficulty of the etching process, disconnection of the wiring line due to the step, or increase in resistance are generated. In order to solve the problem, by filling the BPSG layer of predetermined thickness in the groove of the part to be contacted, when the bit line passes through the non-contact part, the step below the bit line is reduced. The present invention provides a method for manufacturing a contact for a highly integrated device that can easily reduce the resistance and resist the bit line since the active region of the non-bit line contact portion is not etched.
본 발명에 의하면 DRAM셀의 비트라인을 드레인에 콘택할때 에스펙트비(Aspect Ratio)가 아주커서 식각공정의 어려움, 단차에 의한 비트라인 단선 또는 저항이 증가되는 문제점을 해결하기 위하여, 스페이서 옥사이드 및 마스크 옥사이층이 형성된 게이트전극과 노출된 드레인 및 소오스 상부에 하부 실리콘 옥사이드층을 예정된 두께로 형성하는 단계와, 하부 옥사이드층 상부에 게이트전극 상부의 하부옥사이드층 보다도 두꺼운 두께로 BPSG층이 평탄하게 되도록 형성하는 단계와, 상기 BPSG층을 NH4OH 크리닝으로 상기 게이트전극 상부의 하부옥사이드층 보다 낮은 두께까지 에치백하는 단계와, 전체구조 상부에 상부 실리콘 옥사이드층을 예정된 두께로 형성한 다음, 비트라인용 콘택마스크를 이용하여 콘택영역의 상부실리콘 옥사이드층을 제거하는 단계와, 남아있는 상부 실리콘 옥사이드층을 마스크로하여 콘택영역 요부의 G층을 NH4OH 크리닝으로 제거한 다음, 블란켓트 식각으로 콘택영역의 저부에 하부실리콘 옥사이드층을 식각하여 드레인을 노출시키는 동시에 콘택영역이 아닌곳의 상부 실리콘 옥사이드층을 식각하는 단계와, 비트라인 도전층을 전체구조 상부에 증착하고 마스크 패턴 공정으로 드레인에 접속된 비트라인을 패턴하는 단계로 이루어진 것을 특징으로 한다.According to the present invention, in order to solve the problem that the aspect ratio is large when the bit line of the DRAM cell is contacted with the drain, the difficulty of the etching process, the bit line disconnection due to the step difference, or the resistance is increased. Forming a lower thickness of the silicon oxide layer on the gate electrode and the exposed drain and the source having the mask oxime layer to a predetermined thickness, and planarizing the BPSG layer on the lower oxide layer to a thickness thicker than the lower oxide layer on the gate electrode. Forming the BPSG layer by NH 4 OH cleaning to a lower thickness than the lower oxide layer on the gate electrode, and forming an upper silicon oxide layer on the entire structure to a predetermined thickness, and then forming a bit line. Removing the upper silicon oxide layer of the contact region using a contact mask for , The upper silicon oxide layer remaining at the same time the contact area for removing the G layer of the contact region recessed by a mask with NH 4 OH-cleaning, and then by etching the lower silicon oxide layer at the bottom of the contact region in Blanca ketteu etching to expose the drain Etching the upper silicon oxide layer, and depositing the bit line conductive layer on the entire structure and patterning the bit line connected to the drain by a mask pattern process.
이하 첨부된 도면을 참조하여 본 발명을 상세히 설명하고자 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제 1 도 내지 제 10 도는 본 발명의 콘택제조방법을 제 1 실시예에 의해 DRAM셀의 전하저장전극콘택 및 비트라인 콘택에 적용한 도면이다.1 to 10 are diagrams showing the method of manufacturing a contact of the present invention applied to a charge storage electrode contact and a bit line contact of a DRAM cell according to the first embodiment.
제 1 도는 공지의 기술로 기판(1)상부에 소자분리 산화막(3), 게이트 산화막(4), 게이트전극(5), 마스크옥사이드층(6), 스페이서 옥사이드(7), 소오스 및 드레인(2A 및 2B)을 각각 형성한 상태의 단면도이다.1 shows a device isolation oxide film 3, a gate oxide film 4, a gate electrode 5, a mask oxide layer 6, a spacer oxide 7, a source and a drain 2A on a substrate 1 by a known technique. And 2B) are sectional views, respectively.
제 2 도는 노출된 구조상부에 하부실리콘 옥사이드층(8)(예를들어 HTO, MTO, TEOS, Nitride)을 예정된 두께로 형성하고, 그 상부에 BPSG(Boro-phospho silicate Glass)층 (9)을 하부실리콘 옥사이드층(8) 상부면보다 높은 두께로 평탄하게 플로우(Flow)시켜 평탄하게 형성한 상태의 단면도이다.2 shows a lower silicon oxide layer 8 (e.g., HTO, MTO, TEOS, Nitride) having a predetermined thickness on the exposed structure, and a Boro-phospho silicate glass (BPSG) layer 9 thereon. A cross-sectional view of the lower silicon oxide layer 8 having a thickness higher than that of the upper surface of the lower silicon oxide layer 8 to form a flat surface.
제 3 도는 본 발명의 주요부분을 도시하는 것으로 하부 실리콘 옥사이층(8)과 BPSG층(9) 사이의 식각선택비(Etch Selectivity)가 1 : 50 이상인 것을 이용하여 NH4OH 크리닝으로 마스크 옥사이드층(6) 상부의 하부실리콘 옥사이드층(8) 상부면 보다 아래까지 BPSG층(9)을 제거하여 콘택영역의 요홈에 예정된 두께로 BPSG층(9)을 남겨두고 전체구조 상부에 상부 실리콘 옥사이드층(10)을 예정된 두께로 형성한 상태의 단면도이다.FIG. 3 shows the main part of the present invention, wherein the mask oxide layer is subjected to NH 4 OH cleaning using an etching selectivity between the lower silicon oxime layer 8 and the BPSG layer 9 of 1:50 or more. (6) Removing the BPSG layer 9 below the upper surface of the upper silicon oxide layer 8, leaving the BPSG layer 9 to a predetermined thickness in the groove of the contact area, and the upper silicon oxide layer on the entire structure ( 10 is a cross-sectional view of a state formed in a predetermined thickness.
제 4 도는 비트라인을 하부의 드레인(2B)에 콘택하기 위해, 전체구조 상부에 포토레지스트층(20)을 도포하고, 비트라인용 콘택마스크를 사용하여 드레인(2B)상부의 포토레지스트층(20)을 제거하고, 노출된 상부 실리콘 옥사이드층(10)을 제거한 상태의 단면도이다.4, a photoresist layer 20 is applied over the entire structure in order to contact the bit line to the drain 2B at the bottom, and the photoresist layer 20 on the drain 2B is formed using a contact mask for the bit line. ), And the exposed upper silicon oxide layer 10 is removed.
제 5 도는 상기의 포토레지스트층(20)을 제거하고, 남아있는 상부 실리콘 옥사이드층(10)을 마스크층으로 이용하여 NH4OH 크리닝 상, 하부 실리콘 옥사이드층(8 및 10)과 BPSG(9) 사이의 식각선택비가 높은점을 이용하여 콘택영역의 요홈에 채워진 BPSG층(9)만 제거하고, 블란켓트(Blanket) 식각으로 콘택영역의 요홈에 있는 하부 실리콘 옥사이드층(8)과 콘택영역이 아닌 곳의 상부 실리콘 옥사이드층(10)을 식각하여 콘택영역의 드레인(2B)을 노출시킨 상태의 단면도이다. 이때 스페이서 옥사이드(7) 측벽에 약간의 하부 실리콘 옥사이드층(8)이 남아있게 된다.5, the photoresist layer 20 is removed, and the remaining upper silicon oxide layer 10 is used as a mask layer. The NH 4 OH cleaning phase, the lower silicon oxide layers 8 and 10 and the BPSG 9 are removed. Only the BPSG layer 9 filled in the grooves of the contact region is removed by using a high etching selectivity between them, and the lower silicon oxide layer 8 in the grooves of the contact region and the non-contact region are removed by the blanket etching. The upper silicon oxide layer 10 is etched to expose the drain 2B of the contact region. At this time, some lower silicon oxide layer 8 remains on the sidewall of the spacer oxide 7.
제 6 도는 제 5 도 공정후 전체구조 상부에 비트라인용 도전층(11)을 예정된 두께로 증착하여 드레인(2B)에 접속한다음, 비트라인용 도전층(11)상부에 비트라인 마스크 옥사이드층(12)를 형성하고, 그 상부에 포토레지스트층(21)을 도포한후, 비트라인용 마스크를 이용하여 예정된 부분의 포토레지스트층(21)을 제거한 상태의 단면도이다. 여기서 주지할 점은 비트라인 도전층(11)이 드레인(2B) 상부에서도 평탄하게 형성됨으로 비트라인 패턴 형성시에 오버식각을 적게해도 되며 또한 비트라인의 단락방지 및 저항을 감소할 수 있다.FIG. 6 is a bit line conductive layer 11 deposited on the entire structure after the process of FIG. 5 to a predetermined thickness and connected to the drain 2B, and then the bit line mask oxide layer is formed on the bit line conductive layer 11. (12) is formed, the photoresist layer 21 is applied on the upper side, and the photoresist layer 21 of the predetermined part was removed using the mask for a bit line. It should be noted that since the bit line conductive layer 11 is formed even on the drain 2B, the over etching may be reduced when forming the bit line pattern, and the short line prevention and resistance of the bit line may be reduced.
제 7 도는 노출된 비트라인 마스크 옥사이드층(12)을 제거하고 또한, 하부의 노출된 비트라인 도전층(11)을 제거하여 비트라인(11A) 패턴을 형성하고, 전체적으로 옥사이드층을 예정된 두께로 형성하고 식각공정에 의해 비트라인(11A) 측벽에 비트라인 스페이서 옥사이드층(13)을 형성한 단면도이다.Figure 7 removes the exposed bit line mask oxide layer 12, and also removes the underlying exposed bit line conductive layer 11 to form a bit line 11A pattern, the overall oxide layer to a predetermined thickness And a bit line spacer oxide layer 13 on the sidewalls of the bit lines 11A by the etching process.
제 8 도는 캐패시터의 전하저장전극을 소오스(2A)에 콘택하기 위하여 행하는 공정으로, 제 7 도 공정후 전체구조 상부면에 캐핑(Capping) 옥사이드층(14)을 예정된 두께로 형성하고, 그상부에 포토레지스트층(22)을 도포하고, 전하저장전극 콘택용 마스크를 이용하여 소오스(2A)상부의 예정된 포토레지스트층(22)을 제거한 다음, 노출된 캐핑 옥사이드층(14)을 제거한 상태의 단면도이다.FIG. 8 is a step of contacting the charge storage electrode of the capacitor to the source 2A. After the FIG. 7 process, a capping oxide layer 14 is formed on the upper surface of the entire structure to a predetermined thickness. A cross-sectional view of the state in which the photoresist layer 22 is applied, the predetermined photoresist layer 22 on the source 2A is removed using a mask for charge storage electrode contact, and then the exposed capping oxide layer 14 is removed. .
제 9 도는 상기의 포토레지스트층(22)을 제거하고 남아있는 캐핑 옥사이드층(14)을 마스크층으로 이용하고, NH4OH 크리닝에서 캐핑옥사이드층(14)가 BPSG층(9) 사이의 높은 식각선택비를 이용하여 콘택영역의 요홈에 채워진 BPSG층(9)만 제거하고, 블란켓트 식각으로 콘택영역의 요홈에 있는 하부 실리콘 옥사이드층(8)과 비트라인 마스크 옥사이드층(12) 상부에 있는 캐핑 옥사이드층(14)을 식각하여 소오스(2A)를 노출시킨다음, 전하저장 전극용 도전층(15)을 증착한 상태의 단면도이다. 여기서 주지해야 할점은 상기 비트라인용 마스크 옥사이드층(12) 상부에 있는 캐핑 옥사이드층(14)이 식각될때 요홈부분에 조금남아 있을수가 있다는 것이다.9 shows that the photoresist layer 22 is removed and the remaining capping oxide layer 14 is used as a mask layer, and the capping oxide layer 14 is highly etched between the BPSG layers 9 in NH 4 OH cleaning. By using the selectivity, only the BPSG layer 9 filled in the grooves of the contact region is removed, and the capping on the lower silicon oxide layer 8 and the bit line mask oxide layer 12 in the grooves of the contact region is performed by blanket etching. After the oxide layer 14 is etched to expose the source 2A, a cross-sectional view of the conductive layer 15 for charge storage electrodes is deposited. It should be noted that when the capping oxide layer 14 on the bit oxide mask oxide layer 12 is etched, it may be slightly left in the recess.
상기한 바와같이 고집적도를 갖는 소자에서 자기정렬콘택을 이용하여 상부의 도전층을 하부의 도전층에 콘택하는데 특히, 워드라인과 워드라인사이에 비트라인 콘택을 하는 경우 비트라인 콘택식각시 워드라인 측면의 절연층이 손상을 받기 쉬워 비트라인과 워드라인과 단락이 발생되는 문제점과, 비트라인이 큰단차로 인해 단선되거나 비트라인의 저항이 증가되는 문제점과 비트라인 패턴형성히 과도한 오버식각에 의해 다른영역이 손상받는 문제점을 본 발명에 의하면 해결할 수 있으므로 반도체 소자의 수율과 신뢰성을 향상시킬 수 있다.As described above, the upper conductive layer is contacted to the lower conductive layer by using a self-aligned contact in the device having a high degree of integration. In particular, when the bit line contact is made between the word line and the word line, the word line is used during the etching of the bit line contact. The insulation layer on the side is susceptible to damage, causing short-circuits between bit lines, word lines, and short lines, short-circuits due to large steps, or increased resistance of bit lines, and excessive over-etching. According to the present invention, the problem of damaging other regions can be solved, and thus the yield and reliability of the semiconductor device can be improved.
Claims (2)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910015312A KR930010082B1 (en) | 1991-09-03 | 1991-09-03 | Making method of contact hole |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910015312A KR930010082B1 (en) | 1991-09-03 | 1991-09-03 | Making method of contact hole |
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| Publication Number | Publication Date |
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| KR930006899A KR930006899A (en) | 1993-04-22 |
| KR930010082B1 true KR930010082B1 (en) | 1993-10-14 |
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| KR (1) | KR930010082B1 (en) |
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