KR950012033B1 - Method of manufacturing a contact for vlsi device - Google Patents

Abstract

forming a MOS transistor having a gate, source and drain electrodes and a field oxide on a silicon substrate; forming a first insulating layer on the MOS transistor and the field oxide; forming a polyimide pattern only on contact areas located on top of the source electrode and drain electrode after coating a photosensitive polyimide over the first insulating layer; forming a second insulating layer over the device, particularly on the polyimide pattern and forming a second insulating layer pattern by performing an etch back process until a surface of the polyimide pattern is exposed; removing a spacer on side walls of the gate electrode by performing a blanket etching process on the first insulating layer exposed by the plasma etching process; depositing a polysilicon layer on the second insulating layer pattern and forming several polysilicon pads in contact with the drain electrode or the source electrode by etching back process carrying until a surface of the second insulating layer pattern is exposed; depositing a third insulating layer over the device; and exposing each of the several polysilicon pads by removing a portion of the third insulating layer and depositing a conducting layer in contact with the exposed polysilicon pad.

Description

Contact Manufacturing Method for Highly Integrated Devices

1 is a layout diagram of a DRAM cell for applying the present invention.

2A to 2H are cross-sectional views of the contact preparation method of the present invention by cutting the line A-A of FIG.

3A to 3E are cross-sectional views of the contact preparation method of the present invention by cutting the line B-B in FIG.

4A to 4D are cross-sectional views of the contact manufacturing method of the present invention by cutting the C-C line of FIG.

* Explanation of symbols for main parts of the drawings

1: semiconductor substrate, 2A 2B: source and drain

3: field oxide film 4: gate oxide film

5: gate electrode 6: mast oxide

7: oxide spacer 8: first insulating layer

9: BPSG layer 10: Second insulating layer

10A: second insulating layer pattern 11: third insulating layer

11 A third insulating layer spacer 12 polysilicon layer 12 A

12B: contact pad 13: conductive layer for bit line

13A: Bitline 14A: Mask Oxide Layer Pattern

15A: Photosensitive film pattern 16: Fourth insulating layer

16A: fourth insulating layer spacer 17: conductive layer for charge storage electrode

20: contact hole 50: bit line

60: word line 70: bit line contact

80: charge storage electrode contact 90: active region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a contact of a highly integrated device in a semiconductor manufacturing process, and more particularly to a method for forming a contact for a highly integrated device that can be used for not only highly integrated DRAM but also SRAM.

As the device density increases, the cell area decreases, and in order to reduce the cell area, the design rule decreases, and thus, lines and spaces of word lines and bit lines must be reduced. As the line and space are reduced, it is not easy to form bit line contacts and charge storage electrode contacts using the conventional direct contact method in the 64M DRAM class of 0.4 µm or less. Therefore, most companies use self-aligned contact method, but the aspect ratio during contact etching is so large that problems such as decrease in etching selectivity, short circuit of wiring line due to step and increase of resistance As a result, the actual process margin is very small.

In order to solve the problems caused by the step, the present invention minimizes the step difference between the bit line and the charge storage electrode by filling the BPSG layer in the request between the word line and the word line. Contact is formed by NH ₄ OH cleaning or HF DIP (or BCE DIP, HF VAPOR) to solve the problem that word line and bit line are attacked due to deterioration of misalignment and etching selectivity. TEOS [HTO, MTO, LTO, nitride, eg, BPSG layer and a large etching selectivity to remove the BPSG layer filled in the grooves to be filled; TBOS for NH ₄ OH cleaning: = 1: 10 to 100, large THO: BPSG = 1: 100 or more, Si ₃ N ₄ (silicon nitride): BPSG = 1: 100] or more during HF (or BOE DIP) dip process Alternatively, silicon nitride layers are used to protect word lines and bit lines. In addition, in order to solve the problem that the BPSG layer is etched in a direction parallel to the word line when removing the BPSG layer of the contact groove, an oxide layer or a nitride layer is deposited on the BPSG layer and then using an upper contact oxide layer using a contact mask. Alternatively, the nitride layer was etched to form an oxide pattern, and oxide spacers were formed on the sidewalls.

Another feature of the present invention is to open the bit line and the charge storage active contact at the same time to fill the polysilicon in the contact hole (Contact Hole) to form a bit line can reduce the resistance much. In addition, after forming a bit line and a pattern and forming an oxide, the oxide is etched by a blanket etching process without using a contact storage electrode for the charge storage electrode, and the overetch is performed until the contact pad of the contact hole for the charge storage electrode is exposed. The contact is opened.

In the method of manufacturing a bit line contact and a charge storage electrode contact of the present invention, forming a MOSFET comprising a gate electrode, a source, and a drain on a semiconductor substrate, and sequentially forming a first insulating layer and a BPSG layer on the entire structure including the MOSFET. And forming the BPSG layer by etching the BPSG layer so that the upper surface of the first insulating layer is sufficiently exposed by an etchback process, thereby leaving the BPSG layer in the groove. And forming a second insulating layer on the entire structure, forming a second insulating layer pattern by the second insulating layer etching process using a contact mask, and forming a third insulating layer on the entire structure including the second insulating layer pattern. An insulating layer is formed, and the third insulating layer is etched until the BPSG remaining in the recess is sufficiently exposed by a blanket etching process, so that the third insulating layer is disposed on the sidewalls of the second insulating layer pattern. Forming a contact hole, removing the BPSG layer remaining in the recess, etching the exposed first insulating layer by a blank cut etching process to form a contact hole, and forming a contact pad in the contact hole. And sequentially stacking bit lines and mask oxide layers on the entire structure including the contact pads, and forming bit line and mask oxide layer patterns by an etching process using a bit line mask, wherein the mask oxide layer patterns are on top A fourth insulating layer is formed on the entire structure including the bit lines formed on the substrate, and the fourth insulating layer is etched by a blanket etching process to form a fourth insulating layer spacer on the sidewalls of the bit lines. The conductive layer for the storage electrode is deposited and connected to the contact pad for the charge storage electrode, and then the charge storage electrode is formed by a mask pattern process. It is characterized by comprising the steps:

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a layout diagram in which respective wirings of a DRAM cell of the present invention are arranged, and include a bit line 50, a word line 60, a bit line contact 70, a charge storage contact 80, and It is shown that the active regions 90 are each arranged.

2A to 2H are cross-sectional views showing the contact manufacturing method of the present invention by cutting along the line A-A of FIG.

2A illustrates a field oxide film 3, a gate oxide film 4, a gate electrode 5, a mask oxide layer 6, a spacer oxide 7, a source and a drain (i. It is sectional drawing of the state which formed 2A and 2B), respectively. One MOSFET is composed of the gate electrode 5, the source and the drain 2A and 2B.

FIG. 2B is a cross-sectional view of a state in which the first insulating layer 8 is formed to a predetermined thickness on the exposed structure, the BPSG layer 9 is deposited to a predetermined thickness, and is formed to be flat by flow. In the above, the first insulating layer 8 is formed of oxide or nitride.

The 2c Turning first insulating mask oxide layer with a layer 8 and the BPSG layer 9 is higher NH ₄ OH cleaning (Cleaning) etch selectivity (Etch Selectivity) between or HF (or BCE) deep (DIP) process ( 6) Etch back the BPSG layer 9 below the upper surface of the first insulating layer 8 above, leaving the BPSG layer 9A in the groove of the contact region to a predetermined thickness, After the second insulating layer 10 is deposited on the substrate, the second insulating layer 10 of the bit line and the charge storage electrode contact region is etched using a contact mask to form a second insulating layer pattern 10A. It is sectional drawing of the state in which the 3rd insulating layer 11 was formed in predetermined | prescribed thickness on the structure. In the above, the second and third insulating layers 10 and 11 are formed of oxide or nitride.

FIG. 2D illustrates that the third insulating layer 11 is etched by a blanket etching process to form a third insulating layer spacer 11A on the sidewall of the second insulating layer pattern 10A, and at the same time, the blanket etching is performed. It is sectional drawing in the state in which the predetermined thickness of the BPSG layer 9A filled in the recess of the contact area was removed by excessive etching.

FIG. 2E shows a high etching selectivity of the lower BPSG layer 9A using the first insulating layer 8, the second insulating layer pattern 10A and the third insulating layer spacer 11A as a mask after the FIG. 2D process. After etching using NH ₄ OH cleaning or HF dip process, the first insulating layer 8 exposed to the contact region was removed by a blanket etching process to expose the lower source and drain 2A and 2B, respectively. It is sectional drawing of the state which formed 20.

FIG. 2F illustrates the deposition of the doped polysilicon layer 12 on the entire structure including the contact hole 20 and the removal of a predetermined thickness of the doped polysilicon layer 12 by an etch back process. A cross-sectional view of a state in which charge storage electrodes and bit line contact pads 12B and 12A are formed on the drains 2A and 2B. It should be noted that the polysilicon may be formed on the source and drains 2A and 2B by the selective growth method or the epitaxial growth method by forming the contact pad. It may be.

FIG. 2g shows the bit line conductive layer 13 and the bit line mask oxide layer 14 on the entire structure, each having a predetermined thickness, and a photosensitive film 15 is applied thereon, and then using a bit line mask. It is sectional drawing of the state which formed the air gap film pattern 15A.

FIG. 2h illustrates the exposed mask oxide layer 14 and the bit line conductive layer 13 using the photoresist pattern 15A as a mask until the upper portion of the contact pad 12B of the source 2A is exposed. Each is etched to form a bit line 13A connected to the mask oxide layer pattern 14A and the bit line contact pad 12A, the photoresist layer pattern 15A is removed, and then includes the mask oxide layer pattern 14A. After the predetermined thickness is deposited on the entire structure, the fourth insulating layer spacers 16A are formed on the sidewalls of the bit line 13A and the mask oxide layer pattern 14A by blanket etching. A cross-sectional view showing that the conductive layer for charge storage electrode 17 is deposited on the upper portion and connected to the exposed contact pad 12B for the lower portion of charge storage electrode, thereby forming the charge storage electrode pattern in a later step.

3A to 3E are sectional views showing the contact manufacturing method of the present invention by cutting the line B-B of FIG. 1, and FIG. 2A shows bit line contact portions not shown in FIGS.

FIG. 3A is a BB cross-sectional structure of the process of FIG. 2C, wherein the silicon substrate 1, the field oxide film 3, the drain 2B, the first insulating layer 8, the BPSG layer 9, and the second insulating layer pattern ( 10A) and a third insulating layer spacer 11A.

FIG. 3B is a sectional view of a state in which grooves are formed by etching back a predetermined thickness of the BPSG layer 9 exposed after the FIG. 3A process.

FIG. 3C is a BB cross-sectional structure of the FIG. 2F process, in which the contact hole 20 is formed by removing the BPSG layer 9 on the drain 2B, and then forming the bit line contact pads 12A. It is a cross section.

FIG. 3D is a BB cross-sectional structure of the FIG. 2G process, in which a bit line conductive layer 13 connected to the bit line contact pad 12A is formed, and a mask oxide layer 14 and a photoresist film 15 are formed thereon. After filling, it is sectional drawing of the state which formed the photosensitive film pattern 15A using the bit line mask.

3E shows a mask oxide layer pattern 14A and a bit line 13A by an etching process, removes the photoresist pattern 15A, and then forms a fourth insulating layer spacer 16A on the sidewall of the bit line 13A. Is a cross-sectional view of a state in which a conductive layer 17 for charge storage electrodes is deposited on the entire structure.

4A to 4D are sectional views showing the contact manufacturing method of the present invention by cutting the C-C line of FIG. 1, showing the contact portion of the charge storage electrode.

FIG. 4A is a cross-sectional view of the CC cross-section of the process of FIG. 2C. The silicon substrate 1, the field oxide film 3, the source 2A, the first insulating layer 8, the BPSG layer 9, and the second insulating layer pattern ( 10A) and the third insulating layer spacer 11A are shown.

4B is a cross-sectional view of a state in which grooves are formed by etching back a predetermined thickness of the BPSG layer 9 exposed after the process of FIG. 4A.

4C is a cross-sectional view of the CC cross-section of FIG. 2F, wherein the contact hole 20 is formed by removing the BPSG layer 9 on the source 2A, and then forming the contact pad 12B for the charge storage electrode. It is a cross section of.

FIG. 4D is a cross-sectional view of the CC cross-section of FIG. 2G. The fourth insulating layer spacer 16A is formed on the upper surface of the contact hole 20, and the conductive layer 17 for the charge storage electrode is deposited on the entire structure. It is sectional drawing of the state connected to the contact pad 12B of FIG.

As described above, according to the present invention, the upper conductive layer is contacted to the lower conductive layer by using three self-aligned contacts in a semiconductor device having a high degree of integration. In particular, the bit line contact between the word line and the word line is performed. During the line contact process, the bit line and word line are shorted because the insulating layer on the side of the word line is susceptible to damage during the etching process, and the problem that the disconnection or resistance increases in the contact hole due to the step difference in the lower part Can be.

In addition, when forming the contact hole of the charge storage electrode contact, the margin of the photo process is small so that the word line and the bit line are damaged or the etch selectivity is lowered due to the increase of the aspect ratio. Can be.

Claims (3)

In the contact manufacturing method of a highly integrated device, after forming a MOSFET consisting of a gate electrode, a source and a drain on a semiconductor substrate, and sequentially forming a first insulating layer and a BPSG layer in the overall structure including the MOSFET, Planarizing the BPSG layer, and etching the BPSG layer so that the upper surface of the first insulating layer in the etch back process is exposed, thereby leaving the BPSG layer in the groove of the contact region. Forming a second insulating layer on the second insulating layer, and forming a second insulating layer pattern by the second insulating layer etching process using a contact mask; and forming a third insulating layer on the entire structure including the second insulating layer pattern. Forming a third insulating layer spacer on the sidewalls of the second insulating layer pattern by etching the third insulating layer until the BPSG layer remaining in the groove is sufficiently exposed by a blanket etching process. And removing the BPSG layer remaining in the recess, and etching the exposed first insulating layer by a blanket etching process to form a contact hole, and forming a contact pad in the contact hole. Sequentially stacking the bit line conductive layer and the mask oxide layer on the entire structure including the pad, and forming a bit line and a mask oxide layer pattern by an etching process using a bit line mask, and forming the mask oxide layer pattern on the top A fourth insulating layer is formed on the entire structure including the bit line, the fourth insulating layer is etched by a blanket etching process to form a fourth insulating layer spacer on the sidewall of the bit line, and the charge storage electrode is formed on the entire structure. Depositing a conductive layer to connect the contact pad for an electron storage electrode, and then forming a charge storage electrode by a mask pattern process. How to contact the preparation of a highly integrated device, characterized in that eojineun. The method of claim 1, wherein each of the first, second, and third insulating layers is formed of any one of an oxide and a nitride. The method of claim 1, wherein the contact pad is formed by a polysilicon deposition and etch back process.