KR100464934B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR100464934B1 KR100464934B1 KR10-2000-0086650A KR20000086650A KR100464934B1 KR 100464934 B1 KR100464934 B1 KR 100464934B1 KR 20000086650 A KR20000086650 A KR 20000086650A KR 100464934 B1 KR100464934 B1 KR 100464934B1
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- Prior art keywords
- forming
- etching
- interlayer insulating
- contact
- metal wiring
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
Abstract
본 발명은 셀영역과 주변영역을 동시에 노출시키는 금속배선 콘택 식각으로 인해 발생되는 반도체기판의 손실을 방지하도록 한 반도체 소자의 제조 방법에 관한 것으로, 셀영역과 주변영역이 정의된 반도체기판상에 트랜지스터를 형성하는 단계, 상기 셀영역이 소정 부분에 식각버퍼층을 형성하는 단계, 상기 식각버퍼층을 포함한 반도체 기판상에 제 1 층간절연막을 형성하는 단계, 상기 제 1 층간절연막상에 캐패시터를 형성하는 단계, 상기 반도체 기판의 전면에 제 2 층간절연막을 형성하는 단계, 제 1 콘택 마스크를 이용하여 상기 제 1, 2 층간절연막을 식각하여 상기 주변영역 트랜지스터의 소정 부분이 노출되는 금속배선용 제 1 콘택홀을 형성하는 단계, 제 2 콘택마스크를 이용하여 상기 제 2 층간절연막을 식각하여 셀영역의 소정 부분이 노출되는 금속배선용 제 2 콘택홀을 형성하는 단계, 상기 제 1,2 콘택홀을 포함한 전면에 배리어메탈을 형성하는 단계, 및 상기 배리어메탈상에 금속배선을 형성하는 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device which prevents the loss of a semiconductor substrate caused by metal wiring contact etching which simultaneously exposes a cell region and a peripheral region. Forming an etch buffer layer in a predetermined portion of the cell region, forming a first interlayer insulating film on the semiconductor substrate including the etch buffer layer, and forming a capacitor on the first interlayer insulating film; Forming a second interlayer insulating layer on the entire surface of the semiconductor substrate; forming a first contact hole for metal wiring through which a first portion of the peripheral region transistor is exposed by etching the first and second interlayer insulating layers using a first contact mask; Etching the second interlayer insulating layer using a second contact mask to expose a predetermined portion of the cell region. Forming a metal wiring the second contact hole, forming a barrier metal on the front, including the first and second contact holes, and comprises the steps of forming a metal wiring on the barrier metal.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 주변영역의 PMOS 트랜지스터의 특성을 개선시키도록 한 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device to improve characteristics of a PMOS transistor in a peripheral region.
통상적으로 반도체 소자 제조시, 셀영역과 주변영역이 정의된 반도체 기판상에 워드라인을 형성한 후, 이온주입 공정을 진행하여 소스/드레인 접합을 형성한다. 계속해서, 셀영역 상부에 하부전극/유전막/상부전극으로 이루어진 캐패시터를 형성한 후, 전면에 층간절연막을 형성하고 콘택마스크를 이용하여 층간절연막을 식각하여 상부전극과 주변영역의 소스/드레인 접합이 노출되는 금속배선용 콘택홀을 형성한다. 계속해서, 콘택홀에 배리어메탈, 금속배선을 형성한 후, 금속배선과 배리어메탈을 선택적으로 식각하여 캐패시터의 상부전극 및 주변영역의 소스/드레인 접합에 접속되는 금속배선을 형성한다.Generally, in manufacturing a semiconductor device, after forming a word line on a semiconductor substrate in which a cell region and a peripheral region are defined, an ion implantation process is performed to form a source / drain junction. Subsequently, after forming a capacitor including a lower electrode / dielectric film / upper electrode on the cell region, an interlayer insulating film is formed on the front surface and the interlayer insulating film is etched by using a contact mask to etch the source / drain junction between the upper electrode and the peripheral region. The exposed contact hole for metal wiring is formed. Subsequently, after the barrier metal and the metal wiring are formed in the contact hole, the metal wiring and the barrier metal are selectively etched to form the metal wiring connected to the source / drain junction of the upper electrode of the capacitor and the peripheral region.
그러나, 상술한 종래기술에서는 금속배선용 콘택홀을 형성하는 과정, 특히, 금속배선용 콘택홀의 깊이가 깊어짐에 따라 셀영역과 주변영역을 동시에 노출시키는 콘택 식각시, 주변영역의 반도체기판의 손실이 커지고, 주변영역의 콘택 식각과정에서 셀영역의 하부층이 관통되는 문제점이 있다.However, in the above-described prior art, the loss of the semiconductor substrate in the peripheral area is increased during the process of forming the contact hole for the metal wiring, in particular, the contact etching exposing the cell region and the peripheral region at the same time as the depth of the metal wiring contact hole increases. There is a problem that the lower layer of the cell region penetrates during the contact etching process of the peripheral region.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 금속배선 콘택 식각시 셀영역과 주변영역을 동시에 식각함에 따른 반도체기판의 손실을방지하는데 적합한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art, to provide a method of manufacturing a semiconductor device suitable for preventing the loss of the semiconductor substrate by etching at the same time the cell region and the peripheral region during the metal wiring contact etching. have.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 도시한 도면.1A to 1D illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
11 : 반도체 기판 12 : 필드산화막11 semiconductor substrate 12 field oxide film
13 : 워드라인 14 : 소스/드레인 접합13 word line 14 source / drain junction
15 : 폴리실리콘 플러그 16 : 비트라인15 polysilicon plug 16 bit line
16a : 비트라인버퍼층 17 : 스토리지노드 콘택 플러그16a: bit line buffer layer 17: storage node contact plug
18a/18b/18c/18d : 하부전극/유전막/상부전극/플레이트18a / 18b / 18c / 18d: Lower electrode / dielectric film / upper electrode / plate
19a, 19b, 19c : 층간절연막 20 : 산화막19a, 19b, 19c: interlayer insulating film 20: oxide film
21 : 제 1 콘택마스크 22 : 제 1 콘택홀21: first contact mask 22: first contact hole
23 : 제 2 콘택마스크 24 : 제 2 콘택홀23: second contact mask 24: second contact hole
25 : 배리어 메탈 26 : 금속배선25: barrier metal 26: metal wiring
상기의 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은 셀영역과 주변영역이 정의된 반도체기판상에 트랜지스터를 형성하는 단계, 상기 셀영역이 소정 부분에 식각버퍼층을 형성하는 단계, 상기 식각버퍼층을 포함한 반도체 기판상에 제 1 층간절연막을 형성하는 단계, 상기 제 1 층간절연막상에 캐패시터를 형성하는 단계, 상기 반도체 기판의 전면에 제 2 층간절연막을 형성하는 단계, 제 1 콘택 마스크를 이용하여 상기 제 1, 2 층간절연막을 식각하여 상기 주변영역 트랜지스터의 소정 부분이 노출되는 금속배선용 제 1 콘택홀을 형성하는 단계, 제 2 콘택마스크를 이용하여 상기 제 2 층간절연막을 식각하여 셀영역의 소정 부분이 노출되는 금속배선용 제 2 콘택홀을 형성하는 단계, 상기 제 1,2 콘택홀을 포함한 전면에 배리어메탈을 형성하는 단계, 및 상기 배리어메탈상에 금속배선을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising: forming a transistor on a semiconductor substrate having a cell region and a peripheral region defined therein; forming an etch buffer layer on a predetermined portion of the cell region; Forming a first interlayer insulating film on the semiconductor substrate including a buffer layer, forming a capacitor on the first interlayer insulating film, forming a second interlayer insulating film on the entire surface of the semiconductor substrate, and using a first contact mask Etching the first and second interlayer insulating layers to form a first contact hole for metal wiring through which a predetermined portion of the peripheral region transistor is exposed, and etching the second interlayer insulating layer using a second contact mask to Forming a second contact hole for the metal wiring to which a predetermined portion is exposed; forming a barrier metal on the entire surface including the first and second contact holes Phase, and are characterized by yirueojim including the step of forming the metal wiring on the barrier metal.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 도시한 도면이다.1A to 1E are diagrams illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 1a에 도시된 바와 같이, 셀영역과 주변영역이 정의된 반도체기판(11)에소자간 격리를 위한 필드산화막(12)을 형성한 후, 반도체기판(11)상에 다수의 워드라인(13)을 형성한다. 불순물 이온주입을 실시하여 반도체기판(11)에 소스/드레인 접합(14)을 형성하고, 워드라인(13) 사이에 매립되어 소스/드레인접합(14)에 접속되는 다수의 폴리실리콘플러그(15)를 형성한다.As shown in FIG. 1A, after forming a field oxide film 12 for isolation between devices in a semiconductor substrate 11 in which a cell region and a peripheral region are defined, a plurality of word lines 13 are formed on the semiconductor substrate 11. ). A plurality of polysilicon plugs 15 are formed by impurity ion implantation to form source / drain junctions 14 on the semiconductor substrate 11, and are embedded between the word lines 13 and connected to the source / drain junctions 14. To form.
계속해서, 폴리실리콘플러그(15) 중 어느 하나에 접속되는 비트라인(16a)을 형성하고, 후속 금속배선이 형성될 영역에 비트라인버퍼층(16b)을 형성한다.Subsequently, the bit line 16a connected to any one of the polysilicon plugs 15 is formed, and the bit line buffer layer 16b is formed in the region where subsequent metal wiring is to be formed.
이 때, 비트라인버퍼층(16b)은 후속 금속배선용 콘택 식각시 상부층이 과도식각되어 반도체기판(11)을 손상시키는 것을 방지하기 위해 형성되며, 라인형 또는 섬형 중 어느 하나의 형태이고 후속 금속배선보다 그 크기를 크게 한다.At this time, the bit line buffer layer 16b is formed in order to prevent the upper layer from being excessively etched to damage the semiconductor substrate 11 during the subsequent etching of the metal wiring contact. Increase its size.
비트라인(16a) 상부에 폴리실리콘 플러그(15) 중 다른 하나의 폴리실리콘플러그(15)에 접속되는 스토리지노드 콘택플러그(17)를 형성하고, 스토리지노드 콘택플러그(17)에 접속되는 하부전극/유전막/상부전극(18a, 18b, 18c)의 적층 구조로 이루어지는 캐패시터를 형성한다.A storage node contact plug 17 connected to the other polysilicon plug 15 of the polysilicon plug 15 is formed on the bit line 16a, and the lower electrode / connected to the storage node contact plug 17. A capacitor having a stacked structure of dielectric films / upper electrodes 18a, 18b, and 18c is formed.
여기서, 미설명 도면부호 19a,19b,19c는 층간절연막, 13a는 스페이서이며, 캐패시터는 트렌치(Trench) 구조이다.Herein, reference numerals 19a, 19b, and 19c denote interlayer insulating films, 13a denotes spacers, and capacitors have a trench structure.
이와 같이 셀영역에 트랜지스터 및 캐패시터를 형성한 후, 후속 공정으로 셀영역과 주변영역의 금속배선을 위한 콘택 식각을 실시한다.After forming the transistor and the capacitor in the cell region as described above, the contact etching for metal wiring of the cell region and the peripheral region is performed in a subsequent process.
먼저, 상부전극(18c)을 서로 접속시키는 플레이트(18d)를 형성한 후, 전면에 제 1 산화막(20)을 형성한 후 화학적기계적연마(CMP)나 에치백을 실시하여 평탄화한다.First, the plate 18d for connecting the upper electrodes 18c to each other is formed, and then the first oxide film 20 is formed on the entire surface, followed by chemical mechanical polishing (CMP) or etch back to planarize.
도 1b에 도시된 바와 같이, 제 1 산화막(20)상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 금속배선용 제 1 콘택마스크(21)를 형성한다.As shown in FIG. 1B, a photosensitive film is coated on the first oxide film 20 and patterned by exposure and development to form a first contact mask 21 for metal wiring.
계속해서, 제 1 콘택마스크(21)을 이용하여 주변영역의 소스/드레인 접합(14)의 소정부분을 노출시키는 제 1 콘택홀(22)을 형성한다.Subsequently, a first contact hole 22 is formed using the first contact mask 21 to expose a predetermined portion of the source / drain junction 14 in the peripheral region.
도 1c에 도시된 바와 같이, 제 1 콘택마스크(21)을 제거한 후, 전면에 감광막을 도포하고 노광 및 현상으로 패터하여 금속배선용 제 2 콘택마스크(23)을 형성한다. 제 2 콘택마스크(23)을 이용하여 제 1 산화막(20)을 식각하여 플레이트(18d)의 소정 표면이 노출되는 제 2 콘택홀(24)을 형성한다.As shown in FIG. 1C, after removing the first contact mask 21, a photosensitive film is coated on the entire surface and patterned by exposure and development to form a second contact mask 23 for metal wiring. The first oxide film 20 is etched using the second contact mask 23 to form a second contact hole 24 through which a predetermined surface of the plate 18d is exposed.
이와 같이, 한 번의 콘택마스크로 셀영역과 주변영역을 동시에 노출시키는 통상의 기술과는 다르게, 각각 제 1 콘택마스크(21) 및 제 2 콘택마스크(23)를 이용하여 주변영역의 소스/드레인 접합을 노출시키는 제 1 콘택홀(22)과 셀영역을 노출시키는 제 2 콘택홀(24)을 형성하므로, 과도식각으로 인한 주변영역의 반도체기판(11)의 손실을 방지하고 주변영역의 식각 과정에서 셀영역의 플레이트(18d)가 관통되는 현상을 방지할 수 있다.As described above, unlike the conventional technique of simultaneously exposing the cell region and the peripheral region with one contact mask, the source / drain junction of the peripheral region using the first contact mask 21 and the second contact mask 23, respectively. Since the first contact hole 22 to expose the second region and the second contact hole 24 to expose the cell region are formed, it is possible to prevent the loss of the semiconductor substrate 11 in the peripheral region due to the excessive etching and in the etching process of the peripheral region. The phenomenon that the plate 18d of the cell region penetrates can be prevented.
도 1d에 도시된 바와 같이, 제 2 콘택마스크(23)을 제거하고, 노출된 제 1,2 콘택홀을 포함한 전면에 배리어메탈(25)을 증착한 다음, 배리어메탈(25)을 화학적기계적연마나 에치백하여 콘택홀에만 잔류시키고 전면에 금속배선용 금속막을 증착한 후, 선택적으로 패터닝하여 배리어메탈(25)상에 텅스텐, 구리 또는 알루미늄 등의 금속배선(26)을 형성한다.As shown in FIG. 1D, the second contact mask 23 is removed, the barrier metal 25 is deposited on the entire surface including the exposed first and second contact holes, and the chemical barrier polishing of the barrier metal 25 is performed. After etching back, only the contact holes are left and the metal film for metal wiring is deposited on the entire surface. Then, the metal film 26 is selectively patterned to form metal wiring 26 such as tungsten, copper or aluminum on the barrier metal 25.
한편, 배리어메탈(25) 증착후 금속플러그를 형성할 수 있는데 금속플러그는에치백에 의해 형성되고 텅스텐을 이용한다.On the other hand, a metal plug can be formed after deposition of the barrier metal 25. The metal plug is formed by an etch back and uses tungsten.
본 발명이 실시예에서는 주변영역의 소스/드레인 접합을 노출시키는 금속배선용 콘택홀 형성에 대해서만 설명하였지만, 주변 영역의 다른 부분, 예컨대, 워드라인, 비트라인, 폴리실리콘 플러그 중 어느 하나 또는 이들 모두를 노출시키는 금속배선용 콘택홀 형성시에도 적용할 수 있다.Although the present invention has only described the formation of contact holes for metal wiring to expose the source / drain junctions of the peripheral region, any one or both of other portions of the peripheral region, for example, word lines, bit lines, and polysilicon plugs, may be used. The present invention can also be applied to the formation of exposed contact holes for metal wiring.
또한, 본 발명의 실시예에서는 제 1 콘택마스크를 이용하여 주변영역을 먼저 식각한 후 제 2 콘택마스크를 이용하여 셀영역을 식각하였으나, 반대로 제 1 콘택마스크를 이용하여 셀영역을 먼저 식각하고, 제 2 콘택마스크를 이용하여 주변영역을 식각하여 동일한 효과를 구현할 수 있다. 이 때, 주변영역의 다른 부분을 노출시키는 콘택홀 형성시에도 적용 가능하다.Further, in the embodiment of the present invention, the peripheral region is first etched using the first contact mask, and then the cell region is etched using the second contact mask. On the contrary, the cell region is first etched using the first contact mask. The same effect may be realized by etching the peripheral area using the second contact mask. At this time, it is also applicable to the formation of contact holes for exposing other portions of the peripheral area.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 반도체 소자의 제조 방법은 셀영역과 주변영역의 금속배선용 콘택식각을 두 번에 걸쳐 실시하고 셀영역의 금속배선 하부에 비트라인버퍼층을 형성하므로써 금속배선 하부층의 과도식각 및 주변영역의 과도식각으로 인한 반도체 기판의 손실을 방지할 수 있는 효과가 있다.As described above, the method of manufacturing a semiconductor device according to the present invention is performed by performing the contact etching for the metal wiring in the cell region and the peripheral region twice, and forming the bit line buffer layer under the metal wiring in the cell region, thereby over-etching the lower layer of the metal wiring and There is an effect to prevent the loss of the semiconductor substrate due to the excessive etching of the peripheral area.
Claims (5)
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5748521A (en) * | 1996-11-06 | 1998-05-05 | Samsung Electronics Co., Ltd. | Metal plug capacitor structures for integrated circuit devices and related methods |
| JPH10200065A (en) * | 1996-12-29 | 1998-07-31 | Sony Corp | Semiconductor device and its manufacturing method |
| JPH10256505A (en) * | 1997-03-17 | 1998-09-25 | Sony Corp | Manufacture of dram |
| KR19990043724A (en) * | 1997-11-29 | 1999-06-15 | 구본준 | Manufacturing method of semiconductor device |
| KR100292943B1 (en) * | 1998-03-25 | 2001-09-17 | 윤종용 | Fabrication method of dynamic random access memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5748521A (en) * | 1996-11-06 | 1998-05-05 | Samsung Electronics Co., Ltd. | Metal plug capacitor structures for integrated circuit devices and related methods |
| JPH10200065A (en) * | 1996-12-29 | 1998-07-31 | Sony Corp | Semiconductor device and its manufacturing method |
| JPH10256505A (en) * | 1997-03-17 | 1998-09-25 | Sony Corp | Manufacture of dram |
| KR19990043724A (en) * | 1997-11-29 | 1999-06-15 | 구본준 | Manufacturing method of semiconductor device |
| KR100292943B1 (en) * | 1998-03-25 | 2001-09-17 | 윤종용 | Fabrication method of dynamic random access memory device |
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