KR100365755B1 - Mehtod for fabricating semiconductor device - Google Patents

Abstract

The present invention relates to a method of fabricating a semiconductor device to prevent the loss of the gate protective film in a subsequent process, the method comprising the steps of forming a plurality of gate patterns on a semiconductor substrate having a cell region and a peripheral circuit region defined; Sequentially forming a first insulating film and a second insulating film on the entire surface thereof, anisotropically etching the second insulating film to form a first spacer, and performing impurity ion implantation using the first spacer and the gate pattern as a mask. Removing the first spacer, anisotropically etching the first insulating film to form second spacers on both sidewalls of the gate electrode, and forming a third insulating film on the entire surface including the second spacers. And a third spacer selectively etching the third insulating layer to contact the second spacer of the cell region. Forming a polysilicon on the entire surface including the gate electrode and chemically polishing the polysilicon plug; and selectively removing the polysilicon on the peripheral circuit region.

Description

Manufacturing method of semiconductor device {MEHTOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a polysilicon plug.

In general, the bit line or the word line is made of polysilicon, tungsten silicide (Wi-Silicide; WSi _x ), and a capping material. According to a design rule, a mask oxide film or a mask nitride film ( Mask nitride is formed by depositing and patterning it. The problem is that the resistivity of polysilicon and tungsten silicide does not meet the demand of increasing device density, so that tungsten (W) having low resistance instead of tungsten silicide is solved. Is applying.

Hereinafter, a method of manufacturing a semiconductor device according to the related art will be described with reference to the accompanying drawings.

1A to 1D illustrate a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1A, a field oxide film 12 for inter-element isolation is formed on a semiconductor substrate 11 on which a cell region I and a peripheral circuit region I 'are defined, and the semiconductor substrate 11 is formed. After forming the gate oxide film 13 on the gate oxide film 13, the gate electrode 14 is formed. In this case, the gate electrode 14 may be made of conductive polysilicon or tungsten, and may be a gate protective film of any one of a mask nitride film and a mask oxide film as a protective film for insulating the subsequent metal wiring layer. It has a laminated structure including 14a.

Next, the first insulating film 15 for the sidewall is deposited on the entire surface of the semiconductor substrate 11 including the gate electrode 14 and then etched back to form both side walls of the gate electrode 14 on the cell region I. The first spacer 15a is formed in the groove. In this case, the first insulating film 15 for the side wall 15 may use a stacked structure of a nitride film and a silicon oxide film to prevent contamination in a subsequent process, and the first insulating film 15 for the side wall may be formed in the peripheral circuit region I ′ after the etch back. This remains.

As shown in FIG. 1B, a polysilicon film is deposited on the entire surface including the gate electrode 14 and then planarized to separate the polysilicon film on the gate electrode 14 by chemical mechanical polishing to form a polysilicon plug 16. do. At this time, the planarized polysilicon film 16a remains on the peripheral circuit region I ', and the gate protective film 14a of the peripheral circuit region I' is lost by a predetermined thickness after chemical mechanical polishing (A).

As shown in FIG. 1C, a photosensitive film is coated on the entire surface including the polysilicon plug 16 and patterned by exposure and development to form a mask that exposes the peripheral circuit region I ', and then the mask (not shown) is removed. The polysilicon film 16b remaining on the peripheral circuit region I 'of the planarized polysilicon film is removed. At this time, when the residual polysilicon film 16b is removed, the gate protection film 14a is lost by a predetermined thickness (B), and the polysilicon plug 16 is self-aligned using the gate electrode 14 in the cell region (I). Subsequently, the next capacitor and the bit line are connected to the semiconductor substrate 11 at the portion to be connected.

Subsequently, after depositing the second insulating film for the sidewall on the entire surface, the second insulating film and the first insulating film 15 on the peripheral circuit region I 'are anisotropically etched to form a transistor having an LDD structure in the peripheral circuit region I'. To form the second spacer 17 in contact with both side walls of the gate electrode 14 is formed.

Next, an ion implantation process is performed to form a source / drain region (not shown) of the transistor on the entire surface of the semiconductor substrate 11.

As shown in FIG. 1D, after depositing and planarizing the third insulating film 18 on the entire surface, the third insulating film 18 is selectively patterned to form the polysilicon plug 16 and the peripheral circuit region of the cell region I. A contact hole through which a predetermined portion of the semiconductor substrate 11 of (I ') is exposed is formed.

In a subsequent process, a bit line connected through the contact hole is formed, a capacitor is formed on the cell region I, and a subsequent wiring process is performed to complete the semiconductor device.

However, in the above-described prior art, the gate protection film on the gate electrode is lost during planarization for forming the polysilicon plug (A), and the gate protection film is lost again during dry etching to remove the polysilicon film in the peripheral circuit region (B), The gate protective film is also lost in the anisotropic etching for forming the second spacer.

In addition, the etching process for forming the second spacer is a process of etching the same insulating film as the gate protection film, so that the selective etching of the gate protection film cannot be performed. Therefore, all of the gate protection films are etched to damage the conductive film of the gate electrode. Is generated, which causes the gate electrode to be damaged, thereby deteriorating electrical characteristics.

In addition, when tungsten is used as the conductive film of the gate electrode as it is highly integrated, when the gate protective film is etched and the conductive film of the gate electrode is exposed, the equipment may be contaminated in a subsequent heat treatment or cleaning process, and metal contamination may occur in a subsequent process. Problems occur that degrade the reliability of the device.

On the other hand, even if the thickness of the gate protection film is increased in order to prevent the loss of the gate protection film, it is difficult to secure the gate protection film having a sufficient thickness because the loss is large in the process of removing the polysilicon film in the peripheral circuit region.

The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device suitable for preventing the exposure of the gate electrode due to the loss of the gate protective film on the gate electrode.

1A to 1D illustrate a method of manufacturing a semiconductor device according to the prior art;

2A to 2D illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 field oxide film

23: gate oxide film 24: gate electrode

24a: gate protective film 25: silicon nitride film

26: first spacer 27: second spacer

28 silicon oxide film 28a third spacer

29 polysilicon plug 30 interlayer insulating film

The method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a plurality of gate patterns on a semiconductor substrate in which a cell region and a peripheral circuit region are defined; Forming an insulating film sequentially; forming an insulating film by anisotropically etching the second insulating film; forming a first spacer; implanting impurity ions using the first spacer and the gate pattern as a mask; Removing the first insulating film by anisotropically etching the first insulating film to form second spacers on both sidewalls of the gate electrode, forming a third insulating film on the entire surface including the second spacers, and selectively forming the third insulating film. Etching to form a third spacer in contact with the second spacer of the cell region, including the gate electrode Forming polysilicon on the front surface and chemical mechanical polishing to form a polysilicon plug, and selectively removing the polysilicon on the peripheral circuit region.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A to 2D illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, the field oxide film 22 is formed on the semiconductor substrate 21 in which the cell region I and the peripheral circuit region I 'are defined, and the gate oxide film 23 is formed on the semiconductor substrate 21. ) And then the gate electrode 24 is formed on the gate oxide film 23.

In this case, the gate electrode 24 may use polysilicon and tungsten having conductivity, and may have a stacked structure including any one of a gate nitride film 24a or a mask nitride film or a mask oxide film as a protective film for insulating the subsequent metal wiring layer. Have

Subsequently, the silicon nitride film 25 and the silicon oxide film are sequentially formed on the semiconductor substrate 21 including the gate electrode 24, and then the silicon oxide film is anisotropically dried by anisotropic etching having a selectivity to the silicon nitride film 25. Etching is performed to form the first spacers 26.

Subsequently, an ion implantation process is performed to form a source / drain (not shown) of the LDD structure.

As shown in FIG. 2B, the first spacers 26 are removed by wet etching, and the silicon nitride film 25 is anisotropically etched to form the second spacers 27. Next, the silicon oxide film 28 is deposited, and only the silicon oxide film 28 on the cell region I is subjected to an anisotropic etching process to contact the second spacers 27 of the cell region I. To form.

As shown in FIG. 2C, a polysilicon film is deposited on the entire surface including the gate electrode 24 and then planarized to separate the polysilicon film on the gate electrode 24 from each other to form a polysilicon plug 29. At this time, the planarized polysilicon film (not shown) remains on the peripheral circuit region I ', and the silicon oxide film 28 remains, thereby preventing the loss of the gate protection film 24b.

Next, a photoresist film is coated on the entire surface including the polysilicon plug 29 and patterned by exposure and development to form a mask (not shown) exposing the peripheral circuit region I ', and then the flattened poly with a mask. The polysilicon film on the peripheral circuit region I 'of the silicon film is removed. At this time, the polysilicon plug 29 is self-aligned using the gate electrode 24 in the cell region, and is connected to the semiconductor substrate 21 at the portion where the subsequent capacitor and the bit line are to be connected. Since the silicon oxide film 28 remains on the peripheral circuit region I ', the loss of the gate protection film 24a is prevented when the polysilicon film is removed.

As shown in FIG. 2D, after the interlayer insulating film 30 is deposited and planarized on the entire surface, the interlayer insulating film 30 is selectively patterned to form the polysilicon plug 20 and the peripheral circuit region I of the cell region I. A contact hole is formed in which a predetermined portion of the semiconductor substrate 21 of ') is exposed.

In a subsequent process, a bit line connected through a contact hole is formed, a capacitor is formed in the cell region I, and a subsequent wiring process is performed to complete the semiconductor device.

As described above, in the embodiment of the present invention, since the first spacer for forming the LDD structure is formed and the planarization process for forming the polysilicon plug is performed, the thickness of the gate protective film remaining after the planarization process becomes similar. In the subsequent step, one step of reducing the thickness of the gate protective film is omitted, so that the loss of the gate protective film can be prevented.

In addition, since the photo process is not applied in the wet etching process for removing the first spacer, the gate protection layer may be prevented from being lost in the subsequent process without an additional mask process.

In addition, since the second spacer is formed of the silicon nitride film and the third spacer is formed of the silicon oxide film, there is no silicon nitride film under the third spacer in the cleaning process performed before the deposition of the polysilicon film. Can be.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The method of manufacturing the semiconductor device of the present invention as described above has the effect of improving the electrical characteristics of the device by minimizing the process of losing the gate protection film to prevent the exposure of the gate electrode.

Claims (6)

In the manufacturing method of a semiconductor element, Forming a plurality of gate patterns on the semiconductor substrate on which the cell region and the peripheral circuit region are defined; Sequentially forming a first insulating film and a second insulating film on the entire surface including the gate pattern; Anisotropically etching the second insulating film to form a first spacer; Performing impurity ion implantation using the first spacer and the gate pattern as a mask; Removing the first spacer; Anisotropically etching the first insulating layer to form second spacers on both sidewalls of the gate electrode; Forming a third insulating film on the entire surface including the second spacer; Selectively etching the third insulating layer to form a third spacer in contact with the second spacer of the cell region; Forming polysilicon on the entire surface including the gate electrode and chemically polishing the polysilicon plug to form a polysilicon plug; And Selectively removing polysilicon on the peripheral circuit area Method of manufacturing a semiconductor device comprising the. The method of claim 1, And the first insulating film is a silicon nitride film. The method of claim 1, And said second insulating film is a silicon oxide film. The method of claim 1, And the third insulating film is a silicon oxide film. The method of claim 1, The gate pattern is a semiconductor device manufacturing method, characterized in that the laminated film including a gate protective film. The method of claim 1, After forming the third spacer, And the third insulating film remains in the peripheral circuit region.