KR20040007868A - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR20040007868A KR20040007868A KR1020020040467A KR20020040467A KR20040007868A KR 20040007868 A KR20040007868 A KR 20040007868A KR 1020020040467 A KR1020020040467 A KR 1020020040467A KR 20020040467 A KR20020040467 A KR 20020040467A KR 20040007868 A KR20040007868 A KR 20040007868A
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- gate electrode
- semiconductor device
- contact hole
- forming
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 25
- 150000004767 nitrides Chemical class 0.000 claims abstract description 23
- 239000010410 layer Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 2
- 238000005498 polishing Methods 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- -1 spacer nitride Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 자기정렬 콘택(Self-Aligned Contact; SAC)방법을 이용한 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a contact hole using a self-aligned contact (SAC) method.
기존의 반도체 소자에서는 반도체 기판 상에 게이트 산화막(Gate oxide) 및 폴리 실리콘(Poly-Si)을 증착하고 게이트 전극 패터닝(Gate Electrode Patterning) 하여 게이트 전극을 형성한다. 게이트 전극이 형성된 반도체 기판에 스페이서(Spacer)용 질화막(Nitride)을 증착하여 건식 식각을 실시하여 게이트 전극 측벽에 스페이서를 형성한다. 전체 구조 상부에 이온을 주입하여 정션영역을 형성한다. 소자 분리막(Fox)의 보호와 게이트 전극간의 분리를 위해 질화막과 절연막을 증착한 다음 절연막을 평탄화 한다. 자기정렬 콘택 공정을 실시하여 콘택홀을 형성한다.In a conventional semiconductor device, a gate oxide and a poly-Si are deposited on a semiconductor substrate, and a gate electrode is patterned to form a gate electrode. A spacer is formed on the semiconductor substrate on which the gate electrode is formed to form a spacer on the sidewall of the gate electrode by dry etching. Ions are implanted into the entire structure to form the junction region. A nitride film and an insulating film are deposited to protect the device isolation layer Fox and to separate the gate electrode, and then the insulating film is planarized. A self-aligned contact process is performed to form contact holes.
상술한 방법에 의하면, 소자간의 분리를 위해 반도체 기판에 형성하는 소자 분리막이 후속 식각공정에서 소자 분리막의 손실을 억제하기 위하여 전체 구조 상부에 질화막을 증착하게 된다. 이는 게이트 스페이서의 형성으로 인해 줄어든 콘택홀의 임계치수(Critical Dimension; CD)가 질화막에 의해 더욱더 줄어들게 된다. 또한, 비트라인(Bit Line)과 게이트 전극과의 쇼트(Short) 방지를 위해 자기정렬 콘택방법을 이용하여 콘택홀을 형성한다. 하지만, 콘택 식각공정은 질화막에 대한 높은 식각선택비를 가지고 절연막을 식각 하여야 하기 때문에 콘택홀 측벽에 다량의 폴리머(Polymer)가 발생하여 콘택홀의 임계치수를 확보하는데 많은 어려움이 있다.According to the above-described method, a device isolation film formed on a semiconductor substrate for separation between devices deposits a nitride film over the entire structure in order to suppress the loss of the device isolation film in a subsequent etching process. This decreases the critical dimension (CD) of the contact hole, which is reduced due to the formation of the gate spacer, by the nitride film. In addition, a contact hole is formed using a self-aligned contact method to prevent short between the bit line and the gate electrode. However, in the contact etching process, since the insulating film must be etched with a high etching selectivity with respect to the nitride film, a large amount of polymer is generated on the sidewalls of the contact hole, thereby making it difficult to secure the critical dimension of the contact hole.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 게이트 전극 측벽에 스페이서를 형성하지 않고, 질화막과 절연막을 증착한 다음 절연막을 제거하고 게이트 전극 측벽의 질화막을 식각 하여 측벽 스페이서를 형성함과 동시에 콘택홀을 형성함으로써 콘택홀의 임계치수 확보가 용이한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, in order to solve the above problem, the present invention does not form a spacer on the sidewall of the gate electrode, deposits a nitride film and an insulating film, removes the insulating film, and etches the nitride film of the gate electrode sidewall to form sidewall spacers, and simultaneously forms contact holes. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which the critical dimension of the contact hole can be easily formed by forming a C.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도들이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
110 : 반도체 기판112 : 게이트 산화막110 semiconductor substrate 112 gate oxide film
114 : 폴리 실리콘118 : 하드 마스크 층114: polysilicon 118: hard mask layer
116 : 게이트 전극120 : 질화막116 gate electrode 120 nitride film
122 : 절연막124 : 감광막 패턴122: insulating film 124: photosensitive film pattern
130 : 비아홀132 : 스페이서130: via hole 132: spacer
상기의 기술적 과제를 달성하기 위한 본 발명은 게이트 전극이 형성된 반도체 기판에 질화막 및 층간 절연막을 증착하는 단계와, CMP공정을 수행하여 상기 층간 절연막을 평탄화 하는 단계와, 정션 및 콘택홀이 형성될 영역을 정의하는 감광막패턴을 형성하는 단계와, 상기 감광막패턴에 의해 노출된 영역의 상기 층간 절연막을 등방성 식각을 실시하여 제거하는 단계와, 전체구조 상부에 전면 식각을 실시하여 상기 게이트 전극 측벽에 상기 질화막으로 이루어진 측벽 스페이서를 형성하고, 콘택홀을 형성하는 단계 및 전체 구조 상부에 이온주입을 실시하여 정션영역을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법을 제공한다.According to an aspect of the present invention, there is provided a method of depositing a nitride film and an interlayer insulating film on a semiconductor substrate on which a gate electrode is formed, performing a CMP process to planarize the interlayer insulating film, and a region in which junction and contact holes are to be formed. Forming a photoresist pattern defining a photoresist, removing the interlayer insulating layer in an area exposed by the photoresist pattern by isotropic etching, and performing a front surface etch on the entire structure to form the nitride layer on the sidewall of the gate electrode. Forming a sidewall spacer, forming a contact hole, and performing ion implantation on the entire structure to form a junction region.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다. 그러나 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 도면상에서 동일 부호는 동일한 요소를 지칭한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도들이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도 1a를 참조하면, 소자 분리막(미도시)이 형성된 반도체 기판(110) 상부에 게이트 산화막(112), 게이트 전극용 폴리 실리콘(114) 및 하드 마스크 층(118)을 증착한 다음 게이트 전극 패터닝 공정을 실시하여 게이트 전극(116)을 형성한다. 이때, 게이트 전극(116)으로는 플로팅 게이트와 컨트롤 게이트가 적층구조로 형성된 플래시 메모리 셀의 게이트 전극도 포함된다.Referring to FIG. 1A, a gate oxide layer 112, a polysilicon 114 for a gate electrode 114, and a hard mask layer 118 are deposited on a semiconductor substrate 110 on which an isolation layer (not shown) is formed, followed by a gate electrode patterning process. To form a gate electrode 116. In this case, the gate electrode 116 also includes a gate electrode of a flash memory cell in which a floating gate and a control gate are stacked.
도 1b를 참조하면, 게이트 전극(116)이 형성된 전체구조 상부에 질화막(120) 및 산화막 계열의 층간 절연막(122)을 증착한 다음 질화막(120)을 정지층으로 하는 화학적 기계적 연막(Chemical Vaper Deposition; CMP)공정을 실시하여 층간 절연막(122)을 평탄화 한다. 이때 질화막(120)은 콘택홀 형성시 하부의 소자 분리막을 보호하는 역할을 함과 동시에 게이트 전극(116) 측벽에 형성될 스페이서용 질화막의 역할을 한다. 이로써 한번의 질화막(120) 증착으로 게이트 전극의 스페이서 및 콘택홀 식각시 소자분리막의 보호함으로써 공정의 단순화는 물론 콘택홀의 임계치수를 충분히 확보할 수 있다. 또한, CMP공정의 평탄화 타겟(Target)을 게이트 전극(116) 상부의 하드 마스크 층(118)으로 설정하여 게이트 전극(116) 상부에 형성된 질화막(120) 및 층간 절연막(122)을 제거한다.Referring to FIG. 1B, a nitride film 120 and an oxide-based interlayer insulating film 122 are deposited on the entire structure on which the gate electrode 116 is formed, and then a chemical vapor deposition using the nitride film 120 as a stop layer. CMP) process to planarize the interlayer insulating film 122. In this case, the nitride film 120 serves to protect the device isolation layer at the bottom of the contact hole and at the same time serves as a spacer nitride film to be formed on the sidewall of the gate electrode 116. As a result, the device isolation layer is protected during the spacer electrode and the contact hole etching of the gate electrode by one deposition of the nitride film 120, thereby simplifying the process and sufficiently securing the critical dimension of the contact hole. In addition, the planarization target (Target) of the CMP process is set as the hard mask layer 118 on the gate electrode 116 to remove the nitride film 120 and the interlayer insulating film 122 formed on the gate electrode 116.
도 1c를 참조하면, 전체구조 상부에 감광막을 도포한 다음포토리소그라피(Photolithography) 공정을 실시하여 감광막 패턴(124)을 형성한다. 감광막 패턴(124)은 정션(Junction)이 형성될 영역과 콘택홀(130)이 형성될 영역을 개방한다. 감광막 패턴(124)을 식각마스크로 하는 등방성 식각공정을 실시하여 층간 절연막(122)을 식각한다. 상술한 등방성 식각으로는 HF 와 NH4F가 100 : 1 또는 300 : 1로 혼합된 버퍼드 옥사이드 에쳔트(Buffered Oxide Etchant; BOE)를 이용하여 식각을 실시한다. 이로써, 감광막 패턴(124)에 의해 노출된 영역의(즉, 게이트 전극과 게이트 전극간) 산화막을 완전히 제거함으로써 하부에 질화막이 위치한 콘택홀(130)을 형성한다.Referring to FIG. 1C, a photoresist film is coated on the entire structure, and then a photolithography process is performed to form the photoresist pattern 124. The photoresist pattern 124 opens a region where a junction is to be formed and a region where the contact hole 130 is to be formed. The interlayer insulating layer 122 is etched by performing an isotropic etching process using the photoresist pattern 124 as an etching mask. For the isotropic etching described above, etching is performed using a buffered oxide etchant (BOE) in which HF and NH 4 F are mixed at 100: 1 or 300: 1. As a result, the contact hole 130 in which the nitride film is positioned is formed by completely removing the oxide film in the region exposed by the photosensitive film pattern 124 (that is, between the gate electrode and the gate electrode).
도 1d를 참조하면, 상기 감광막 패턴(124) 제거한 다음 전면 식각(Blanket Etch)을 실시하여 층간 절연막(122)의 제거로 인해 형성된 콘택홀(130) 하부의 질화막(120) 제거와 게이트 스페이서(132)를 형성한다. 또는, 이로써 게이트 전극(116)을 감싸고 있는 질화막(120)의 손실이 거의 없어 자기정렬콘택의 안정성을 유지할 수 있고, 콘택홀의 임계치수를 충분히 확보할 수 있다. 전체 구조 상부에 이온주입을 실시하여 정션영역(미도시)을 형성함으로써, 게이트, 소스 및 드레인으로 구성된 반도체 소자를 형성한다.Referring to FIG. 1D, the photoresist layer pattern 124 is removed, followed by blanket etching to remove the nitride layer 120 and the gate spacer 132 under the contact hole 130 formed by the removal of the interlayer insulating layer 122. ). Alternatively, there is almost no loss of the nitride film 120 surrounding the gate electrode 116, thereby maintaining stability of the self-aligned contact, and sufficiently securing the critical dimension of the contact hole. Ion implantation is performed on the entire structure to form a junction region (not shown), thereby forming a semiconductor device consisting of a gate, a source, and a drain.
상술한 바와 같이, 본 발명은 콘택홀을 먼저 형성한 다음 게이트 스페이서 및 이온주입을 함으로써, 콘택홀의 임계치수를 충분히 확보할 수 있다.As described above, in the present invention, the contact hole is first formed, and then the gate spacer and the ion implantation are used to sufficiently secure the critical dimension of the contact hole.
또한, 충분한 콘택홀의 임계치수를 확보함으로써 콘택 저항을 줄일 수 있다.In addition, the contact resistance can be reduced by securing a critical dimension of a sufficient contact hole.
또한, 한번의 질화막 증착공정을 실시하여 하부 필드 산화막을 보호하고, 게이트 스페이서를 형성함으로써 공정의 단순화를 이룰 수 있다.In addition, the process of simplifying the process may be achieved by performing a single nitride film deposition process to protect the lower field oxide layer and forming a gate spacer.
Claims (3)
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100620703B1 (en) * | 2004-12-30 | 2006-09-13 | 동부일렉트로닉스 주식회사 | Bonding Pad and Method for Forming the Same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100620703B1 (en) * | 2004-12-30 | 2006-09-13 | 동부일렉트로닉스 주식회사 | Bonding Pad and Method for Forming the Same |
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