KR100381030B1 - Method for fabricating semicondductor device - Google Patents
Method for fabricating semicondductor device Download PDFInfo
- Publication number
- KR100381030B1 KR100381030B1 KR10-2000-0084539A KR20000084539A KR100381030B1 KR 100381030 B1 KR100381030 B1 KR 100381030B1 KR 20000084539 A KR20000084539 A KR 20000084539A KR 100381030 B1 KR100381030 B1 KR 100381030B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- field oxide
- semiconductor substrate
- polysilicon
- etching
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
본 발명은 인접셀간 브릿지를 방지하도록 한 반도체 소자의 제조 방법에 관한 것으로, 반도체 기판에 소자간 격리를 위한 필드산화막을 형성하는 단계, 상기 반도체 기판상에 다수의 게이트전극을 형성하는 단계, 상기 게이트전극을 포함한 반도체 기판상에 측벽용 절연막을 형성하는 단계, 상기 반도체 기판의 활성영역만을 노출시킨 상태에서 상기 측벽용 절연막을 전면식각하여 상기 게이트전극의 양측벽에 접하는 측벽 스페이서를 형성하는 단계, 상기 반도체 기판의 전면에 폴리실리콘을 형성하는 단계, 상기 폴리실리콘을 화학적기계적연마하여 상기 게이트전극 사이에 서로 분리된 폴리실리콘 플러그를 형성하는 단계, 상기 필드산화막 상부를 오픈시키는 필드산화막 오픈마스크를 형성하는 단계, 및 상기 필드산화막 오픈마스크에 의해 노출된 상기 필드산화막 상부의 상기 측벽용 절연막 상에 잔류하는 폴리실리콘을 선택적으로 식각하여 제거하는 단계를 포함하여 이루어진다.The present invention relates to a method for fabricating a semiconductor device to prevent bridges between adjacent cells, the method comprising: forming a field oxide film for isolation between devices on a semiconductor substrate; forming a plurality of gate electrodes on the semiconductor substrate; Forming a sidewall insulating film on a semiconductor substrate including an electrode, forming a sidewall spacer in contact with both sidewalls of the gate electrode by etching the entire sidewall insulating film while exposing only an active region of the semiconductor substrate; Forming polysilicon on the front surface of the semiconductor substrate; forming polysilicon plugs separated from each other between the gate electrodes by chemical mechanical polishing of the polysilicon; and forming a field oxide open mask that opens an upper portion of the field oxide layer. And exposed by the field oxide open mask. And selectively etching and removing polysilicon remaining on the sidewall insulating film on the field oxide film.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 플러그를 구비하는 반도체 소자의 제조 방법에 관한 것이다.TECHNICAL FIELD This invention relates to the manufacturing method of a semiconductor element. Specifically, It is related with the manufacturing method of the semiconductor element provided with a plug.
이하 첨부 도면을 참조하여 종래기술에 대해 설명하기로 한다.Hereinafter, the related art will be described with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래기술에 따른 반도체 소자의 제조 방법을 도시한 공정 단면도로서, 셀(Cell) 영역만을 도시하고 있다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art, and show only a cell region.
도 1a에 도시된 바와 같이, 반도체기판(11)에 소자간 격리를 위한 필드산화막(12)을 형성한 후, 반도체기판(11)상에 다수의 게이트전극(13)을 형성한다.As shown in FIG. 1A, after forming the field oxide film 12 for isolation between devices on the semiconductor substrate 11, a plurality of gate electrodes 13 are formed on the semiconductor substrate 11.
계속해서, 게이트전극(13)을 포함한 전면에 측벽용 절연막을 증착하고 셀지역만 오픈한 상태에서 측벽용 절연막을 전면식각하여 게이트전극(13)의 양측벽에 접하는 측벽스페이서(14)를 형성한다. 이 때, 셀영역의 활성영역과 필드산화막(12)상에 형성된 측벽용 절연막은 모두 전면식각되며, 측벽스페이서(14)는 게이트전극 (13)과 후속 폴리실리콘 플러그를 절연시킨다.Subsequently, the sidewall insulating film is deposited on the entire surface including the gate electrode 13, and the sidewall insulating film is etched by etching the sidewall insulating film in a state where only the cell region is opened, thereby forming sidewall spacers 14 contacting both side walls of the gate electrode 13. . At this time, both the active region of the cell region and the sidewall insulating film formed on the field oxide film 12 are all etched away, and the sidewall spacer 14 insulates the gate electrode 13 from the subsequent polysilicon plug.
도 1b에 도시된 바와 같이, 반도체 기판(11)의 전면에 폴리실리콘을 증착한 후 단차를 제거하기 위한 화학적기계적연마(Chemical Mechanical Polishing; CMP) 공정을 실시하여 게이트전극(13)사이에 매립되는 폴리실리콘 플러그(15)를 형성한다.As shown in FIG. 1B, the polysilicon is deposited on the entire surface of the semiconductor substrate 11 and then buried between the gate electrodes 13 by performing a chemical mechanical polishing (CMP) process to remove a step. The polysilicon plug 15 is formed.
도 1c에 도시된 바와 같이, 필드산화막(12) 상부의 폴리실리콘 플러그(15)를 선택적으로 식각하여 필드산화막(12) 상부를 노출시킨다(16).As illustrated in FIG. 1C, the polysilicon plug 15 on the field oxide layer 12 is selectively etched to expose the top portion of the field oxide layer 12 (16).
그러나, 상술한 종래기술에서는 폴리실리콘 플러그(15)가 선택적으로 식각된 필드산화막(12) 상부에 식각잔막이 잔류하여 셀간 완전 절연이 되지 않아 인접 셀영역과의 브릿지(Bridge)가 발생하거나 식각 타겟이 커서 식각량의 증가로 측벽스페이서(14)의 손실을 발생시키는 문제점이 있다.However, in the above-described conventional technology, the etching residual film remains on the field oxide film 12 in which the polysilicon plug 15 is selectively etched, so that the cells are not completely insulated, thereby generating a bridge to an adjacent cell region or an etching target. This cursor has a problem of causing loss of the sidewall spacer 14 due to the increase in the etching amount.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 셀영역의 필드산화막 상부를 절연시키기 위한 폴리실리콘 플러그 식각시 식각잔막으로 인한 인접 셀영역간 브릿지를 방지하고, 측벽스페이서의 손실을 방지하는데 적합한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art, to prevent the bridge between the adjacent cell region due to the etch residual film during polysilicon plug etching to insulate the upper field oxide film of the cell region, and to prevent the loss of sidewall spacers It is an object to provide a method for manufacturing a suitable semiconductor device.
도 1a 내지 도 1c는 종래기술에 따른 반도체 소자의 제조 방법을 도시한 공정 단면도,1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 도시한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 필드산화막21 semiconductor substrate 22 field oxide film
23 : 게이트전극 24 : 측벽용 절연막23 gate electrode 24 insulating film for side wall
24a : 스페이서 25 : 활성영역 오픈 마스크24a: spacer 25: active area open mask
26 : 폴리실리콘 26a : 폴리실리콘 플러그26: polysilicon 26a: polysilicon plug
26b : 잔류 폴리실리콘 27 : 필드산화막 오픈 마스크26b: Residual polysilicon 27: Field oxide film open mask
상기의 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은 반도체 기판에 소자간 격리를 위한 필드산화막을 형성하는 단계, 상기 반도체 기판상에 다수의 게이트전극을 형성하는 단계, 상기 게이트전극을 포함한 반도체 기판상에 측벽용 절연막을 형성하는 단계, 상기 반도체 기판의 활성영역만을 노출시킨 상태에서 상기 측벽용 절연막을 전면식각하여 상기 게이트전극의 양측벽에 접하는 측벽 스페이서를 형성하는 단계, 상기 반도체 기판의 전면에 폴리실리콘을 형성하는 단계, 상기 폴리실리콘을 화학적기계적연마하여 상기 게이트전극 사이에 서로 분리된 폴리실리콘 플러그를 형성하는 단계, 상기 필드산화막 상부를 오픈시키는 필드산화막 오픈마스크를 형성하는 단계, 및 상기 필드산화막 오픈마스크에 의해 노출된 상기 필드산화막 상부의 상기 측벽용 절연막 상에 잔류하는 폴리실리콘을 선택적으로 식각하여 제거하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a field oxide film for isolation between devices on a semiconductor substrate, forming a plurality of gate electrodes on the semiconductor substrate, including the gate electrode Forming a sidewall insulating film on the semiconductor substrate, forming a sidewall spacer in contact with both sidewalls of the gate electrode by etching the entire sidewall insulating film while only the active region of the semiconductor substrate is exposed; Forming polysilicon on the front surface; forming polysilicon plugs separated from each other between the gate electrodes by chemical mechanical polishing of the polysilicon; forming a field oxide open mask to open the field oxide layer; The field oxide film exposed by the field oxide open mask And selectively etching and removing the polysilicon remaining on the upper sidewall insulating film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 도시한 공정 단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체 기판(21)에 소자간 격리를 위한 필드산화막(22)을 형성한 후, 필드산화막(22)을 포함한 반도체 기판(21)상에 소정 간격을 갖는 다수의 게이트전극(23)을 형성한다. 여기서, 게이트전극(23)은 폴리실리콘, 폴리실리콘과 전도막의 적층막으로 이루어지며, 게이트전극(23) 하부에는 게이트산화막(도시 생략)이 형성된다.As shown in FIG. 2A, after forming the field oxide film 22 for isolation between devices in the semiconductor substrate 21, a plurality of gates having a predetermined interval on the semiconductor substrate 21 including the field oxide film 22 are formed. The electrode 23 is formed. Here, the gate electrode 23 is formed of a laminated film of polysilicon, polysilicon, and a conductive film, and a gate oxide film (not shown) is formed under the gate electrode 23.
게이트전극(23)을 포함한 전면에 측벽용 절연막(24)을 증착한 후, 셀영역의 활성영역만을 오픈시키는 활성영역 오픈 마스크(25)를 이용하여 측벽용 절연막(24)을 전면식각하여 활성영역 상부의 게이트전극(23)의 양측벽에 접하는 측벽 스페이서(24a)를 형성한다. 이 때, 필드산화막(22) 상부의 게이트전극(23)상에는 측벽용 절연막(24)이 잔류한다.After depositing the sidewall insulating film 24 on the entire surface including the gate electrode 23, the sidewall insulating film 24 is etched entirely using an active region open mask 25 that opens only the active region of the cell region. Side wall spacers 24a are formed in contact with both side walls of the upper gate electrode 23. At this time, the sidewall insulating film 24 remains on the gate electrode 23 on the field oxide film 22.
한편, 활성영역 오픈 마스크(25)는 반도체기판(21)의 전면에 감광막을 도포하고 노광 및 현상으로 패터닝하여 형성된다.On the other hand, the active area open mask 25 is formed by applying a photosensitive film to the entire surface of the semiconductor substrate 21 and patterning it by exposure and development.
도 2b에 도시된 바와 같이, 활성영역 오픈 마스크(25)를 제거한 후, 반도체 기판(21)의 전면에 폴리실리콘(26)을 증착한다.As shown in FIG. 2B, after the active region open mask 25 is removed, polysilicon 26 is deposited on the entire surface of the semiconductor substrate 21.
도 2c에 도시된 바와 같이, 폴리실리콘(26)의 단차를 제거하기 위한 화학적기계적연마 공정을 실시하여 활성영역 상부에 서로 분리된 폴리실리콘 플러그(26a)를 형성한다.As shown in FIG. 2C, a chemical mechanical polishing process for removing the steps of the polysilicon 26 is performed to form polysilicon plugs 26a separated from each other on the active region.
이 때, 필드산화막(22) 상부에 증착된 폴리실리콘(26)도 화학적기계적연마되는데, 게이트전극(23)의 사이에 잔류하는 측벽용 절연막(24) 중 게이트전극(23) 상부의 측벽용 절연막(24)이 연마되어 게이트전극(23) 사이의 필드산화막(22)상에만 측벽용 절연막(24b)이 잔류하고 측벽용 절연막(24b)상에 잔류 폴리실리콘(26b)이 잔류한다.At this time, the polysilicon 26 deposited on the field oxide film 22 is also subjected to chemical mechanical polishing. Among the sidewall insulating films 24 remaining between the gate electrodes 23, the insulating film for the sidewalls above the gate electrode 23 is used. The 24 is polished so that the sidewall insulating film 24b remains only on the field oxide film 22 between the gate electrodes 23, and the remaining polysilicon 26b remains on the sidewall insulating film 24b.
도 2c에 도시된 바와 같이, 전면에 감광막을 도포하고 노광 및 현상으로 패터닝하여 필드산화막(22) 상부를 오픈시키는 필드산화막 오픈 마스크(27)를 형성한다.As shown in FIG. 2C, a photoresist film is coated on the entire surface and patterned by exposure and development to form a field oxide film open mask 27 that opens the field oxide film 22.
도 2d에 도시된 바와 같이, 필드산화막 오픈 마스크(27)를 이용하여 필드산화막(22) 상부의 잔류 폴리실리콘(26b)을 식각한다.As shown in FIG. 2D, the remaining polysilicon 26b on the field oxide layer 22 is etched using the field oxide layer open mask 27.
이 때, 전술한 폴리실리콘 플러그(26a)를 형성하기 위한 화학적기계적연마후 필드산화막(22) 상부의 잔류 폴리실리콘(26b)은 하부에 잔류하는 측벽용 절연막 (24b)에 의해 그 식각되어야할 두께가 얇다. 따라서, 폴리실리콘(26b)을 식각하기 위한 식각 타겟이 감소한다.At this time, the remaining polysilicon 26b on the top of the field oxide film 22 after the chemical mechanical polishing to form the polysilicon plug 26a described above has a thickness to be etched by the insulating film 24b for the sidewall remaining below. Thin Thus, the etching target for etching the polysilicon 26b is reduced.
이와 같이, 측벽용 절연막(24b)이 잔류한 상태에서 잔류 폴리실리콘(26b)을 식각하면 식각 잔막을 형성시키지 않으며, 즉, 잔류 폴리실리콘(26b)의 과도 식각 시간(Over etch time) 조절이 가능함에 따라 인접 셀과의 식각 잔막으로 인한 브릿지 마진을 조절하거나 측벽 스페이서의 손실을 방지한다.As such, when the residual polysilicon 26b is etched while the sidewall insulating layer 24b remains, the etching residual layer is not formed, that is, the overetch time of the residual polysilicon 26b can be adjusted. As a result, it is possible to adjust the bridge margin due to the etching residual film with the adjacent cells or to prevent the loss of the sidewall spacers.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 반도체 소자의 제조 방법은 필드산화막 상부에 측벽용 절연막을 잔류시킨채 폴리실리콘을 식각하므로써 식각잔막으로 인한 인접셀과의 브릿지를 방지할 수 있으며, 폴리실리콘 식각시 식각시간을 조절하여 측벽용 절연막의 손실을 방지할 수 있는 효과가 있다.The method of manufacturing a semiconductor device of the present invention as described above can prevent the bridge with adjacent cells due to the etching residual film by etching the polysilicon while the insulating film for the sidewall is left on the field oxide film, and the etching time during the polysilicon etching There is an effect to prevent the loss of the insulating film for the side wall by adjusting the.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0084539A KR100381030B1 (en) | 2000-12-28 | 2000-12-28 | Method for fabricating semicondductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0084539A KR100381030B1 (en) | 2000-12-28 | 2000-12-28 | Method for fabricating semicondductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020055176A KR20020055176A (en) | 2002-07-08 |
| KR100381030B1 true KR100381030B1 (en) | 2003-04-26 |
Family
ID=27687929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2000-0084539A KR100381030B1 (en) | 2000-12-28 | 2000-12-28 | Method for fabricating semicondductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100381030B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100701802B1 (en) * | 2005-09-09 | 2007-03-30 | 대주전자재료 주식회사 | Insulator coated with hydrophilic photocatalyst |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000038331A (en) * | 1998-12-05 | 2000-07-05 | 김영환 | Fabrication method of semiconductor memory device |
| KR20000042874A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Fabrication method of semiconductor device |
| KR20000051867A (en) * | 1999-01-27 | 2000-08-16 | 김영환 | Manufacturing method for semiconductor memory |
| US6124192A (en) * | 1999-09-27 | 2000-09-26 | Vanguard International Semicondutor Corporation | Method for fabricating ultra-small interconnections using simplified patterns and sidewall contact plugs |
-
2000
- 2000-12-28 KR KR10-2000-0084539A patent/KR100381030B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000038331A (en) * | 1998-12-05 | 2000-07-05 | 김영환 | Fabrication method of semiconductor memory device |
| KR20000042874A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Fabrication method of semiconductor device |
| KR20000051867A (en) * | 1999-01-27 | 2000-08-16 | 김영환 | Manufacturing method for semiconductor memory |
| US6124192A (en) * | 1999-09-27 | 2000-09-26 | Vanguard International Semicondutor Corporation | Method for fabricating ultra-small interconnections using simplified patterns and sidewall contact plugs |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020055176A (en) | 2002-07-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100381030B1 (en) | Method for fabricating semicondductor device | |
| KR100348222B1 (en) | A method for forming a contact line of a semiconductor device | |
| KR100313957B1 (en) | Method for fabricating of capacitor | |
| KR100800131B1 (en) | Method for fabricating semiconductor device | |
| KR100399963B1 (en) | Method for forming storage node electrode semiconductor device | |
| KR20010056884A (en) | Method for forming bit line contact of semiconductor | |
| KR100307536B1 (en) | Manufacturing method for cell transistor in dram | |
| KR100370120B1 (en) | Method for forming contact | |
| KR20020058512A (en) | Method for fabricating semiconductor device | |
| KR100314737B1 (en) | Method for forming contact hole spacer in semiconductor device | |
| KR100531551B1 (en) | Semiconductor device and method for fabricating the same | |
| KR100328824B1 (en) | Manufacturing method for capacitor | |
| KR100280549B1 (en) | Manufacturing Method For Capacitor | |
| KR100400763B1 (en) | Method for manufacturing capacitor of semiconductor device | |
| KR100249175B1 (en) | Method for fabricating of capacitor | |
| KR100388213B1 (en) | method for forming a storage node in a semiconductor device | |
| KR19980077340A (en) | Method for forming storage electrode of semiconductor device | |
| KR20000043188A (en) | Method for manufacturing capacitor of semiconductor device | |
| KR20040070482A (en) | Method of manufacturing a flash memory device | |
| KR20020056639A (en) | method for manufacturing of semiconductor device | |
| KR19990057080A (en) | Manufacturing method of semiconductor device | |
| KR20030056901A (en) | Method for forming storage node electrode of capacitor | |
| KR19980045145A (en) | Contact hole formation method of semiconductor device | |
| KR19980026842A (en) | Manufacturing method of semiconductor device | |
| KR20040102397A (en) | method for manufacturing landing plug contact in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110325 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |