KR100444773B1 - Method for forming of semiconductor device - Google Patents

Abstract

The present invention can be formed by a dual damascene process for the upper electrode and the lower electrode, and at the same time forming the metal contact of the logic region when forming the DRAM cell lower electrode, the depth of the logic metal contact can be lowered, and the metal contact can be easily buried. In addition, the use of a high-k dielectric for logic analog capacitors has the advantage of reducing the chip size by reducing the capacitor area.

Description

Manufacturing method of semiconductor device {METHOD FOR FORMING OF SEMICONDUCTOR DEVICE}

According to the present invention, the upper electrode and the lower electrode may be formed by a dual damascene process, and the metal contact of the logic region may be simultaneously formed at the time of forming the DRAM cell lower electrode, thereby reducing the depth of the logic metal contact and facilitating the filling of the metal contact. The present invention relates to a method for manufacturing a semiconductor device.

1A to 1P are a first embodiment showing a manufacturing process of a semiconductor device according to the prior art.

First, as shown in FIG. 1A, a well (not shown) and an insulating layer 3 are formed in the DRAM cell part 1 and the logic part 2 of the silicon substrate, and then the gate poly 4 and the hard mask 5 are formed. After depositing and patterning, after forming the source / drain junction layer (6) to form a sidewall spacer (7), after depositing a first ILD (Inter Layer Dielectric: 8) and planarization process.

In this case, the gate poly 14 may be formed of doped polysilicon or a combination of tungsten silicide and tungsten, and the hard mask may be formed of an oxide film.

The sidewall spacers 7 may be formed of an oxide film or a nitride film, or may be formed of a combination of an oxide film and a nitride film.

Subsequently, after forming the storage node contact plug 9 in the DRAM cell region 1 as shown in FIG. 1B, the second ILD 10 is deposited as shown in FIG. 1C, and then the DRAM cell region 1 is formed. The bit line contact hole 11 is formed in the logic region, and the contact hole 12 of the source / drain region is formed in the logic region.

Then, as illustrated in FIG. 1D, a plug is formed in the contact holes 11 and 12, a bit line 15 is formed in the DRAM cell region 1, and a local interconnection line 16 is formed in the logic region 2. Let's do it.

At this time, tungsten silicide or tungsten is used as the material of the bit line 15 and the local interconnection line 16.

Subsequently, as shown in FIG. 1E, the third ILD 17 and the fourth ILD 18 are stacked, and the third ILD 17 and the fourth ILD 18 are partially etched as shown in FIG. After the hole is formed, the plug 19 is formed of a conductive material.

In this case, the double plug technique is used to increase the height of the cell capacitor according to the miniaturization of the pattern.

Then, as illustrated in FIG. 1G, after the fifth ILD 20 and the sixth ILD 21 are deposited, the fifth and sixth ILDs 20 and 21 of the portion where the lower electrode is to be formed are etched. The lower electrode 22 material is deposited as shown in 1h.

In this case, polysilicon or tungsten is generally used as the material of the lower electrode 22.

Thereafter, as shown in FIG. 1I, an insulating layer 23 for etching the lower electrode 22 is deposited, and then the lower electrode 22 is shorted by etch back or CMP as shown in FIG. As shown in FIG. 6, the sixth ILD 21 and the insulating layer 23 of the DRAM cell region 1 are etched to expose the lower electrode 22. In this case, the material of the insulating layer 23 is SOG ( Spin On Glass) or FOX.

Subsequently, as shown in FIG. 1L, the first capacitor insulating film 24 is deposited, and then, as shown in FIG. 1M, the upper electrode 25 is deposited and partially etched to form the upper electrode 25 of the cell capacitor.

At this time, an oxide film, tungsten or Ta2O5 is used as the material of the first capacitor insulating film 24.

Then, as illustrated in FIG. 1N, the seventh ILD 26 and the eighth ILD 27 are deposited and then etched and deposited to form the lower electrode 28 of the analog capacitor in the logic region, and the logic and DRAM ferry region. A wiring 29 for connecting the local wiring of the wire and a wiring 30 connected to the upper electrode of the DRAM cell region to apply a voltage are formed.

At this time, aluminum or tungsten is used as the lower electrode 28 of the logic analog capacitor.

Subsequently, as shown in FIG. 1O, an insulating film 31 of the logic analog capacitor is deposited, and then an upper electrode material 32 is deposited, and then the upper electrode is patterned as shown in FIG. 1P.

At this time, an oxide film or a nitride film is used as the material of the logic analog capacitor insulating film 31, and a TiN film is used as the upper electrode material 32.

Then, after depositing the ninth IMD 33 and the tenth IMD 34, the wiring 34 is formed.

However, the conventional technology according to the first embodiment can only form a DRAM capacitor with a MIS structure or a SIS structure, which increases the complexity of the process and also limits the storage capacity due to the process miniaturization. Since the contact hole depth of the logic region is deepened, it is difficult to process to fill it.

In addition, in the MLD, a logic analog capacitor is formed between the metal 1 and the metal 2, so that the planarization of the IMD layer is difficult due to the topology of the analog capacitor.

2A to 2F are a second embodiment showing a manufacturing process of a semiconductor device according to the prior art.

First, as shown in FIG. 2A, the wells and insulating layers 43 of the DRAM cell region 41 and the logic unit 42 of the silicon substrate are formed, and then the gate poly 44 and the hard mask 45 are deposited. After patterning, the source / drain 46 regions are formed, and then the sidewall spacers 47 are formed.

At this time, the material of the gate is made of a combination of doped polysilicon, tungsten silicide and tungsten.

Next, after the first ILD 48 is deposited, the planarization process is performed, and then the contact holes 49 and the wirings 50 are simultaneously formed in the DRAM region 41 and the logic region 42.

Subsequently, as shown in FIG. 2B, the second ILD 51 is deposited, and then, the etch stop layer 52 is deposited for the dual damascene process, and then the portion and logic where the storage node contact of the DRAM cell region 41 is formed. The region where the metal contact of the region is to be formed is etched.

In this case, a nitride film is used as the etch stop film 52.

Then, as shown in FIG. 2C, the third ILD 53 is deposited, and as shown in FIG. 2D, the third ILD 53 of the portion where the lower electrode of the DRAM region 41 is to be formed is etched. After etching the portion where the metal contact of the logic region is to be formed, the lower electrode material 56 of the DRAM cell region is deposited.

At this time, tungsten or the like is used as the lower electrode material 56.

Next, as shown in FIG. 2E, the lower electrode material 56 is etched back so that a tungsten plug 54 is formed in the logic region and a lower electrode 55 is formed in the DRAM area. Then, as shown in FIG. 2F. As described above, the dielectric layer 57 is deposited and then left only in the DRAM cell region 41 through an etching process, and then the upper electrode 58 is deposited, thereby forming a logic interconnect 59 and a DRAM upper electrode 58.

At this time, Ta 2 O 5 or BST is used as the dielectric film 57.

However, the related art according to the second embodiment has a problem of deteriorating insulation characteristics by performing photo dry etching after deposition of the cell capacitor dielectric film to simultaneously form the MIS or MIM cell capacitor and the logic wiring.

In addition, since the cell storage node is formed at the same time as the lower electrode is formed, it is difficult to fill the storage node with the electrode, and as the pattern becomes finer, short circuit between the DRAM cell bit line and the storage node contact may occur. There was a difficult problem.

The present invention has been made to solve the above problems, and an object of the present invention is to form a top electrode and a bottom electrode in a dual damascene process, and at the same time forming a metal contact of the logic region when forming a DRAM cell bottom electrode, It is to provide a method of manufacturing a semiconductor device that can lower the depth of the metal contact and facilitate the filling of the metal contact.

1A to 1P are a first embodiment showing a manufacturing process of a semiconductor device according to the prior art.

2A to 2F are a second embodiment showing a manufacturing process of a semiconductor device according to the prior art.

3A to 3N are cross-sectional views illustrating a process of manufacturing a semiconductor device according to the present invention.

-Explanation of symbols for the main parts of the drawings-

61: DRAM cell area 62: logic area

64: gate poly 65: hard mask

67: sidewall spacer 68: the first ILD

70: second ILD 79: first etching stop film

82: second etch stop film 86-1: logic analog capacitor

87: lower electrode of the DRAM cell capacitor 90: upper electrode

94, 95, 96: wiring

The present invention for realizing the above object is to form a source / drain junction layer after depositing a gate poly and a hard mask on the DRAM cell portion and the logic portion on the silicon substrate and patterning, and the resultant image formed on the junction layer Depositing a first ILD after forming sidewall spacers in the semiconductor substrate; depositing a second ILD after forming a storage node contact plug in the DRAM cell region; and forming a contact hole in the DRAM cell region and the logic region. Forming a bit line in a DRAM cell region and a local interconnection line in a logic region, depositing a third ILD and a fourth ILD on the resultant, depositing a first etch stop layer, and then etching the DRAM cell in an etching process. Removing a portion where a storage node contact hole is to be formed, depositing a fifth ILD and a second etch stop layer on the resultant, and then etching a second etching of the DRAM cell region. Removing the stop layer by an etching process and depositing a sixth ILD; and a region in which a lower electrode of the DRAM cell capacitor is to be formed and a region in which a logic analog capacitor is to be formed through a dual damascene process on the resultant in which the sixth ILD is deposited. Opening and forming a DRAM cell storage node, depositing a lower electrode material and a seventh ILD on the product on which the DRAM cell storage node is formed, and performing a CMP process, and on the resultant CMP process Depositing a logic analog capacitor insulating film after photo and wet etching; depositing an eighth ILD on the logic analog capacitor insulating film, and patterning the upper electrode to form an upper electrode, and depositing a ninth and tenth ILD. It relates to a method for manufacturing a semiconductor device comprising the step of forming a wiring by patterning.

In this case, the material of the upper electrode and the lower electrode is formed of any one of Pt, Ru, Ir or oxides thereof, and the insulating film of the logic analog capacitor is formed of any one of BST, SBT, PZT, Ta2O5. It is done.

The first etch stop layer or the second etch stop layer may be formed of a nitride film.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

3A to 3N are cross-sectional views illustrating a process of manufacturing a semiconductor device according to the present invention.

First, as shown in FIG. 3A, a well (not shown) and an insulating layer 63 are formed in the DRAM cell 61 and the logic unit 62 on the silicon substrate, and then the gate poly 64 and the hard mask ( 65) is deposited and then patterned, and then the source / drain junction layer 66 is formed, followed by the formation of the sidewall spacers 67 and deposition of the first ILD 68.

At this time, the sidewall spacer 67 is formed of an oxide film or a nitride film.

Subsequently, as shown in FIG. 3B, the storage node contact plug 69 is formed in the DRAM cell region 61. Then, after the second ILD 70 is deposited as shown in FIG. 3C, the DRAM cell is illustrated in FIG. 3D. The bit line contact hole 71 is formed in the region, and the contact hole 72 of the gate or source / drain region is formed in the logic region.

At this time, the storage node contact plug 69 is formed of doped poly or tungsten.

Then, as shown in FIG. 3E, bit lines 75 are used in the DRAM cell region 61 and local interconnect lines 76 are disposed in the logic region 62 using tungsten silicide or tungsten in the contact holes 71 and 72. ).

Subsequently, as shown in FIG. 3F, after the third ILD 77 and the fourth ILD 78 are deposited, the first etch stop layer 79 is deposited, and the DRAM cell storage node contact hole is to be formed by the etching process. Remove 80.

In this case, the third ILD 77 is used to prevent oxidation and adhesion of the bit line and may be omitted.

Thereafter, as illustrated in FIG. 3G, the fifth ILD 81 and the second etch stop layer 82 are deposited, and then the second etch stop layer 82 in the DRAM cell region is removed through etching, and then the sixth ILD ( 83).

Then, as shown in FIG. 3H, the region 85 in which the lower electrode of the DRAM cell capacitor is to be formed and the region 84 in which the logic analog capacitor is to be formed are opened through the dual damascene process, and the DRAM cell storage node 85-is formed. To form 1).

Subsequently, as shown in FIG. 3I, the lower electrode material 86 and the seventh ILD 88 are deposited, and then the lower electrode 87 and the logic analog capacitor of the DRAM cell capacitor are transferred through the CMP as shown in FIG. Short circuit 86-1).

At this time, Pt, Ru, Ir are used as the lower electrode material 86, and SOG or FOX is used as the seventh ILD 88.

Then, as shown in FIG. 3K, the fifth ILD 81, the sixth ILD 83, and the seventh ILD 88 of the DRAM cell are removed through photographic and wet etching, as shown in FIG. 3L. Logic analog capacitor insulating film 89 is deposited.

In this case, the first etch stop layer 79 serves as a mask for wet etching, and as the material of the insulating layer 89, BST, PZT, SBT, Ta 2 O 5, or the like is used.

Subsequently, as illustrated in FIG. 3M, the eighth ILD is deposited and then patterned to form the DRAM cell capacitor upper electrode 90 and the logic electrode capacitor upper electrode 91, and as shown in FIG. 3N, the ninth ILD. And depositing and patterning the 92 and 10th ILDs 93 to connect the wiring 94 connecting the upper and lower electrodes of the analog capacitor in the logic region to the wiring 95 connecting the local wiring of the logic or DRAM ferry region; The wiring 96 for applying the voltage of the upper electrode of the DRAM cell capacitor is formed through the dual damascene technique.

At this time, Al, W, Cu are used as the material of each of the wirings 93, 94, and 95.

As described above, the present invention forms a top electrode and a bottom electrode by a dual damascene process, and simultaneously forms a metal contact of a logic region at the time of forming a DRAM cell bottom electrode, thereby lowering the depth of the logic metal contact and filling the metal contact. In addition, the use of a high-k dielectric for logic analog capacitors has the advantage of reducing the chip size by reducing the area of the capacitor.

Claims (4)

Depositing a gate poly and a hard mask on the DRAM cell portion and the logic portion on the silicon substrate, and then patterning and forming a source / drain junction layer; Depositing a first ILD after forming sidewall spacers on the resultant formed joint layer; Depositing a second ILD after forming a storage node contact plug in the DRAM cell region; Forming contact holes in the DRAM cell region and in the logic region, and forming bit lines in the DRAM cell region and local interconnect lines in the logic region; Depositing a third etch stop layer after depositing a third ILD and a fourth ILD on the resultant, and removing a portion where a DRAM cell storage node contact hole is to be formed by etching; Depositing a fifth ILD and a second etch stop layer on the resultant, removing the second etch stop layer in the DRAM cell region by an etching process, and then depositing a sixth ILD; Opening a region where a lower electrode of the DRAM cell capacitor and a region where a logic analog capacitor is to be formed through a dual damascene process on the resultant on which the sixth ILD is deposited, and forming a DRAM cell storage node; Depositing a lower electrode material and a seventh ILD on a resultant product on which the DRAM cell storage node is formed, and then performing a CMP process; Depositing a logic analog capacitor insulating film after the photo and wet etching the result of the CMP process; And depositing an eighth ILD on the logic analog capacitor insulating layer and patterning the upper electrode to form an upper electrode, and depositing and patterning the ninth and tenth ILD to form wiring. Manufacturing method. The method of manufacturing a semiconductor device according to claim 1, wherein the material of the upper electrode and the lower electrode is formed of any one of Pt, Ru, Ir, or an oxide thereof. The method of claim 1, wherein the insulating film of the logic analog capacitor is formed of any one of BST, SBT, PZT, and Ta 2 O 5. The method of claim 1, wherein the first etch stop layer or the second etch stop layer is formed of a nitride film.