KR100384864B1 - Method for forming gateelectrode in semiconductor device - Google Patents
Method for forming gateelectrode in semiconductor device Download PDFInfo
- Publication number
- KR100384864B1 KR100384864B1 KR10-2000-0074147A KR20000074147A KR100384864B1 KR 100384864 B1 KR100384864 B1 KR 100384864B1 KR 20000074147 A KR20000074147 A KR 20000074147A KR 100384864 B1 KR100384864 B1 KR 100384864B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- film
- gate
- oxide film
- tungsten
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 51
- 239000010937 tungsten Substances 0.000 claims abstract description 51
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 18
- 230000004888 barrier function Effects 0.000 claims abstract description 14
- 238000009792 diffusion process Methods 0.000 claims abstract description 14
- 238000000059 patterning Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000007789 gas Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 description 4
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 3
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- General Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 저저항 미세 게이트전극의 형성 방법에 관한 것으로, 반도체기판상에 게이트산화막을 형성하는 단계, 상기 게이트산화막상에 폴리실리콘, 확산배리어층, 제 1 텅스텐막, 캡산화막, 제 2 텅스텐막을 차례로 형성하는 단계, 상기 제 2 텅스텐막상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 게이트패턴을 형성하기 위한 감광막패턴을 형성하는 단계, 상기 감광막패턴을 이용하여 상기 제 2 텅스텐막을 식각하는 단계, 및 상기 제 2 텅스텐막을 하드마스크로 하여 상기 캡산화막, 상기 제 1 텅스텐막, 상기 확산배리어층 및 상기 폴리실리콘을 순차적으로 식각하여 게이트패턴을 형성하는 단계를 포함하여 이루어진다.The present invention relates to a method of forming a low-resistance fine gate electrode, comprising: forming a gate oxide film on a semiconductor substrate, and forming a polysilicon, a diffusion barrier layer, a first tungsten film, a cap oxide film, and a second tungsten film on the gate oxide film. Forming a photoresist film on the second tungsten film and patterning the photoresist film by exposure and development to form a photoresist pattern for forming a gate pattern; etching the second tungsten film by using the photoresist pattern; Forming a gate pattern by sequentially etching the cap oxide film, the first tungsten film, the diffusion barrier layer, and the polysilicon using the second tungsten film as a hard mask.
본 발명은 제 2 텅스텐막을 추가하므로써 게이트 패터닝시 캡산화막의 손실을 최소화하면서 미세 패턴 형성이 용이한 효과가 있다.The present invention has an effect of easily forming a fine pattern while minimizing the loss of the cap oxide film during gate patterning by adding the second tungsten film.
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 저저항을 갖는 게이트전극의 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a gate electrode having a low resistance.
최근에 반도체 소자의 집적도가 증가함에 따라 게이트 선폭이 감소하여 종래의 높은 저항을 가지는 폴리실리콘(Polysilicon), 텅스텐실리사이드(WSi), 티타늄실리사이드(TiSi2)에 의해서는 소자에서 요구하는 저항을 만족시키지 못하기 때문에 RC 지연시간(Delay time)이 증가하게 된다. 따라서 이와 같은 면저항(Sheet resistance) 문제점을 개선시키기 위하여 텅스텐/폴리실리콘 메탈게이트 (W/Polysilicon metal gate)를 적용하고 있는 추세이다.In recent years, as the degree of integration of semiconductor devices increases, the gate line width decreases, and polysilicon, tungsten silicide (WSi), and titanium silicide (TiSi 2 ), which have high resistances, do not satisfy the resistance required by the device. As a result, the RC delay time is increased. Therefore, in order to improve the sheet resistance problem, a tungsten / polysilicon metal gate is applied.
일반적으로 텅스텐막(W)은 벌크저항(Bulk resistance)이 6μΩㆍcm으로 텅스텐실리사이드(WSi)의 80μΩㆍcm과 티타늄실리사이드(TSi2)의 18μΩㆍcm에 비해 아주 낮은 저항을 가지므로 고집적 소자의 게이트 물질로 적합하다.In general, the tungsten film (W) has a bulk resistance of 6 µΩ · cm, which is much lower than 80 µΩ · cm of tungsten silicide (WSi) and 18 µΩ · cm of titanium silicide (TSi 2 ). It is suitable as a gate material.
그러나, 텅스텐/폴리실리콘(W/Polysilicon) 게이트 구조에서는 후속 500℃이상의 열공정에 의해서 텅스텐과 하부의 폴리실리콘의 반응에 의한 텅스텐실리사이드(WSi)가 형성되므로써, 낮은 텅스텐게이트의 저항을 유지할 수 없는 문제점이 있다. 따라서 일반적으로 텅스텐과 폴리실리콘막 사이에 확산배리어층으로 텅스텐나이트라이드막을 증착하여 텅스텐과 폴리실리콘이 반응하여 저항을 증가시키는 것을 방지한다.However, in the tungsten / polysilicon gate structure, tungsten silicide (WSi) is formed by the reaction of tungsten and polysilicon at the bottom by a subsequent thermal process of 500 ° C. or higher, so that the resistance of the low tungsten gate cannot be maintained. There is a problem. Therefore, in general, a tungsten nitride film is deposited as a diffusion barrier layer between the tungsten and the polysilicon film to prevent the tungsten and the polysilicon from reacting to increase the resistance.
도 1a 내지 도 1c는 종래기술에 따른 게이트전극의 형성 방법을 도시한 도면이다.1A to 1C illustrate a method of forming a gate electrode according to the prior art.
도 1a에 도시된 바와 같이, 반도체기판(11)상에 게이트산화막(12)을 형성한 후, 게이트산화막(12)상에 폴리실리콘(13), 확산배리어층(14), 텅스텐(15), 캡산화막(16)(Cap oxide)을 순차적으로 형성한다. 여기서, 캡산화막(16)상에 하부반사방지막(Bottom Anti Reflective Coating)을 형성할 수 있는데, 하부반사방지막은 게이트 패터닝시 하부막의 반사를 방지하기 위해 이용된다.As shown in FIG. 1A, after the gate oxide film 12 is formed on the semiconductor substrate 11, the polysilicon 13, the diffusion barrier layer 14, the tungsten 15, and the gate oxide film 12 are formed on the gate oxide film 12. Cap oxide layer 16 (Cap oxide) is formed sequentially. Here, a bottom anti-reflective coating may be formed on the cap oxide layer 16. The bottom anti-reflective coating is used to prevent reflection of the lower layer during gate patterning.
캡산화막(16)상에 미세한 패터닝을 위해 감광막을 도포하고 노광 및 현상으로 패터닝하여 게이트패턴을 형성하기 위한 감광막패턴(17)을 형성한다.A photoresist film is applied on the cap oxide film 16 for fine patterning, and patterned by exposure and development to form a photoresist pattern 17 for forming a gate pattern.
도 1b에 도시된 바와 같이, 두께가 감소된 감광막패턴(17a)을 이용하여 하부의 캡산화막(16)을 패터닝한다. 이 때, 하부반사방지막을 적용할 경우, 먼저 하부반사방지막을 패터닝한 후 캡산화막을 패터닝하며, 도면부호 16a는 패터닝된 캡산화막을 나타낸다.As shown in FIG. 1B, the cap oxide layer 16 is patterned by using the photosensitive layer pattern 17a having a reduced thickness. In this case, when the lower anti-reflection film is applied, the lower anti-reflection film is first patterned and then the cap oxide film is patterned, and reference numeral 16a denotes the patterned cap oxide film.
여기서, 도 1a에 도시된 감광막패턴(17)보다 두께가 낮아짐은 미세패턴을 형성하기 위함이다.Here, the thickness is lower than that of the photosensitive film pattern 17 shown in FIG. 1A to form a fine pattern.
도 1c에 도시된 바와 같이, 감광막패턴(17a)을 제거하고, 캡산화막(16a)을 이용하여 텅스텐(15), 확산배리어층(14) 및 폴리실리콘(13)을 순차적으로 패터닝하여 폴리실리콘(13a)/확산배리어층(14a)/텅스텐(15a)/캡산화막(16b)의 적층구조로 이루어진 게이트패턴을 형성한다. 이 때, 캡산화막(16b)은 하부 텅스텐(15a) 패터닝시 소정 두께만큼 손실되어 최종 두께가 감소된다.As shown in FIG. 1C, the photosensitive film pattern 17a is removed, and the tungsten 15, the diffusion barrier layer 14, and the polysilicon 13 are sequentially patterned using the cap oxide film 16a to form polysilicon ( 13a) / diffusion barrier layer 14a / tungsten 15a / cap oxide film 16b, a gate pattern is formed. At this time, the cap oxide film 16b is lost by a predetermined thickness during patterning of the lower tungsten 15a so that the final thickness is reduced.
그러나, 상술한 노광 공정에서는 0.15㎛ 이하의 미세패턴을 형성하기 어렵고, 미세패턴을 형성하기 위하여 감광막의 도포 두께가 낮아지기 때문에 하부반사방지막/캡산화막의 적층막을 식각할 때 충분한 감광막 두께를 확보하지 못하므로 감광막 선택비가 문제로 대두되는 문제점이 있다.However, in the above-described exposure process, it is difficult to form a fine pattern of 0.15 μm or less, and since the coating thickness of the photoresist film is reduced to form the fine pattern, sufficient photoresist film thickness cannot be secured when etching the laminated film of the lower anti-reflection film / cap oxide film. Therefore, there is a problem in that the selection ratio of the photoresist becomes a problem.
또한, 구조에 따라서 높은 두께의 캡산화막이 요구되지만 감광막 선택비 및 텅스텐 식각시 캡산화막의 손실 제어가 힘들어 높은 두께의 캡산화막을 갖는 게이트전극을 형성하는데 한계가 있다.In addition, although a cap oxide film having a high thickness is required according to the structure, there is a limitation in forming a gate electrode having a cap oxide film having a high thickness because cap selectivity and loss control of the cap oxide film at the time of tungsten etching are difficult.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 게이트 패터닝시 캡산화막이 손실되는 것을 방지하고, 높은 두께의 캡산화막과 낮은 두께의 감광막을 적용하여 미세 패터닝이 가능한 저저항 게이트전극의 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art, to prevent the loss of the cap oxide film during gate patterning, by applying a high thickness cap oxide film and a low thickness photosensitive film of the low resistance gate electrode capable of fine patterning The purpose is to provide a formation method.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 게이트전극의 형성 방법을 도시한 도면,1A to 1C illustrate a method of forming a gate electrode according to an exemplary embodiment of the present invention;
도 2a 내지 도 2c는 본 발명의 실시예에 따른 게이트전극의 형성 방법을 도시한 도면.2A to 2C illustrate a method of forming a gate electrode according to an exemplary embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 게이트산화막21 semiconductor substrate 22 gate oxide film
23 : 폴리실리콘 24 : 확산배리어층23: polysilicon 24: diffusion barrier layer
25 : 제 1 텅스텐막 26 : 캡산화막25: first tungsten film 26: cap oxide film
27 : 제 2 텅스텐막 28 : 감광막패턴27: second tungsten film 28: photosensitive film pattern
상기 목적을 달성하기 위한 본 발명의 게이트전극의 형성 방법은 반도체기판상에 게이트산화막을 형성하는 단계, 상기 게이트산화막상에 폴리실리콘, 확산배리어층, 제 1 텅스텐막, 캡산화막, 제 2 텅스텐막을 차례로 형성하는 단계, 상기 제 2 텅스텐막상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 게이트패턴을 형성하기 위한 감광막패턴을 형성하는 단계, 상기 감광막패턴을 이용하여 상기 제 2 텅스텐막을 식각하는 단계, 및 상기 제 2 텅스텐막을 하드마스크로 하여 상기 캡산화막, 상기 제 1 텅스텐막, 상기 확산배리어층 및 상기 폴리실리콘을 순차적으로 식각하여 게이트패턴을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of forming a gate electrode of the present invention for achieving the above object comprises the steps of forming a gate oxide film on a semiconductor substrate, a polysilicon, a diffusion barrier layer, a first tungsten film, a cap oxide film, a second tungsten film on the gate oxide film Forming a photoresist film on the second tungsten film and patterning the photoresist film by exposure and development to form a photoresist pattern for forming a gate pattern; etching the second tungsten film by using the photoresist pattern; And forming a gate pattern by sequentially etching the cap oxide film, the first tungsten film, the diffusion barrier layer, and the polysilicon using the second tungsten film as a hard mask.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2c는 본 발명의 실시예에 따른 게이트전극의 형성 방법을 도시한 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method of forming a gate electrode according to an exemplary embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체기판(21)상에 게이트산화막(22)을 형성하고, 게이트산화막(22)상에 폴리실리콘(23), 확산배리어층(24), 제 1 텅스텐막(25), 캡산화막(26)을 차례로 형성한다. 계속해서, 캡산화막(26)상에 제 2 텅스텐막(27)을 형성한 후, 제 2 텅스텐막(27)상에 감광막을 도포하고 노광 및 현상하여 게이트패턴을 형성하기 위한 감광막패턴(28)을 형성한다.As shown in FIG. 2A, the gate oxide film 22 is formed on the semiconductor substrate 21, and the polysilicon 23, the diffusion barrier layer 24, and the first tungsten film 25 are formed on the gate oxide film 22. ) And the cap oxide film 26 are formed in this order. Subsequently, after the second tungsten film 27 is formed on the cap oxide film 26, the photosensitive film pattern 28 for applying a photosensitive film on the second tungsten film 27, exposing and developing to form a gate pattern is formed. To form.
이와 같이, 감광막패턴(28) 하부에 제 2 텅스텐막(27)이 형성되면, 통상과 동일한 캡산화막 높이를 갖는 게이트전극을 형성한다 할 때, 통상의 기술보다 낮은 두께의 감광막이 요구되어 미세 패턴 형성이 용이하다.As described above, when the second tungsten film 27 is formed below the photoresist pattern 28, when the gate electrode having the same cap oxide film height is formed, a photoresist film having a lower thickness than that of the conventional technology is required and thus the fine pattern is formed. Easy to form
도 2b에 도시된 바와 같이, 감광막패턴(28)을 이용하여 제 2 텅스텐막(27)을 식각하여 제 2 텅스텐막 패턴(27a)을 형성한다.As shown in FIG. 2B, the second tungsten film 27 is etched using the photosensitive film pattern 28 to form the second tungsten film pattern 27a.
도 2c에 도시된 바와 같이, 감광막패턴(28) 제거후, 제 2 텅스텐막 패턴 (27a)을 하드마스크로 하여 게이트패터닝 공정을 진행한다. 예컨대, 하부의 캡산화막(26), 제 1 텅스텐막(25), 확산배리어층(24), 폴리실리콘(23)을 순차적으로 식각하여 폴리실리콘(23a)/확산배리어층(24a)/제 1 텅스텐막(25a)/캡산화막(26a)의 적층 구조로 이루어진 게이트 패턴을 형성한다.As shown in FIG. 2C, after removing the photoresist pattern 28, the gate patterning process is performed using the second tungsten layer pattern 27 a as a hard mask. For example, the lower cap oxide film 26, the first tungsten film 25, the diffusion barrier layer 24, and the polysilicon 23 are sequentially etched to form the polysilicon 23a / diffusion barrier layer 24a / first. A gate pattern formed of a laminated structure of the tungsten film 25a / cap oxide film 26a is formed.
여기서, 캡산화막(26a) 식각시 감광막 선택비와 텅스텐 식각시 감광막 선택비는 유사하며, 이러한 텅스텐을 하드마스크로 이용하여 캡산화막을 식각하면 고선택비 식각이 가능하다. 그리고, 제 2 텅스텐막 패턴(27a)을 하드마스크로 하부의 캡산화막(26) 및 제 1 텅스텐막(25)을 식각하므로 캡산화막(26a)의 손실 제어가 가능하다.Here, the selectivity of the photoresist film at the time of etching the cap oxide film 26a and the photoresist selection ratio at the time of tungsten etching are similar. When the cap oxide film is etched using the tungsten as a hard mask, high selectivity etching is possible. Since the cap oxide film 26 and the first tungsten film 25 are etched with the second tungsten film pattern 27a as a hard mask, loss control of the cap oxide film 26a can be performed.
그리고, 게이트패턴 형성을 위한 식각장치로는 RIE(Reactive Ion Etcher), MERIE(Magnetically Enhanced RIE), HDP(High Density Plasma) 등 플라즈마내 이온밀도(Ion density)와 이온 에너지(Ion energy)를 의존적으로 또는 독립적으로 조절이 가능한 장치(Ion Energy Modulation; 이하 'IEM'이라 약칭함)를 이용한다.In addition, the etching apparatus for forming the gate pattern depends on ion density and ion energy in plasma such as Reactive Ion Etcher (RIE), Magnetically Enhanced RIE (MERIE) and High Density Plasma (HDP). Alternatively, an independently adjustable device (Ion Energy Modulation) may be used.
통상적으로, IEM 식각 장치는 RF(Radio Frequency) 파워가 인가되는 상부전극(Upper electrode)과 하부전극(Bottom electrode)이 구비된다.In general, the IEM etching apparatus includes an upper electrode and a bottom electrode to which RF (Radio Frequency) power is applied.
이러한 IEM 식각장치를 사용하는 경우, 상부전극 및 하부전극에 500W∼2000W의 RF 파워를 인가하고, 장치내 압력을 10mtorr∼100mtorr, 온도를 -30℃∼50℃로 유지한다. 그리고, 식각가스인 산소가스의 플로우(Flow)량이 CxFx계열 가스의 10%∼80% 범위이다.In the case of using such an IEM etching apparatus, RF power of 500 W to 2000 W is applied to the upper electrode and the lower electrode, and the pressure in the apparatus is maintained at 10 mtorr to 100 mtorr and the temperature at -30 ° C to 50 ° C. In addition, the flow amount of oxygen gas, which is an etching gas, is in a range of 10% to 80% of the C x F x series gas.
본 발명의 실시예에서는 캡산화막을 예로 들었지만, 캡질화막(Cap nitride)을 적용할 경우에도 텅스텐막을 하드마스크로 하여 캡질화막 식각이 용이하다.Although the cap oxide film is taken as an example in the embodiment of the present invention, even when a cap nitride film is applied, the cap nitride film is easily etched using the tungsten film as a hard mask.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 게이트전극의 형성 방법은 캡산화막상에 텅스텐막을 추가로 형성하므로써 노광공정시 낮은 두께의 감광막이 요구되므로 미세패턴 형성이 용이하며, 텅스텐막을 하드마스크로 이용하여 캡산화막 식각 및 게이트 식각을 식각을 진행하므로 높은 두께의 캡산화막을 구현할 수 있고, 아울러 캡산화막의 손실 제어가 가능하여 저저항 게이트전극을 형성할 수 있는 효과가 있다.As described above, the method of forming the gate electrode of the present invention further requires forming a tungsten film on the cap oxide film, so that a photosensitive film having a low thickness is required during the exposure process, so that a fine pattern can be easily formed, and the cap oxide film is etched using the tungsten film as a hard mask. And since the gate etching is etched to achieve a high thickness of the cap oxide film, it is possible to control the loss of the cap oxide film has the effect of forming a low resistance gate electrode.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0074147A KR100384864B1 (en) | 2000-12-07 | 2000-12-07 | Method for forming gateelectrode in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0074147A KR100384864B1 (en) | 2000-12-07 | 2000-12-07 | Method for forming gateelectrode in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020044895A KR20020044895A (en) | 2002-06-19 |
| KR100384864B1 true KR100384864B1 (en) | 2003-05-22 |
Family
ID=27680208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2000-0074147A KR100384864B1 (en) | 2000-12-07 | 2000-12-07 | Method for forming gateelectrode in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100384864B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100928528B1 (en) * | 2002-12-30 | 2009-11-26 | 주식회사 하이닉스반도체 | Oxide etching method using tungsten hard mask |
-
2000
- 2000-12-07 KR KR10-2000-0074147A patent/KR100384864B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020044895A (en) | 2002-06-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2622059B2 (en) | Method for manufacturing semiconductor integrated circuit | |
| JP2002217170A (en) | Method of forming fine pattern, method of fabricating semiconductor device and semiconductor device | |
| JP2004031944A (en) | Forming method of very narrow width transistor gate element by photolithography | |
| US6211557B1 (en) | Contact structure using taper contact etching and polycide step | |
| KR100299386B1 (en) | Gate electrode formation method of semiconductor device | |
| KR100384864B1 (en) | Method for forming gateelectrode in semiconductor device | |
| KR20070113604A (en) | Method for forming micro pattern of semiconductor device | |
| KR20020078624A (en) | Method for forming the dual gate of semiconductor device | |
| KR100497609B1 (en) | Method of etching silicon nitride film | |
| KR100282416B1 (en) | Method for fabricating semiconductor device | |
| KR100641548B1 (en) | Method of manufacturing semiconductor device | |
| KR100380282B1 (en) | Gate of semiconductor device and the method of fabricating thereof | |
| KR100328694B1 (en) | Method of manufacturing semiconductor device | |
| KR100439771B1 (en) | Method for preventing hardmask loss of semicondctor device | |
| KR100205095B1 (en) | Method for forming bit line of semiconductor device | |
| KR100436773B1 (en) | Etching method of forming conductive pattern with large cd gain of semiconductor device | |
| KR100319877B1 (en) | Manufacturing method of semiconductor device having polyside structure | |
| KR100342874B1 (en) | Method For Forming The Contact Double Photo Resist | |
| KR100398574B1 (en) | Method for forming gate spacer of semiconductor device | |
| KR100314738B1 (en) | Method for forming gate electrode in semiconductor device | |
| KR100772699B1 (en) | Method for forming semiconductor device | |
| KR20030001084A (en) | Method for forming pattern of semiconductor device | |
| KR100575078B1 (en) | Method For Manufacturing Semiconductor Device | |
| KR0179295B1 (en) | Forming method of metal wiring in semiconductor device | |
| KR100485159B1 (en) | Formation method of contact hole in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110429 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |