KR100447261B1 - Method for manufacturing semiconductor device using nitride layer as etch stop layer - Google Patents

Method for manufacturing semiconductor device using nitride layer as etch stop layer Download PDF

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KR100447261B1
KR100447261B1 KR1019970081325A KR19970081325A KR100447261B1 KR 100447261 B1 KR100447261 B1 KR 100447261B1 KR 1019970081325 A KR1019970081325 A KR 1019970081325A KR 19970081325 A KR19970081325 A KR 19970081325A KR 100447261 B1 KR100447261 B1 KR 100447261B1
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etching
pattern
gas
insulating film
film
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KR19990061071A (en
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김정호
김종삼
김진웅
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to minimize the plasma damage and to restrain polymers by using a nitride layer as an etch stop layer when forming a gate electrode. CONSTITUTION: A first oxide layer, a nitride layer, a second oxide layer and a photoresist pattern are sequentially formed on a substrate(10). A second oxide pattern(16) is formed by etching the second oxide layer to expose the nitride layer using the photoresist pattern as a mask. A nitride pattern(14) and a first oxide pattern(12) are formed by etching the nitride layer and the first oxide layer. The photoresist pattern is removed. A gate insulating layer is formed on the resultant structure. A gate electrode(22) is then formed by forming a metal film and polishing the metal film and the gate insulating layer to expose the second oxide pattern.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 구리와 같은 금속막을 게이트전극에 사용하는 경우 식각정지층으로 질화막을 사용함으로서 반도체 기판이 노출되는 것을 방지하여 플라즈마 손상을 최소화하고 후속공정을 용이하게 실시할 수 있으며, 폴리머 발생과 게이트산화막 손상을 방지할 수 있는 기술에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, in particular, when using a nitride film as the etch stop layer when using a metal film such as copper to prevent the semiconductor substrate is exposed to minimize the plasma damage and facilitate the subsequent process The present invention relates to a technology capable of preventing the occurrence of polymers and damaging gate oxide films.

일반적으로, 반도체 소자의 집적도가 증가함에 따라 게이트 산화막의 두께가 감소하게 되고, 그로인하여 게이트 산화막의 막질이 양호한 것을 요구하게 된다.In general, as the degree of integration of semiconductor elements increases, the thickness of the gate oxide film decreases, thereby requiring that the quality of the gate oxide film be good.

또한, 트랜지스터의 게이트 전극 패턴닝 공정후에 게이트 전극의 측벽의 식각 손상의 회복과 게이트 전극의 활성화를 위하여 산화 공정을 실시하게 되는데 이때 게이트 산화막도 역시 산화되어 게이트 산화막의 에지부가 두꺼워지는 게이트 버즈빅(bird's beak)현상이 발생한다.In addition, after the gate electrode patterning process of the transistor, an oxidation process is performed to recover the etch damage of the sidewall of the gate electrode and to activate the gate electrode. bird's beak).

그리고, 상기 게이트전극을 패터닝하는 과정에서 게이트전극의 과도 식각시 게이트산화막이 제거되어 반도체 기판에 어택(attack)을 받게 된다.In the process of patterning the gate electrode, when the gate electrode is excessively etched, the gate oxide layer is removed to be attacked by the semiconductor substrate.

한편, 초고집적 소자를 구현하기 위해서는 저소비전력화와 초고속화가 필수적인데 이를 위해서는 게이트전극 또는 비트라인 등의 배선을 저항이 낮은 Cu와 같은 금속막을 사용하여야 한다.On the other hand, low power consumption and high speed are essential to realize an ultra-high integration device. For this purpose, a metal film such as Cu having low resistance should be used for wiring of a gate electrode or a bit line.

그러나, 기존의 방식으로 게이트전극를 형성하는 방법은 게이트산화막을 성장시킨후 금속막을 증착하고 감광막마스크를 이용하여 식각공정을 진행하게 되면 다음과 같은 문제점을 야기한다.However, in the conventional method of forming a gate electrode, a gate oxide film is grown, a metal film is deposited, and an etching process is performed using a photoresist mask.

첫째, 구리(Cu)와 같은 금속막 식각시에는 폴리실리콘막 식각과는 다르게 산화막에 대하여 매우 높은 식각선택비를 확보하는 것이 어렵기 때문에 게이트산화막과 같이 매우 얇은 산화막을 사용할 경우 게이트산화막이 손상되어 정상적인 게이트 구현을 어렵게 하였다.First, when etching a metal film such as copper (Cu), it is difficult to secure a very high etching selectivity with respect to the oxide film, unlike the polysilicon film etching, so that when a very thin oxide such as a gate oxide is used, the gate oxide film is damaged. Normal gate implementation is difficult.

둘째, 구리와 같은 물질을 식각할 경우 감광막 제거후 폴리머 제거가 매우 어렵기 때문에 후속 공정을 진행하기가 어려워 게이트전극에 금속막을 적용하지 못하는 문제점이 발생한다.Second, when etching a material such as copper is difficult to remove the polymer after removing the photoresist film, it is difficult to proceed to the subsequent process occurs a problem that can not apply a metal film to the gate electrode.

이에, 본 발명은 상기한 문제점을 해결하기 위한 것으로 산화막/질화막/산화막으로 이루어진 3층 구조의 절연막을 형성한 다음 상부 산화막 식각시 질화막에 대하여 식각선택비의 차를 이용한 식각공정으로 반도체 기판이 노출되는 것을 방지하여 플라즈마 손상을 최소화한 후 질화막 하부의 산화막을 습식식각하고 노출된 반도체 기판에 게이트산화막를 형성한 다음 금속막을 형성하고 화학적,기계적연마(Chemical Mechanical Polishing 이하, CMP)공정을 실시하여 금속막의 게이트전극을 형성함으로서 소자의 전기적 특성을 향상시키는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned problems, and to form a three-layer insulating film consisting of oxide film / nitride film / oxide film and then exposed the semiconductor substrate by the etching process using the difference in etching selectivity with respect to the nitride film during the upper oxide film etching After minimizing plasma damage by minimizing plasma damage, wet etching the oxide film under the nitride film, forming a gate oxide film on the exposed semiconductor substrate, forming a metal film, and performing a chemical mechanical polishing (CMP) process. It is an object of the present invention to provide a method for manufacturing a semiconductor device by improving the electrical characteristics of the device by forming a gate electrode.

도 1a 내지 도 1f 는 본 발명에 따른 반도체 소자의 제조공정도1A to 1F are manufacturing process diagrams of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10 : 반도체 기판 12 : 제 1산화막10 semiconductor substrate 12 first oxide film

14 : 질화막 16 : 제 2산화막14 nitride film 16 second oxide film

18 : 감광막패턴 20 : 게이트산화막18: photosensitive film pattern 20: gate oxide film

22 : 금속막22: metal film

상기 목적을 달성하기 위해 본 발명에 따르면,According to the present invention to achieve the above object,

반도체 기판 상부에 제 1절연막과 제 2절연막, 제 3절연막, 감광막패턴을 순차적으로 형성하는 공정과,Sequentially forming a first insulating film, a second insulating film, a third insulating film, and a photoresist pattern on the semiconductor substrate;

상기 감광막패턴을 마스크로 상기 제 2절연막이 노출될때 까지 식각하여 제 3절연막패턴을 형성하는 공정과,Forming a third insulating film pattern by etching the photoresist pattern using a mask until the second insulating film is exposed;

상기 감광막패턴 및 제 3절연막패턴을 마스크로 제 1절연막의 일부가 노출될때 까지 식각하여 제 2절연막패턴과 제 1절연막패턴을 형성하는 공정과,Forming a second insulating film pattern and a first insulating film pattern by etching the photoresist pattern and the third insulating film pattern until a part of the first insulating film is exposed;

상기 감광막패턴을 제거한 후 게이트전극용 절연막을 형성하는 공정과,Removing the photoresist pattern and forming an insulating film for a gate electrode;

상기 구조의 전표면에 금속막을 형성하는 공정과,Forming a metal film on the entire surface of the structure;

상기 금속막을 CMP공정으로 상기 제 3절연막패턴이 노출될때 까지 연마하여 게이트절연막과 금속막패턴을 구비하는 게이트전극을 형성하는 공정을 포함하는 것을 특징으로 한다.And grinding the metal film by the CMP process until the third insulating film pattern is exposed to form a gate electrode having a gate insulating film and a metal film pattern.

이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1f 는 본 발명에 따른 반도체 소자의 제조공정도이다.1A to 1F are manufacturing process diagrams of a semiconductor device according to the present invention.

먼저, 반도체 기판(10) 상부에 얇은 두께의 제 1산화막(12)과 질화막(14), 제 2산화막(16)을 순차적으로 형성한 다음, 감광막패턴(18)을 순차적으로 형성한다.First, a thin first oxide film 12, a nitride film 14, and a second oxide film 16 are sequentially formed on the semiconductor substrate 10, and then the photoresist pattern 18 is sequentially formed.

이 때, 상기 질화막(14)은 상기 제 1산화막(12) 식각시 식각정지층으로 사용하며, 상기 감광막패턴(18)은 게이트전극으로 예정된 부위에 홈을 노출시키는 패턴을 형성한다.(도 1a 참조)In this case, the nitride film 14 is used as an etch stop layer when the first oxide film 12 is etched, and the photoresist pattern 18 forms a pattern for exposing a groove in a predetermined region as a gate electrode. Reference)

다음, 상기 감광막패턴(18)을 마스크로 상기 질화막(14)이 노출될때 까지 식각하여 제 2산화막(16)패턴을 형성한다.Next, the second oxide layer 16 pattern is formed by etching the photoresist layer pattern 18 using the mask until the nitride layer 14 is exposed.

이 때, 상기 제 2산화막(16) 식각시 상기 질화막(14)에 대한 식각선택비차를 이용하되 CHF3, C4F8, C3F8, C2F4, C2F6, C2HF5가스군에서 임의의 1개의 가스를 식각가스로 사용하여 식각공정을 진행한다.At this time, when etching the second oxide film 16, the etching selectivity difference with respect to the nitride film 14 is used, but CHF 3 , C 4 F 8 , C 3 F 8 , C 2 F 4 , C 2 F 6 , C 2 In the HF 5 gas group, an etching process is performed using any one gas as an etching gas.

또한, 상기 제 2산화막(16) 식각시 상기 질화막(14)에 대한 식각선택비차를 이용하여 CH3F, CO, Ar 가스군에서 임의의 1개 가스를 식각가스로 사용하여 식각공정을 진행할 수도 있다.In addition, when the second oxide layer 16 is etched, an etching process may be performed using any one gas from the CH 3 F, CO, and Ar gas group as an etching gas by using an etching selectivity difference with respect to the nitride layer 14. have.

그리고, 상기 CHF3, C4F8, C3F8, C2F4, C2F6, C2HF5가스들에 대한 공정 창(window)을 확장시키기 위하여 CH2F2, CH3F, C2H2, H2등의 수소를 포함하는 가스를 첨가하여 식각공정을 진행한다.And, in order to expand the process window for the CHF 3 , C 4 F 8 , C 3 F 8 , C 2 F 4 , C 2 F 6 , C 2 HF 5 gases CH 2 F 2 , CH 3 The etching process is performed by adding a gas containing hydrogen such as F, C 2 H 2 , and H 2 .

또한, 상기 CHF3, C4F8, C3F8, C2F4, C2F6, C2HF5가스에 Ar, He, Ne, Xe 가스를 혼합가스를 혼합하여 식각 공정에 사용할 수도 있다.In addition, the CHF 3 , C 4 F 8 , C 3 F 8 , C 2 F 4 , C 2 F 6 , C 2 HF 5 gas mixed with Ar, He, Ne, Xe gas to be used in the etching process It may be.

여기서, 상기 CH3F, CO, Ar 가스식각에 O2, Ar, He, N2가스를 혼합하여 사용하는 경우 상기 반도체 기판(10)의 전극에 바이어스 파워를 가하지 않고 등방성식각 공정을 진행할 수 있다.(도 1b 참조)Here, when O 2 , Ar, He, and N 2 gases are mixed with the CH 3 F, CO, and Ar gas, the isotropic etching process may be performed without applying bias power to the electrodes of the semiconductor substrate 10. (See FIG. 1B)

그 다음, 상기 감광막패턴(18) 및 제 2산화막(16)패턴을 마스크로 제 1산화막(12)의 일부분이 노출될때 까지 습식식각하여 질화막(14)패턴을 형성한다.Subsequently, the nitride layer 14 pattern is formed by wet etching the photoresist layer pattern 18 and the second oxide layer pattern 16 until a portion of the first oxide layer 12 is exposed.

이 때, 상기 질화막(14)패턴 식각시 반도체 기판(10)이 노출되지 않도록 플라즈마 손상을 최소화한다.(도 1c 참조)At this time, plasma damage is minimized so that the semiconductor substrate 10 is not exposed when the nitride layer 14 pattern is etched (see FIG. 1C).

다음, 상기 감광막패턴(18)을 제거한 후 열산화 공정을 실시하여 반도체 기판(10) 표면에 게이트산화막(20)을 형성한다.(도 1d 참조)Next, the photoresist pattern 18 is removed and then thermally oxidized to form a gate oxide film 20 on the surface of the semiconductor substrate 10 (see FIG. 1D).

그 다음, 상기 제 2산화막(16)패턴 측벽의 홈을 메우는 금속막(22)으로 Cu막을 형성한다.(도 1e 참조)Next, a Cu film is formed by the metal film 22 filling the grooves on the sidewalls of the second oxide film 16 pattern (see FIG. 1E).

다음, 상기 금속막(22)을 CMP 공정으로 상기 제 2산화막(16)패턴이 노출될때 까지 연마하여 질화막(14)패턴과 금속막(22)패턴을 구비하는 게이트전극을 형성한다.(도 1f 참조)Next, the metal film 22 is polished by the CMP process until the pattern of the second oxide film 16 is exposed to form a gate electrode having the nitride film 14 pattern and the metal film 22 pattern (FIG. 1F). Reference)

상기한 바와같이 본 발명에 따르면, 구리와 같은 금속막을 사용하여 게이트전극을 형성하는 경우 식각정지층으로 질화막을 사용함으로서 반도체 기판이 노출되는 것을 방지하여 플라즈마 손상을 최소화하고 후속공정을 용이하게 실시할 수 있으며, 폴리머 발생과 게이트산화막 손상을 방지할 수 있어 소자의 전기적 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, according to the present invention, when the gate electrode is formed using a metal film such as copper, the nitride substrate is used as the etch stop layer to prevent the semiconductor substrate from being exposed, thereby minimizing plasma damage and facilitating subsequent steps. In addition, it is possible to prevent polymer generation and damage to the gate oxide layer, thereby improving the electrical characteristics and reliability of the device.

Claims (6)

반도체 기판 상부에 제 1절연막과 제 2절연막, 제 3절연막, 감광막패턴을 순차적으로 형성하는 공정과,Sequentially forming a first insulating film, a second insulating film, a third insulating film, and a photoresist pattern on the semiconductor substrate; 상기 감광막패턴을 마스크로 상기 제 2절연막이 노출될때 까지 식각하여 제 3절연막패턴을 형성하는 공정과,Forming a third insulating film pattern by etching the photoresist pattern using a mask until the second insulating film is exposed; 상기 감광막패턴 및 제 3절연막패턴을 마스크로 제 1절연막의 일부가 노출될때 까지 식각하여 제 2절연막패턴과 제 1절연막패턴을 형성하는 공정과,Forming a second insulating film pattern and a first insulating film pattern by etching the photoresist pattern and the third insulating film pattern until a part of the first insulating film is exposed; 상기 감광막패턴을 제거한 후 게이트전극용 절연막을 형성하는 공정과,Removing the photoresist pattern and forming an insulating film for a gate electrode; 상기 구조의 전표면에 금속막을 형성하는 공정과,Forming a metal film on the entire surface of the structure; 상기 금속막을 CMP공정으로 상기 제 3절연막패턴이 노출될때 까지 연마하여 게이트절연막과 금속막패턴을 구비하는 게이트전극을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 소자의 제조방법And forming a gate electrode having a gate insulating film and a metal film pattern by polishing the metal film until the third insulating film pattern is exposed by a CMP process. 제 1 항에 있어서, 상기 제 1, 2, 3절연막은 각각 산화막, 질화막, 산화막으로 형성된 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the first, second, and third insulating films are formed of an oxide film, a nitride film, and an oxide film, respectively. 제 1 항에 있어서, 상기 제 3절연막 패턴시 상기 제 2절연막에 대하여 고식각선택비차를 갖는 식각가스로 CHF3, C4F8, C3F8, C2F4, C2F6, C2HF5가스군에서 임의의 1개 가스를 식각가스로 이용하거나 CH3F, CO, Ar 가스군에서 임의의 1개 가스를 식각가스로 이용하는 것을 특징으로 하는 반도체 소자의 제조방법.The etching gas of claim 1, wherein the etching gas has a high etching selectivity difference with respect to the second insulating layer when the third insulating layer pattern is formed. CH 3 , C 4 F 8 , C 3 F 8 , C 2 F 4 , C 2 F 6 A method for manufacturing a semiconductor device, comprising using any one gas as an etching gas in the C 2 HF 5 gas group or using any one gas as an etching gas in the CH 3 F, CO, Ar gas group. 제 1 항 또는 제 3 항에 있어서, 상기 CHF3, C4F8, C3F8, C2F4, C2F6, C2HF5가스식각들에 대한 공정 창을 확장시키기 위하여 CH2F2, CH3F, C2H2, H2등의 수소를 포함하는 가스를 첨가하여 식각공정을 진행하는 것을 특징으로 하는 반도체 소자의 제조방법.4. A method according to claim 1 or 3, in order to extend the process window for the CHF 3 , C 4 F 8 , C 3 F 8 , C 2 F 4 , C 2 F 6 , C 2 HF 5 gas etchings. 2 F 2 , CH 3 F, C 2 H 2 , H 2 , a method for manufacturing a semiconductor device characterized in that the etching process is performed by adding a gas containing hydrogen. 제 1 항 또는 제 4 항에 있어서, 상기 CHF3, C4F8, C3F8, C2F4, C2F6, C2HF5가스식각에 Ar, He, Ne, Xe 가스를 혼합하여 식각 공정을 진행하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1 or 4, wherein the CHF 3 , C 4 F 8 , C 3 F 8 , C 2 F 4 , C 2 F 6 , C 2 HF 5 gas etching to Ar, He, Ne, Xe gas A method of manufacturing a semiconductor device, characterized in that for performing the etching process by mixing. 제 1 항 또는 제 4 항에 있어서, 상기 CH3F, CO, Ar 가스식각에 O2, Ar, He, N2가스를 혼합하여 사용하는 경우 상기 반도체 기판의 전극에 바이어스 파워를 가하지 않고 등방성식각 공정을 진행하는 것을 특징으로 하는 반도체 소자의 제조방법.The isotropic etching method according to claim 1 or 4, wherein O 2 , Ar, He, and N 2 gases are mixed with the CH 3 F, CO, and Ar gas etch without applying bias power to the electrodes of the semiconductor substrate. Process for producing a semiconductor device, characterized in that the step of proceeding.
KR1019970081325A 1997-12-31 1997-12-31 Method for manufacturing semiconductor device using nitride layer as etch stop layer KR100447261B1 (en)

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