KR20000074480A - Method for forming gate electrode of semiconductor device - Google Patents
Method for forming gate electrode of semiconductor device Download PDFInfo
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- KR20000074480A KR20000074480A KR1019990018453A KR19990018453A KR20000074480A KR 20000074480 A KR20000074480 A KR 20000074480A KR 1019990018453 A KR1019990018453 A KR 1019990018453A KR 19990018453 A KR19990018453 A KR 19990018453A KR 20000074480 A KR20000074480 A KR 20000074480A
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- Prior art keywords
- titanium silicide
- film
- gate electrode
- layer
- etching
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 64
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 26
- 229920000642 polymer Polymers 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 6
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims abstract description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims abstract description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims description 33
- 239000000460 chlorine Substances 0.000 claims description 16
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 10
- 229910052801 chlorine Inorganic materials 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000000908 ammonium hydroxide Substances 0.000 claims description 3
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 239000000243 solution Substances 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000011259 mixed solution Substances 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract 2
- 238000007254 oxidation reaction Methods 0.000 abstract 2
- 235000011114 ammonium hydroxide Nutrition 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 description 15
- 229910052581 Si3N4 Inorganic materials 0.000 description 14
- 230000004888 barrier function Effects 0.000 description 12
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 9
- 229910008484 TiSi Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 229910019001 CoSi Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
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- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 다결정실리콘막 상에 티티늄 실리사이드(TiSiX)막을 적층한 폴리사이드(polycide) 구조의 게이트 전극을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a gate electrode having a polycide structure in which a titanium silicide (TiSi X ) film is laminated on a polysilicon film.
MOS 소자가 고집적화됨에 따라 게이트 전극의 저항 증가로 인한 워드 라인(word line)의 RC 지연(delay)등과 같은 문제가 발생한다. 이를 해결하기 위하여, 낮은 면저항(sheet resistance(Ω/□))을 갖는 게이트 전극 물질에 대한 개발이 요구되고 있다. 이러한 요구에 맞추어, 현재 텅스텐 실리사이드(WSi2), 티타늄 실리사이드(TiSi2), 코발트 실리사이드(CoSi2)등의 실리사이드막을 다결정실리콘막 상에 적층한 형태의 폴리사이드 구조에 대한 개발이 활발하게 이루어지고 있으며, 이중 텅스텐 실리사이드를 적층한 폴리사이드 구조의 게이트 전극은 MOS 소자에 이미 적용되고 있다.As the MOS device is highly integrated, problems such as RC delay of a word line due to an increase in resistance of the gate electrode occur. In order to solve this problem, development of a gate electrode material having a low sheet resistance (Ω / □) is required. In line with these demands, the development of a polycide structure in which silicide films such as tungsten silicide (WSi 2 ), titanium silicide (TiSi 2 ), and cobalt silicide (CoSi 2 ) are laminated on a polycrystalline silicon film has been actively developed. In addition, a gate electrode having a polyside structure in which double tungsten silicide is laminated is already applied to a MOS device.
디자인룰이 0.15㎛에서 0.18㎛ 이하의 소자에서는 워드 라인 저항에 의한 DRAM 소자의 동작 속도 저하가 주요한 문제로 부각되고 있는데, 텅스텐 실리사이드막을 적층한 폴리사이드 구조의 워드 라인을 채용한 디자인룰이 0.15㎛ 이하 소자의 경우, 면저항이 15Ω/□ 정도로, 256K 블록(block)에서 하나의 워드 라인의 저항값은 36KΩ 정도가 되어 매우 높은 값을 갖는다.In devices with a design rule of 0.15 µm to 0.18 µm or less, a major problem is that the DRAM device has a lower operation speed due to word line resistance. In the case of the following elements, the sheet resistance is about 15 mA / square, and the resistance value of one word line in a 256K block is about 36 KΩ, which is very high.
따라서, 워드 라인의 저항값을 낮추기 위하여, 티타늄 실리사이드(TiSiX)막을 채용한 폴리사이드 구조의 워드 라인을 디자인룰 0.15㎛ 이하의 소자에 적용하려는 노력이 시도되고 있다. 이 경우 티타늄 실리사이드(TiSiX)막과 그 상부에 형성되는 하드 마스크(hard mask)와의 반응 및 티타늄 실리사이드막과 그 하부에 형성되는 다결정실리콘막과의 반응을 억제하기 위해 티타늄 실리콘 나이트라이드(TiSiN) 장벽막(barrier film)을 형성하여 원하는 면저항을 얻을 수 있다. 그러나, 건식식각 관점에서는 티타늄 실리사이드(TiSiX)막 식각 시 다량의 폴리머(polymer)가 티타늄 실리사이드막 측벽에 부착되어 다음의 다결정실리콘막의 식각시 식각 프로파일 확보를 곤란하게 한다.Therefore, in order to lower the resistance value of the word line, efforts have been made to apply a word line having a polyside structure including a titanium silicide (TiSi X ) film to devices having a design rule of 0.15 μm or less. In this case, in order to suppress the reaction between the titanium silicide (TiSi X ) film and the hard mask formed thereon and the reaction between the titanium silicide film and the polysilicon film formed below the titanium silicon nitride (TiSiN) By forming a barrier film, a desired sheet resistance can be obtained. However, in terms of dry etching, a large amount of polymer is attached to the sidewalls of the titanium silicide layer during the etching of the titanium silicide (TiSi X ) layer, thereby making it difficult to secure an etching profile during the etching of the next polysilicon layer.
도 1a 및 도 1b는 티타늄 실리사이드막을 채용한 폴리사이드 구조의 게이트 전극을 형성하는데 있어서 종래의 식각방법을 설명하기 위해 도시한 단면도들이다.1A and 1B are cross-sectional views illustrating a conventional etching method in forming a gate electrode having a polyside structure using a titanium silicide film.
반도체 기판(10) 표면에 게이트 산화막(12)를 형성한 후, 다결정실리콘막(14)과 제1 티타늄 실리콘 나이트라이드막(16)과, 티타늄 실리사이드막(18)과 제2 티타늄 실리콘 나이트라이드막(20)을 차례대로 적층한다. 이후, 상기 제2 티타늄 실리콘 나이트라이드막(20) 상에 실리콘 나이트라이드로 된 제1 하드 마스크와 산화물로 된 제2 하드 마스크를 적층한 후, 이를 포토레지스트 패턴(미도시)을 마스크로 하여 식각함으로써 각각 제1 하드 마스크 패턴(22) 및 제2 하드 마스크 패턴(24)을 형성한다. 이어서, 상기 제2 하드 마스크 패턴(도 1a의 24) 및 제1 하드 마스크 패턴(22)을 마스크로 하여 제2 티타늄 실리콘 나이트라이드막(20), 티타늄 실리사이드막(18) 및 제1 티타늄 실리콘 나이트라이드막(16)을 차례대로 식각한다. 이때, 상기 티타늄 실리사이드막 식각 시, 티타늄 실리사이드는 반응성이 매우 뛰어난 물질이기 때문에 식각 가스와 반응을 하여 비휘발성 폴리머를 형성하고 이러한 폴리머는 티타늄 실리사이드막 측벽에 부착되어 폴리머 스페이서(26)를 형성하기 쉽다 (도 1a).After the gate oxide film 12 is formed on the surface of the semiconductor substrate 10, the polysilicon film 14, the first titanium silicon nitride film 16, the titanium silicide film 18, and the second titanium silicon nitride film (20) is laminated in order. Subsequently, a first hard mask made of silicon nitride and a second hard mask made of oxide are stacked on the second titanium silicon nitride film 20, and then etched using a photoresist pattern (not shown) as a mask. Thus, the first hard mask pattern 22 and the second hard mask pattern 24 are formed, respectively. Subsequently, a second titanium silicon nitride film 20, a titanium silicide film 18, and a first titanium silicon knight are formed using the second hard mask pattern 24 (FIG. 1A) and the first hard mask pattern 22 as a mask. The ride film 16 is sequentially etched. In this case, when the titanium silicide layer is etched, since the titanium silicide is a highly reactive material, it reacts with an etching gas to form a nonvolatile polymer, and the polymer is easily attached to the titanium silicide layer sidewalls to form the polymer spacer 26. (FIG. 1A).
이러한, 폴리머 스페이서(26)는 이후 다결정실리콘막(14) 식각 시, 티타늄 실리사이드막과 함께 마스크 역할을 하기 때문에 최종적으로 형성되는 다결정실리콘막(14)의 크리티컬 디멘젼(Critical Dimension; CD)을 확장시켜, 도 1b에 도시된 바와 같이, 티타늄 실리사이드막(18)과 다결정실리콘막(14) 계면에 뚜렷하게 턱(step)(28)을 형성한다.Since the polymer spacer 26 subsequently serves as a mask along with the titanium silicide layer when the polysilicon layer 14 is etched, the critical dimension (CD) of the finally formed polycrystalline silicon layer 14 may be expanded. As shown in FIG. 1B, a step 28 is distinctly formed at the interface between the titanium silicide film 18 and the polysilicon film 14.
티타늄 실리사이드막 식각 시 형성되는 폴리머 스페이서를 LDD (Lightly Doped Drain) 반도체 소자 제조 방법에 응용하는 경우도 있지만, 디자인룰이 0.15㎛ 이하의 초집적 반도체 소자를 제조하는데 있어서는 집적도를 저하시키는 요인으로 작용한다. 또한, 상기한 바와 같은 턱(28)이 형성된 상태에서 이후 게이트 스페이서(30)를 형성하게 되면 상기 턱(28) 부분의 게이트 스페이서 폭(L1)이 다른 부분보다 얇아 충분한 절연효과를 얻을 수 없다는 단점이 있다.Although the polymer spacer formed during the etching of the titanium silicide layer may be applied to a method of manufacturing a lightly doped drain (LDD) semiconductor device, the design rule may reduce the degree of integration when manufacturing a super integrated semiconductor device of 0.15 μm or less. . In addition, when the gate spacer 30 is formed later in the state in which the tuck 28 is formed as described above, the gate spacer width L1 of the tuck 28 is thinner than other portions, and thus, sufficient insulation effect cannot be obtained. There is this.
본 발명의 목적은 티타늄 실리사이드막과 다결정실리콘막 사이에 형성되던 턱 발생을 방지할 수 있는 반도체 소자의 게이트 전극 형성 방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a gate electrode of a semiconductor device capable of preventing occurrence of tuck formed between a titanium silicide film and a polysilicon film.
도 1a 및 도 1b는 티타늄 실리사이드막을 채용한 폴리사이드 구조의 게이트를 형성하는데 있어서 종래의 식각방법을 설명하기 위해 도시한 단면도들이다.1A and 1B are cross-sectional views illustrating a conventional etching method in forming a gate of a polyside structure employing a titanium silicide film.
도 2a 내지 도 2c는 티타늄 실리사이드막을 채용한 폴리사이드 구조의 게이트 전극을 형성하는데 있어서 본 발명의 일 실시에에 의한 식각방법을 설명하기 위해 도시한 단면도들이다.2A to 2C are cross-sectional views illustrating an etching method according to an embodiment of the present invention in forming a gate electrode having a polyside structure using a titanium silicide layer.
도 3a 및 도 3b는 티타늄 실리사이드막과 다결정실리콘막을 식각하는 여러 가지 방법에 따른 크리티컬 디멘젼의 차이를 보여주기 위한 그래프들로써, 도 3a는 셀 영역에서의 결과를, 도 3b는 센서 엠플리파이어(sense amplifier) 영역에서의 결과를 나타낸다.3A and 3B are graphs illustrating differences in critical dimensions according to various methods of etching a titanium silicide film and a polysilicon film. FIG. 3A shows results in a cell region, and FIG. 3B shows a sensor amplifier. Results in the amplifier area are shown.
상기 목적을 달성하기 위한, 본 발명에 의한 반도체 소자의 게이트 전극 형성방법은, 반도체 기판 표면에 게이트 산화막을 형성하는 공정과, 상기 게이트 산화막 상에 다결정실리콘막과 티타늄 실리사이드막을 차례대로 적층하는 공정과, 상기 티타늄 실리사이드막 상에 게이트 전극 형성을 위한 하드 마스크를 형성하는 공정과, 상기 하드 마스크를 마스크한 이방성식각으로 상기 티타늄 실리사이드막을 식각하는 공정과, 1000:1의 HF와 수산화 암모늄(NH4OH), 과산화수소(H2O2) 및 물(H2O)을 1:4:20으로 혼합한 35℃ ∼ 45℃ 정도의 저온 용액을 혼합한 용액으로 티타늄 실리사이드막 식각 시 발생한 폴리머를 스트립하는 공정과, 다결정실리콘막을 식각하는 공정을 구비하는 것을 특징으로 한다.In order to achieve the above object, a method of forming a gate electrode of a semiconductor device according to the present invention includes the steps of forming a gate oxide film on the surface of a semiconductor substrate, and laminating a polysilicon film and a titanium silicide film on the gate oxide film in sequence; Forming a hard mask for forming a gate electrode on the titanium silicide layer; etching the titanium silicide layer by anisotropic etching the mask on the hard mask; and 1000: 1 HF and ammonium hydroxide (NH 4 OH). ), A process of stripping a polymer generated during etching of a titanium silicide layer with a mixture of hydrogen peroxide (H 2 O 2 ) and water (H 2 O) in a low temperature solution of about 35 ° C. to 45 ° C. mixed at 1: 4: 20. And etching the polycrystalline silicon film.
상기 티타늄 실리사이드막은 염소(Cl2)와 질소(N2) 가스를 사용하여 식각하고, 상기 다결정실리콘막은 염소(Cl2)와 산소(O2) 가스를 사용하여 식각한다.The titanium silicide layer is etched using chlorine (Cl 2 ) and nitrogen (N 2 ) gas, and the polysilicon layer is etched using chlorine (Cl 2 ) and oxygen (O 2 ) gas.
따라서, 본 발명에 의하면, 티타늄 실리사이드막과 다결정실리콘막이 적층된 형태의 게이트 전극의 측벽이 수직 프로파일을 갖도록 할 수 있다.Therefore, according to the present invention, the sidewalls of the gate electrode in which the titanium silicide film and the polycrystalline silicon film are stacked can have a vertical profile.
이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세히 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해서 제공되어지는 것이다. 따라서, 도면에서의 요소의 형상 등은 보다 명확한 설명을 강조하기 위해서 과장되어진 것이며, 도면 상에서 동일한 부호로 표시된 요소는 동일한 요소를 의미한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements.
도 2a 내지 도 2c는 티타늄 실리사이드막을 채용한 폴리사이드 구조의 게이트 전극을 형성하는데 있어서 본 발명의 일 실시에에 의한 식각방법을 설명하기 위해 도시한 단면도들이다.2A to 2C are cross-sectional views illustrating an etching method according to an embodiment of the present invention in forming a gate electrode having a polyside structure using a titanium silicide layer.
먼저, 도 2a를 참조하면, 반도체 기판(30) 표면에 산화막을 성장시켜 게이트 산화막(32)을 형성한 후, 상기 게이트 산화막(32) 상에 다결정실리콘막(34), 티타늄 실리콘 나이트라이드로 된 제1 장벽막(36), 티타늄 실리사이드(TiSiX)(38) 및 티타늄 실리콘 나이트라이드로 된 제2 장벽막(40)을 차례대로 적층한다. 이후, 상기 제2 장벽막(40) 상에 실리콘 나이트라이드막과 산화막을 차례대로 적층한 후 포토레지스트 패턴(미도시)을 마스크로 이용한 식각공정으로 상기 실리콘 나이트라이드막과 산화막을 패터닝함으로써 상기 실리콘 나이트라이드막으로 된 제1 하드 마스크(42)와 상기 산화막으로 된 제2 하드 마스크(44)를 형성한다.First, referring to FIG. 2A, an oxide film is grown on a surface of a semiconductor substrate 30 to form a gate oxide film 32, and then a polysilicon film 34 and titanium silicon nitride are formed on the gate oxide film 32. The first barrier film 36, the titanium silicide (TiSi X ) 38, and the second barrier film 40 made of titanium silicon nitride are sequentially stacked. Thereafter, the silicon nitride layer and the oxide layer are sequentially stacked on the second barrier layer 40, and the silicon nitride layer and the oxide layer are patterned by an etching process using a photoresist pattern (not shown) as a mask. A first hard mask 42 made of a nitride film and a second hard mask 44 made of an oxide film are formed.
계속해서, 상기 제1 및 제2 하드 마스크(42 및 44)을 마스크로하여 그 하부에 적층되어 있는 제2 장벽막(40), 티타늄 실리사이드막(38) 및 제1 장벽막(36)을 차례대로 식각하여 티타늄 실리사이드 패턴(50)을 형성한다. 이때, 상기 티타늄 실리사이드 패턴(50)을 형성하기 위한 식각 시, 식각 가스와 티타늄 실리사이드가 반응하여 비휘발성의 폴리머를 생성하여 상기 티타늄 실리사이드 패턴(50)의 측벽에 폴리머 스페이서(46)를 형성한다.Subsequently, the second barrier film 40, the titanium silicide film 38, and the first barrier film 36, which are stacked below the first and second hard masks 42 and 44, are used as a mask. Etching is performed to form the titanium silicide pattern 50. At this time, during etching to form the titanium silicide pattern 50, an etching gas and titanium silicide react to form a nonvolatile polymer to form a polymer spacer 46 on sidewalls of the titanium silicide pattern 50.
상기 폴리머 스페이서(46)가 형성되어 있는 상태에서 다결정실리콘막(34)을 식각하면 식각된 다결정실리콘막 패턴은 티타늄 실리사이드 패턴(50)의 크리티컬 디멘젼에 상기 폴리머 스페이서(46)의 폭을 합한 정도의 크기로 형성되어 원하는 크기보다 더 확장된 형태로 형성된다.When the polysilicon layer 34 is etched while the polymer spacers 46 are formed, the etched polysilicon layer pattern is formed by adding the width of the polymer spacers 46 to the critical dimensions of the titanium silicide pattern 50. It is formed in size and formed in a form that extends more than desired size.
따라서, 본 발명에서는 상기 다결정실리콘막 식각시 원하는 크기로 크리티컬 디멘젼을 확보하고, 최종적인 게이트 전극의 프로파일을 원하는 모양 (티타늄 실리사이드막과 다결정실리콘막 사이에 턱이 발생하지 않은 형태)으로 얻기 위해, 상기 티타늄 실리사이드 패턴(50) 형성 후 습식 스트립(wet strip)으로 폴리머 스페이서를 제거한다. 이하, 언급한 습식 스트립에 대해 도 2b를 참조하여 설명한다.Therefore, in the present invention, in order to secure a critical dimension at a desired size when the polysilicon film is etched, and to obtain a final gate electrode profile in a desired shape (a form in which no jaw occurs between the titanium silicide film and the polysilicon film), After the titanium silicide pattern 50 is formed, the polymer spacer is removed by a wet strip. Hereinafter, the wet strip mentioned will be described with reference to FIG. 2B.
도 2b를 참조하면, 상기 티타늄 실리사이드 패턴(50) 형성 후, 1000:1의 HF용액과 35℃ ∼ 45℃의 저온 SC-1 (수산화암모늄(NH4OH) : 과산화수소(H2O2): 물(H2O) = 1 : 4 : 20) 용액을 혼합한 용액에 기판을 담구는 습식 스트립 공정으로 상기 폴리머 스페이서(도 2a의 46)를 제거한다.Referring to FIG. 2B, after the titanium silicide pattern 50 is formed, a 1000: 1 HF solution and 35 ° C. to 45 ° C. of low temperature SC-1 (ammonium hydroxide (NH 4 OH): hydrogen peroxide (H 2 O 2 ): The polymer spacer (46 in FIG. 2A) is removed by a wet strip process of immersing the substrate in a solution of water (H 2 O) = 1: 4: 20) solution.
상기 폴리머 스페이서는 습식 스트립 뿐만아니라 플라즈마 식각으로도 제거할 수 있으나, 플라즈마 식각의 경우, 하드 마스크가 부식되거나 하부의 다결정실리콘막이 손상될 수 있으므로 습식 스트립 공정을 행하는 것이 바람직하다. 또한, 습식 스트립에 있어서, 폴리머 스트립에 우수한 성능을 나타내는 황산(H2SO4)을 사용할 수 있으나, 이 경우 황산 용액에 의해 제1 하드 마스크(40)이 제2 장벽막(38) 상에서 뜨는 리프팅(lifting) 현상이 발생하였다.The polymer spacer may be removed not only by the wet strip but also by plasma etching. However, in the case of plasma etching, it is preferable to perform the wet strip process because the hard mask may be corroded or the underlying polysilicon layer may be damaged. In addition, in the wet strip, sulfuric acid (H 2 SO 4 ), which shows excellent performance in the polymer strip, may be used, in which case the lifting of the first hard mask 40 floating on the second barrier film 38 by the sulfuric acid solution. (lifting) phenomenon occurred.
따라서, 본 발명의 일 실시예에서는 상기와 같이 1000:1의 HF 용액과 35℃ ∼ 45℃의 저온 SC-1(NH4OH:H2O2:H2O = 1:4:20) 용액을 혼합한 용액을 사용하여 습식 스트립을 행한다. 이때, 상기 SC-1 용액을 고온으로 할 경우, 티타늄 실리사이드의 손실이 많고, 오히려 티타늄 실리사이드막과 다결정실리콘막 사이의 턱 발생을 가속화할 수 있다.Therefore, in one embodiment of the present invention as described above 1000: 1 HF solution and 35 ℃ ~ 45 ℃ low temperature SC-1 (NH 4 OH: H 2 O 2 : H 2 O = 1: 4: 20) solution Wet the strip using the mixed solution. At this time, when the SC-1 solution is used at a high temperature, the loss of titanium silicide is large, and it is possible to accelerate the generation of the jaw between the titanium silicide film and the polysilicon film.
도 2c을 참조하면, 상기 폴리머 스페이서를 제거한 후, 하드 마스크 및 티타늄 실리사이드 패턴(50)을 마스크로 하여 다결정실리콘막(34)을 패터닝함으로써 다결정실리콘막(34), 제1 장벽막(36) 및 티타늄 실리사이드막(38)으로 구성된 게이트 전극을 완성한다. 이후, 예컨대 실리콘 나이트라이드와 같은 물질을 도포하고 이방성식각하여 상기 게이트 전극 측벽에 측벽 스페이서(48)을 형성한다.Referring to FIG. 2C, after removing the polymer spacer, the polysilicon layer 34, the first barrier layer 36, and the polysilicon layer 34 are patterned by using the hard mask and the titanium silicide pattern 50 as a mask. The gate electrode composed of the titanium silicide film 38 is completed. Thereafter, a material such as silicon nitride is applied and anisotropically etched to form sidewall spacers 48 on the gate electrode sidewalls.
도 2c의 "L2"를 참조하면, 티타늄 실리사이드막(38)과 다결정실리콘막(34) 사이에 턱이 형성되어 있지 않으므로, 이부분에서 측벽 스페이서의 폭이 얇아지던 종래의 문제점이 발생하지 않는다는 것을 알 수 있다.Referring to " L2 " in FIG. 2C, since no tuck is formed between the titanium silicide film 38 and the polysilicon film 34, the conventional problem that the width of the sidewall spacers becomes thinner at this portion does not occur. Able to know.
본 발명에 의하면, 티타늄 실리사이드 패턴(50)의 크리티컬 디멘젼(CD)은 제1 하드 마스크(42)의 크리티컬 디멘젼과 거의 차이가 없으며, 패터닝된 다결정실리콘막(34)의 크기 또한 제1 하드 마스크(42)의 크리티컬 디멘젼과 거의 차이가 없도록 게이트 전극을 형성할 수 있다는 것을 알 수 있다. 즉, 본 발명에 의한 게이트 전극은 티타늄 실리사이드막(38)과 다결정실리콘막(34) 사이에 턱 발생하지 않은 수직 프로파일(vertical profile)을 갖는다는 것을 알 수 있다. 본 발명에 의하면, 제1 하드 마스크(42) (또는, 제2 하드 마스크(44)) 대비 패터닝된 다결정실리콘막의 크리티컬 디멘젼 차이를 30nm 이내로 관리할 수 있다.According to the present invention, the critical dimension (CD) of the titanium silicide pattern 50 is hardly different from the critical dimension of the first hard mask 42, and the size of the patterned polysilicon film 34 is also the first hard mask ( It can be seen that the gate electrode can be formed so that there is almost no difference from the critical dimension of 42). That is, it can be seen that the gate electrode according to the present invention has a vertical profile that does not occur between the titanium silicide film 38 and the polysilicon film 34. According to the present invention, the critical dimension difference of the patterned polysilicon film compared to the first hard mask 42 (or the second hard mask 44) can be managed within 30 nm.
도 3a 및 도 3b는 티타늄 실리사이드막과 다결정실리콘막을 식각하는 여러 가지 방법에 따른 크리티컬 디멘젼의 차이를 보여주기 위한 그래프들로써, 도 3a는 셀 영역에서의 결과를, 도 3b는 센서 엠플리파이어(sense amplifier) 영역에서의 결과를 나타낸다.3A and 3B are graphs illustrating differences in critical dimensions according to various methods of etching a titanium silicide film and a polysilicon film. FIG. 3A shows results in a cell region, and FIG. 3B shows a sensor amplifier. Results in the amplifier area are shown.
도 3a 및 도 3b에서 ①선은 염소(Cl2)와 질소(N2)를 사용하여 티타늄 실리사이드막과 다결정실리콘막을 하나의 스텝으로 식각한 경우를, ②선은 염소(Cl2)와 산소(O2)를 사용하여 티타늄 실리사이드막과 다결정실리콘막을 하나의 스텝으로 식각한 경우를, ③선은 염소와 질소를 사용하여 티타늄 실리사이드막을 식각한 후, 염소와 산소를 사용하여 다결정실리콘막을 식각하는 두 개의 스텝으로 공정을 진행한 경우를, ④선은 염소와 질소를 사용하여 티타늄 실리사이드막을 식각한 후, 습식 스트립으로 폴리머 스페이서를 제거하고, 이후 염소와 산소로 다결정실리콘막을 식각하는 세 개의 스텝으로 공정을 진행한 경우를 나타낸다.In FIGS. 3A and 3B, the line ① represents a case where the titanium silicide film and the polysilicon film are etched in one step using chlorine (Cl 2 ) and nitrogen (N 2 ), and the line ② represents chlorine (Cl 2 ) and oxygen ( In the case where the titanium silicide film and the polysilicon film were etched in one step using O 2 ), the line ③ is used to etch the titanium silicide film using chlorine and nitrogen, and then the polysilicon film is etched using chlorine and oxygen. In the case where the process is performed in four steps, line ④ is a three-step process of etching the titanium silicide film using chlorine and nitrogen, removing the polymer spacer with a wet strip, and then etching the polysilicon film with chlorine and oxygen. Indicates the case where the process proceeds.
시료채취 정도에 따라 하드 마스크의 초기 크리티컬 디멘젼이 다르지만, 상기 네 개의 공정조건 중 본 발명의 경우 (④선, 즉 티타늄 실리사이드막 식각 후 습식 스트립을 추가하는 공정)) 셀 영역 및 센스 엠플리파이어 영역 모두에서 크리티컬 디멘젼의 차이가 가장 적음을 알 수 있다. 이때, 상기 크리티컬 디멘젼은 실리콘 나이트라이드(SiN)로 된 하드 마스크와, 티타늄 실리사이드막(TiSiX)막과, 다결정실리콘막 각각에서 측정한 것이다.The initial critical dimension of the hard mask differs depending on the degree of sampling, but in the case of the present invention among the four process conditions (4), that is, a process of adding a wet strip after etching the titanium silicide layer), the cell region and the sense amplifier region. It can be seen that the difference in critical dimensions is the smallest in all. In this case, the critical dimension is measured by a hard mask made of silicon nitride (SiN), a titanium silicide film (TiSi X ) film, and a polycrystalline silicon film, respectively.
본 발명의 일 실시예에서는 티타늄 실리사이드(TiSiX)막을 형성한 경우만을 예를 들었으나, 텅스텐 실리사이드(WSiX), 코발트 실리사이드(CoSiX)로 폴리사이드 구조의 게이트 전극을 형성하는 경우에도 동일하게 상기한 습식 스트립 공정을 적용할 수 있다. 또한, 본 발명의 일 실시예에서는 장벽막으로 티타늄 실리콘 나이트라이드(TiSiN)만을 언급하였으나, 상기 장벽막을 티타늄 나이트라이드(TiN), 티타늄 알루미늄 나이트라이드(TiAlN) 등 중 하나로 형성할 수도 있음은 물론이다. 더하여, 본 발명의 일 실시예에서는 다결정실리콘막과 티타늄 실리사이드막 사이 및 티타늄 실리사이드막과 제1 하드 마스크 사이에 장벽막을 형성한 경우만을 설명하였으나, 이러한 장벽막이 형성되지 않은 상태의 폴리사이드 구조의 게이트 전극을 형성할 때에도 상기 습식 스트립 공정을 적용할 수 있음은 물론이다. 마지막으로, 본 발명의 일 실시예서는 제1 및 제2 하드 마스크를 사용하였으나, 이러한 하드 마스크의 적용없이 포토레지스트 패턴만으로, 또는 하나의 하드 마스크만을 형성한 상태에서 본 발명의 공정을 진행하는 것도 가능하다.In the exemplary embodiment of the present invention, only a case of forming a titanium silicide (TiSi X ) film is given, but the same is also true of forming a gate electrode having a polyside structure using tungsten silicide (WSi X ) and cobalt silicide (CoSi X ). The wet strip process described above can be applied. In addition, in the exemplary embodiment of the present invention, only titanium silicon nitride (TiSiN) is mentioned as the barrier film, but the barrier film may be formed of one of titanium nitride (TiN), titanium aluminum nitride (TiAlN), and the like. . In addition, in the exemplary embodiment of the present invention, only the case where the barrier film is formed between the polysilicon film and the titanium silicide film and between the titanium silicide film and the first hard mask has been described, but the gate of the polyside structure without such a barrier film is formed. Of course, the wet strip process can be applied when forming the electrode. Finally, although one embodiment of the present invention uses the first and second hard masks, the process of the present invention may be performed using only a photoresist pattern or only one hard mask without applying such a hard mask. It is possible.
본 발명에 의한 반도체 소자의 게이트 전극 형성 방법에 의하면, 티타늄 실리사이드막과 다결정실리콘막 사이에 턱이 발생하는 것을 방지할 수 있으므로 수직 프로파일을 갖는 폴리사이드 구조의 게이트 전극을 형성할 수 있다.According to the method for forming a gate electrode of the semiconductor device according to the present invention, it is possible to prevent the occurrence of tuck between the titanium silicide film and the polysilicon film, so that a gate electrode having a polyside structure having a vertical profile can be formed.
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KR100499628B1 (en) * | 2002-06-29 | 2005-07-05 | 주식회사 하이닉스반도체 | Cleaning Method of Semiconductor Device |
KR100734669B1 (en) * | 2003-08-08 | 2007-07-02 | 동부일렉트로닉스 주식회사 | Method and apparatus for manufacturing semiconductor device |
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KR100499628B1 (en) * | 2002-06-29 | 2005-07-05 | 주식회사 하이닉스반도체 | Cleaning Method of Semiconductor Device |
KR100734669B1 (en) * | 2003-08-08 | 2007-07-02 | 동부일렉트로닉스 주식회사 | Method and apparatus for manufacturing semiconductor device |
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