KR20010030433A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE: To provide a method of manufacturing a semiconductor device adapted for applications such as devices, where a junction leakage current at storage nodes is required to be reduced or whose device areas are required to be reduced. CONSTITUTION: A second insulating film 15 is formed above the surface of a semiconductor substrate 1, and a third insulating film 16 is formed on the film 15 as an interlayer film. Furthermore, a contact hole 7 is formed in a manner so as to pass through the film 16 and reaching the surface of the film 15. A fourth insulating film is formed on the film 16 having the hole 7 formed therein. The fourth insulating film and the film 15 are etched, using an anisotropic etching method to form a sidewall 9 made of the fourth insulating film on the side surface of the hole 7, and to expose the surface of the substrate 1 to the hole 7.

Description

Manufacturing method of semiconductor device

The present invention relates to a method for manufacturing a semiconductor device in which contact holes are formed in an interlayer insulating film.

In the semiconductor device manufacturing technology, the contact hole forming technology plays a very important role. 3 and 4 are cross-sectional views illustrating a semiconductor device manufacturing process for explaining the first and second conventional techniques.

3 shows a basic contact hole of a semiconductor device. A gate oxide film 2, an interlayer insulating film 17, a gate electrode 3, and a wiring 18 are formed on the semiconductor substrate 1, and a contact hole 7 penetrates the interlayer insulating film 17 to form a semiconductor substrate. It is formed to reach the surface of (1).

4 shows an example of a self-aligned contact hole in which the contact hole 7 is opened in a self-aligned manner with respect to the gate electrode 3. Hereinafter, a method of manufacturing a contact hole will be described with reference to the drawings.

First, a gate oxide film 2 is formed on the semiconductor substrate 1. Next, a polycrystalline silicon and a silicon nitride film having a predetermined resistance value are sequentially formed by doping predetermined impurities at a predetermined concentration for each film.

Subsequently, the silicon nitride film and the polycrystalline silicon film are sequentially etched back using a known photoresist method to form a gate electrode structure 30 composed of the gate electrode 3 and the silicon nitride film 4 formed thereon.

Next, a silicon nitride film is formed on the front surface, and the front surface is etched back by an anisotropic dry etching to form sidewalls 11 made of a silicon nitride film only on the side surface of the gate electrode structure 30. As a result, the gate electrode 3 is covered with the upper silicon nitride film 4 and the sidewalls 11 of the silicon nitride film. In this case, for example, a silicon oxide film may be formed on the gate electrode structure 30 as an etch back stopper in the sidewall forming process made of the silicon nitride film.

Next, an interlayer insulating film 17 is formed over the entire surface using a silicon oxide film made of a material such as BPSG. In the meantime, the wiring 18 forming step is inserted. For the formation of the wiring 18, for example, an impurity is doped to a predetermined concentration to form a polysilicon film having a predetermined resistance value, and the film is patterned by a known photoresist method. Next, the interlayer insulating film 17 is formed again on the wiring 18.

Next, the contact hole 7 is formed using the photoresist method. The etching at the time of forming the contact hole is performed under the condition that the silicon oxide film can be selectively etched with respect to the silicon nitride film. As etching conditions, for example, at a substrate temperature of 100 ° C., a pressure of 60 mTorr, and an RF power of 800 W, a Japanese-made RIE etching apparatus using a RIE etching apparatus that injects a CHF ₃ gas at a flow rate of 25 sccm and a CO gas at a flow rate of 75 sccm is used. Conditions as disclosed in Japanese Patent Laid-Open No. 6-132252 may be mentioned.

However, after the formation of the contact holes, damage to the surface of the substrate exposed to the etch atmosphere, for example, defects caused by penetration of ions in the etch atmosphere, removal or recovery from deposits, metal contamination, and the like, or treatment for removal of the native oxide film Etc. is a common system.

As the surface treatment, for example, a wet treatment using a mixed solution of hydrogen peroxide with one selected from ammonia, hydrochloric acid and sulfuric acid (hereinafter referred to as cleaning solution) is performed on the surface of the semiconductor substrate. Alternatively, the damage layer is removed by slightly thermally oxidizing the exposed substrate surface, and then removing the oxide film formed using a buffered hydrofluoric acid solution diluted to a concentration range of 1:30 to 1: 100. .

To remove the natural oxide film, a hydrofluoric acid solution diluted in the range of 1:30 to 1: 400, a buffered hydrofluoric acid solution that is a mixed solution of hydrogen fluoride and ammonium fluoride, and the like may be used.

According to the first or second conventional technology, since the side of the contact hole has an exposed silicon oxide film such as BPSG serving as an interlayer insulating film, when a wet treatment using a cleaning solution or a buffered hydrofluoric acid solution is performed, In addition, the side surface of the contact hole is also etched to cause a problem that the diameter of the contact hole is expanded.

In addition, since no oxidizing species is contained in the side of the contact hole, the gate electrode or the wiring in the vicinity of the contact hole in the interlayer insulating film is also oxidized, so that defects such as reduction in size and abnormal oxidation are eliminated. Occurs.

In the case where the distance to the wiring is large, the oxidation reaction is diffusion controlled so that the oxidation hardly occurs. However, in recent devices such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), the margin for the distance between the contact hole and the wiring is smaller than 0.1 mu m, so the above-described effects are no longer ignored. In many cases it can not be.

In this case, the silicon oxide film such as BPSG on the side of the contact hole exposed to the cleaning solution or the buffered hydrofluoric acid solution is also etched, thereby causing an additional problem of increasing the diameter of the contact hole.

According to the third and fourth conventional techniques described in Japanese Patent Laid-Open Nos. 1-208831 and 3-181135, the silicon nitride film is formed on the side of the contact hole, thereby improving the above-mentioned problems.

The contact holes disclosed in these documents have an object to obtain a certain effect by forming a silicon nitride film on the side of the contact hole. Considering the relationship with the present invention, since the side of the contact hole is protected by the installation of the silicon nitride film according to the technique mentioned here, these prior arts expand the diameter of the contact hole by the cleaning solution or the buffered hydrofluoric acid solution. And problems of oxidation of unwanted portions during the oxidation treatment are improved.

However, even in the technique disclosed in Japanese Patent Laid-Open No. Hei 1-208831 or Hei 3-181135, the following problems remain unresolved.

That is, in the third and fourth conventional techniques, as shown in Fig. 5A, first, by using a known photoresist method, a BPSG film or the like provided as the interlayer insulating film 17 is used as the photoresist 19 as a mask. By anisotropic dry etching, a contact hole 7 reaching the semiconductor substrate 1 is formed. Next, a silicon nitride film is formed on the front surface and the back surface is etched back using anisotropic etching, so that the sidewall 9 made of the silicon nitride film is formed only on the side of the contact hole, as shown in FIG. 5B.

In this process, the bottom of the contact hole is exposed a total of two times. That is, first, as shown in FIG. 5A, when etching the interlayer insulating film 17 for forming a contact hole, and next, as shown in FIG. 5B, for forming the sidewall 9 made of silicon nitride film. During etching.

In general, in the case of etching a film, etching is performed for a time exceeding the time required for etching to a desired film thickness in consideration of the uniformity of the resultant film. This is commonly referred to as overetching.

Moreover, in recent years, the thickness reduction of the interlayer insulating film is not as severe as that in which a reduction in the contact hole diameter is required. As a result, the aspect ratio of the contact hole tends to increase.

In etching used to form such contact holes, the energy given to etching ion species is increasing to enhance anisotropy. Therefore, when the surface of the substrate is exposed to the etching atmosphere, damage caused by such ionic species or damage caused by movement of contaminants derived from other places by the ionic species occurs.

In this case, the total etching time including the overetching time is set, for example, approximately 1.5 times as long as the time required for the desired film thickness, so that the larger the target thickness of the film to be etched, the longer the overetching time is. .

In other words, the longer the overetch time is, the more serious the damage or contamination of the surface of the semiconductor substrate is. As a result, in the third and fourth prior arts, the surface of the semiconductor substrate is severely damaged upon etching for forming contact holes in the interlayer insulating film having a large thickness.

When such damage or contamination is introduced into the semiconductor substrate region, the electrical characteristics, particularly the junction leakage current characteristics, deteriorate in the diffusion region formed in this region. In particular, a device such as DRAM or SRAM, which requires a small reduction of the junction leakage current in the diffusion layer of the storage node, is a serious problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device capable of simultaneously suppressing problems such as undesirably increasing the diameter of a contact hole, oxidizing an undesired gate electrode, and introducing an undesired damage to a semiconductor substrate. Is in.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention in a process order.

2A and 2B are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

3 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the first conventional technology.

4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the second conventional technology.

5A and 5B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the third and fourth conventional techniques, respectively.

※ Explanation of symbols for main parts of drawing

1 semiconductor substrate 2 gate oxide film

3: gate electrode 4: silicon nitride film

7,17: contact hole 9,9a, 9b, 11: side wall

14: first insulating film 15: second insulating film

16: third insulating film 17: interlayer insulating film

18 wiring 19 photoresist

In the semiconductor device manufacturing method according to the present invention, forming a first insulating film on the surface of the semiconductor substrate, forming a second insulating film on the first insulating film, forming a third insulating film on the second insulating film, Forming a contact hole penetrating through the third insulating film and reaching the surface of the second insulating film, forming a fourth insulating film on the entire surface including the contact hole, and etching the fourth insulating film by using an anisotropic etching method Forming a sidewall formed of an insulating film on the side portion of the contact hole, exposing a second insulating film, and removing the exposed second insulating film and then exposing the semiconductor substrate by removing the first insulating film.

The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description with reference to the accompanying drawings.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention in a process order.

First, as shown in FIG. 1A, a gate oxide film 2 having a thickness of 10 nm is formed on the semiconductor substrate 1 by thermal oxidation. Next, a chemical vapor deposition (CVD) method is performed by using a 100 nm thick polycrystalline silicon film having a predetermined tooth value obtained by doping phosphorus in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm 3 as a conductive film (gate electrode 3). Next, a silicon nitride film having a thickness of 100 nm is formed as the first interlayer insulating film 4 by the CVD method. Guiding to the polysilicon film may be performed by vapor phase thermal diffusion or ion implantation after film formation. In order to further reduce the resistance value of the gate electrode, the gate electrode may be formed by laminating a polycrystalline silicon film and a high melting point metal silicide such as WSi. In addition, the gate oxide film 2 acts as a pad oxide film to relieve the tensile stress of the silicon nitride film as the first insulating film.

Next, the first insulating film 4 and the conductive film (gate electrode 3) are sequentially dry-etched by the photoresist method by using the photoresist as a mask, and patterned in the same manner. A gate electrode structure 30 formed of one insulating film 4 is formed.

Next, a silicon nitride film having a thickness of 20 nm is formed as a second interlayer insulating film 5 on the surface of the semiconductor substrate 1 on which the gate electrode structure is formed by CVD.

Next, a 500 nm-thick BPSG film is formed on the second insulating film 5 as the third insulating film 6 serving as an interlayer insulating film by CVD. Here, a BPSG (borophosphosilicate glass) film is obtained by adding several percent B (boron) and P (phosphorus) to a silicon oxide film, exhibits reflowability by heat treatment, and is well known as a material suitable for an interlayer insulating film. In addition, the source-drain diffusion layer is formed at least before forming the third insulating film 6. For example, P is injected at an injection energy of 30 keV and an injection amount of 1 × 10 ¹⁴ atoms / cm 2 before the formation of the first insulating film 4, followed by injection of 80 keV and an injection amount of 5 × 10 ¹⁵ atoms / after the formation of the first insulating film 4. By injecting As in cm 2, an LDD type MOS transistor can be formed.

Next, the contact hole 7 which penetrates the 3rd insulating film 6 is formed using the photoresist method which uses a photoresist as a mask. In this case, etching is performed under the condition that the silicon oxide film can be selectively etched with respect to the silicon nitride film. As an etching condition, for example, at a substrate temperature of 100 ° C., a pressure of 60 mTorr, and an RF power of 800 W, a condition using a RIE etching apparatus that injects a CHF ₃ gas at a flow rate of 25 sccm and a CO gas at a flow rate of 75 sccm is used. May be mentioned. In these conditions, since the etching is stopped on the second insulating film 5, the bottom surface of the contact hole maintains the shape of the second insulating film 5, so that the surface of the semiconductor substrate 1 is not exposed to the etching atmosphere.

Next, after removing the photoresist, a silicon nitride film having a thickness of 20 nm is formed on the entire surface as a fourth insulating film, as shown in Fig. 1B.

Next, as shown in FIG. 1C, the entire surface is etched back by anisotropic etching to form sidewalls 9a and 9b made of silicon nitride film only on the side surfaces of the contact holes 7. Following the etch back, the surface of the semiconductor substrate 1 is etched by etching the second insulating film 5 as shown in FIG. 1D and etching the gate oxide film 2 as shown in FIG. 1E. ) Is exposed as the bottom.

Here, the gate electrode 3 is formed to be completely covered by the first insulating film 4 and the second insulating film 5 and the sidewall 9b. In this state, since the etching at the time of forming the contact hole is performed under the condition that the silicon oxide film is selectively etched with respect to the silicon nitride film, even if the contact hole 7 extends to the portion above the gate electrode 3, the silicon nitride film is formed. Since the first insulating film 4, the second insulating film 5, and the sidewall 9b on the gate electrode 3 are not removed, this can be realized.

In other words, the first embodiment of the present invention applies a self-alignment technique in which the contact holes 7 are self-aligned with respect to the gate electrode 3 to the formation of the contact holes 7. In this way, the present invention can achieve the effects of the self-aligned contact method and the inherent effects of the present invention without compromising the advantages of each method.

Next, the above-described various processes are performed on the bottom surface of the contact hole 7, and then a conductive film is filled in the contact hole 7.

2A and 2B are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

2A and 2B illustrate an embodiment when applied to the formation of a single contact hole.

First, as shown in FIG. 2A, first, as shown in FIG. 2A, a 10 nm thick silicon oxide film is formed on the semiconductor substrate 1 as the first insulating film 14 by thermal oxidation. Although the gate electrode is not shown in this figure, it can be formed together with the oxide film as in the first embodiment.

Next, a 10 nm thick silicon nitride film is formed on the entire surface by the CVD method, and then a BPSG film 500 nm thick is formed by the CVD method as the third insulating film 16 serving as an interlayer insulating film. do. The first insulating film 4 (silicon oxide film) serves as a pad oxide film that relaxes the tension of the silicon nitride film as the second insulating film 15.

Next, by using the photoresist method, the third insulating film 16 is etched back using the photoresist as a mask to open the contact hole 17. In this case, etching is performed under the condition that the silicon oxide film can be selectively etched with respect to the silicon nitride film. As an etching condition, for example, at a substrate temperature of 100 ° C., a pressure of 60 mTorr, and an RF power of 800 W, a condition using a RIE etching apparatus that injects a CHF ₃ gas at a flow rate of 25 sccm and a CO gas at a flow rate of 75 sccm is used. May be mentioned. Under these conditions, since the etching is stopped on the second insulating film 15, the surface of the semiconductor substrate 1 is not exposed to the etching atmosphere.

Next, after removing the photoresist, a 50 nm thick silicon nitride film is formed on the entire surface by a CVD method, and the entire surface is etched back by anisotropic etching to form sidewalls 9 formed of the silicon nitride film on only the side surfaces of the contact holes. do.

Following the etch back, as shown in FIG. 2B, by etching the second insulating film 15 and then etching the first insulating film 14, the surface of the semiconductor substrate 1 is exposed as the bottom surface of the contact hole.

Next, the above-described various processes are performed on the bottom surface of the contact hole 7, and then a conductive film is filled in the contact hole 7.

Although the present invention has been described with reference to specific embodiments, this description is not to be interpreted in a limiting sense. Various modifications of the disclosed embodiments are possible to those skilled in the art with reference to the description of the present invention. Accordingly, the appended claims include all modifications and embodiments that fall within the true scope of the invention.

As described above, according to the present invention, it is possible to cover the inner surface of the contact hole with the silicon nitride film except for the bottom of the contact hole. Therefore, the diameter of the contact hole is increased by wet etching for removal of a natural oxide film or the like, for the purpose of removing damage to the exposed substrate surface as the bottom of the contact hole, which is performed after the formation of the contact hole. Diffusion into the interlayer insulating film of the oxide species at the time of treatment can be prevented.

Further, according to the present invention, the etching of the interlayer insulating film at the time of forming the contact hole can be stopped once on the silicon nitride film provided on the front surface of the substrate, and the exposure of the surface of the substrate can be limited to only one time when the sidewalls are formed. Therefore, the surface exposure time of the contact hole can be significantly shortened in the etch atmosphere, and damage to the substrate forming the bottom of the contact hole can be greatly reduced.

In addition, since the present invention is suitable for the contact hole forming process by the self-aligning method, the object of the present invention can be obtained, and at the same time, the self-aligning of the contact holes can be realized.

As a result, it is suitable to be applied to devices requiring reduction of junction leakage current in storage nodes, for example, DRAM and SRAM, reduction of device area, or a margin for separation between contact holes and wiring. It is possible to provide a method for manufacturing a semiconductor device.

Claims (6)

In the semiconductor device manufacturing method: Forming a first insulating film on the surface of the semiconductor substrate; Forming a second insulating film on the first insulating film; Forming a third insulating film on the second insulating film; Forming a contact hole penetrating through the third insulating layer and reaching the surface of the second insulating layer; Forming a fourth insulating layer on the entire surface including the contact hole; Etching the fourth insulating film by using an anisotropic etching method to form a sidewall formed of the fourth insulating film on the side portion of the contact hole and exposing the second insulating film; And And removing the exposed second insulating film and exposing the semiconductor substrate by removing the first insulating film. The method of claim 1, wherein the second and fourth insulating layers are silicon nitride layers. The method of claim 2, wherein the first insulating film is a silicon oxide film. The method of claim 3, wherein the silicon oxide film is a gate oxide film. In the semiconductor device manufacturing method: Sequentially forming a gate oxide film and a gate electrode on the semiconductor substrate; Forming a first insulating film on the gate electrode and the gate oxide film; Forming a second insulating film on the first insulating film; Forming a contact hole penetrating through the second insulating layer and reaching the surface of the first insulating layer; Forming a third insulating layer on the entire surface including the contact hole; Etching the third insulating film using an anisotropic etching method to form a sidewall formed of the third insulating film on the side portion of the contact hole and exposing the first insulating film; And And removing the gate oxide film to expose the semiconductor substrate after removing the exposed first insulating film. 6. The method of claim 5, wherein the first and third insulating films are silicon nitride films.