KR100312973B1 - Method for forming metal electrode in memory device - Google Patents
Method for forming metal electrode in memory device Download PDFInfo
- Publication number
- KR100312973B1 KR100312973B1 KR1019990060641A KR19990060641A KR100312973B1 KR 100312973 B1 KR100312973 B1 KR 100312973B1 KR 1019990060641 A KR1019990060641 A KR 1019990060641A KR 19990060641 A KR19990060641 A KR 19990060641A KR 100312973 B1 KR100312973 B1 KR 100312973B1
- Authority
- KR
- South Korea
- Prior art keywords
- tungsten
- etching
- film
- forming
- nitride film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 43
- 229910052751 metal Inorganic materials 0.000 title description 13
- 239000002184 metal Substances 0.000 title description 13
- 238000005530 etching Methods 0.000 claims abstract description 65
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 64
- 239000010937 tungsten Substances 0.000 claims abstract description 63
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 claims abstract description 29
- -1 tungsten nitride Chemical class 0.000 claims abstract description 22
- 150000004767 nitrides Chemical class 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 229920000642 polymer Polymers 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 238000005406 washing Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 239000007789 gas Substances 0.000 description 15
- 238000009616 inductively coupled plasma Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 229910019001 CoSi Inorganic materials 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Plasma & Fusion (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 측벽 노칭, 스텝 프로파일 및 잔유물의 발생없이 그리고 새로운 장비 및 가스의 개발 필요 없이 TCP 방식으로 텅스텐(W)/질화텅스텐(WNx)/폴리실리콘 구조의 전극을 식각하기 위한 방법을 제공하는데 그 목적이 있는 것으로, 이를 위한 본 발명은 텅스텐 전극 형성 방법에 있어서, 소정공정이 완료된 기판 상에 폴리실리콘막, 질화텅스텐막 및 텅스텐막을 차례로 적층하는 단계; 상기 텅스텐막 상에 하드마스크로서 질화막 패턴을 형성하는 단계; 및 상기 질화막 패턴을 식각마스크로하여 상기 텅스텐막/질화텅스텐막/폴리실리콘막을 TCP 방식으로 식각하되, 텅스텐막 및 질화텅스텐막을 식각하는 제1식각단계, 변성막 제거를 위한 제2식각단계 및 폴리실리콘막을 식각하기 위한 제3식각단계로 식각을 실시하고, 상기 제1식각단계에서 소스 파워 대 바이어스 파워의 비율을 0.6∼1 : 1로 하는 단계를 포함하여 이루어짐을 특징으로 한다.The present invention provides a method for etching electrodes of tungsten (W) / tungsten nitride (WN x ) / polysilicon structures in a TCP manner without sidewall notching, step profile and residue generation and without the need for new equipment and gas development. It is an object of the present invention to provide a method of forming a tungsten electrode, comprising: sequentially stacking a polysilicon film, a tungsten nitride film and a tungsten film on a substrate on which a predetermined process is completed; Forming a nitride film pattern on the tungsten film as a hard mask; And etching the tungsten film / tungsten nitride film / polysilicon film using a TCP method using the nitride film pattern as an etching mask, and etching the tungsten film and the tungsten nitride film, the second etching step for removing the modified film, and the poly Etching is performed in a third etching step for etching the silicon film, and the first etching step includes the step of setting the ratio of source power to bias power to 0.6 to 1: 1.
Description
본 발명은 고집적 메모리소자 제조방법에 관한 것으로, 특히 메탈(metal) 게이트(메모리소자의 워드라인) 또는 메탈 비트라인을 갖는 1Gb(giga bit)급 이상의 다이나믹램(DRAM : Dynamic Random Access Memory)과 같은 초고집적 메모리소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated memory device, and in particular, such as a dynamic random access memory (DRAM) of 1Gb or more having a metal gate (word line of a memory device) or a metal bit line. It relates to a method for manufacturing an ultra-high density memory device.
고집적화의 진전으로 3년에 메모리의 용량이 4배씩 증가되어 이미 1Gb(giga bit) DRAM의 개발이 이루어졌고 그 이상의 초고집적 DRAM에 대한 연구가 진행되고 있다. 이와 같이 DRAM의 집적도가 높아질수록 전기 신호를 읽고 기록하는 역할을 하는 셀의 면적은 1Gb의 경우 대략 0.08㎛2이다. 따라서, 이에 상응하게 워드라인 및 비트라인의 요구선폭도 매우 감소하게 되었고, 그 결과 기존의 폴리실리콘 또는 단순한 실리사이드와 같은 워드라인 또는/및 비트라인(이하 워드라인 또는/및 비트라인을 '전극'이라 칭한다) 물질로는 1Gb급 이상의 DRAM에서 요구되는 미세선폭으로 낮은 저항값을 구현할 수 없게 되었다. 따라서, 아래 표1에 나타난 바와 같이 면저항(Rs)이 아주 적은 TiSi2, CoSi2, W, Mo, Al, Cu 등의 메탈로 전극을 형성하려는 연구가 꾸준히 진행되고 있다.With the progress of high integration, memory capacity has been increased by four times in three years, and 1Gb (giga bit) DRAM has already been developed. As the integration density of DRAM increases, an area of a cell that reads and writes an electrical signal is about 0.08 μm 2 for 1Gb. Accordingly, the required line widths of word lines and bit lines are correspondingly reduced, and as a result, word lines or / and bit lines such as conventional polysilicon or simple silicides (hereinafter referred to as word electrodes or / and bit lines are referred to as 'electrodes'). With this material, it is impossible to realize low resistance due to the fine line width required in DRAMs of 1Gb or more. Therefore, as shown in Table 1 below, studies are being made to form electrodes using metals such as TiSi 2 , CoSi 2 , W, Mo, Al, and Cu having very low sheet resistance (Rs).
특히 텅스텐(W)은 면저항이 상당히 적기 때문에 0.13㎛ 디자인 룰을 갖는 소자에 유용하게 적용될 수 있는 바, 텅스텐 메탈 전극은 통상 폴리실리콘막과 텅스텐층 및 이 두 층 간의 확산 혹은 반응을 방지하기 위한 예컨대 질화텅스텐(WNx) 또는 질화타이타늄(TiN)과 같은 얇은 베리어메탈(barrier metal) 층을 포함하는 3개층으로 구성되어, 텅스텐/베리어메탈/폴리실리콘막 구조의 전극을 이루게 된다.In particular, tungsten (W) can be usefully applied to devices having a 0.13 μm design rule because the sheet resistance is very low. Tungsten metal electrodes are usually used to prevent diffusion or reaction between polysilicon film and tungsten layer and the two layers. It is composed of three layers including a thin barrier metal layer such as tungsten nitride (WN x ) or titanium nitride (TiN) to form an electrode of a tungsten / barrier metal / polysilicon film structure.
한편, 현재 널리 이용되고 있는 건식 식각 장비는 TCP(Transformer coupled Plasma) 방식의 식각 장비로서, 고밀도 플라즈마를 식각 반응에 직접 이용할 수 있고, 비용이 싸며 설계가 간편하다는 등의 이유로 현재 가장 널리 이용되고 있다.On the other hand, currently widely used dry etching equipment is a TCP (Transformer coupled Plasma) etching equipment, the most widely used because of the high-density plasma can be used directly in the etching reaction, inexpensive and easy to design. .
도1은 TCP 방식 식각장비를 보여준다. 도1에 도시된 바와 같이 TCP 장비는 바이어스 파워(bias power)를 인가받는 하부전극(11)상에 기판(12)이 놓이고 반응실 위쪽에 소스 파워(source power)를 인가받는 코일(coil)(13)이 놓여있고 코일과 반응실 사이는 석영이나 세라믹 창(14)으로 분리되어 있다. 이러한 구조에서 소스 파워와 바이어스 파워를 인가하면 반응실에 유입되는 기체는 플라즈마화되는 바, 플라즈마(15)가 기판 상부에서 바로 형성되므로 고밀도 플라즈마를 직접 반응에 사용할 수 있다.Figure 1 shows a TCP type etching equipment. As shown in FIG. 1, in the TCP apparatus, a coil 12 is placed on a lower electrode 11 to which bias power is applied, and a source power is applied above the reaction chamber. (13) is placed and separated between the coil and the reaction chamber by a quartz or ceramic window (14). In this structure, when the source power and the bias power are applied, the gas flowing into the reaction chamber becomes plasma, and since the plasma 15 is formed directly on the substrate, a high density plasma can be used for the direct reaction.
그런데, 이러한 TCP 플라즈마 식각장비로 텅스텐(W)/질화텅스텐(WNx)/폴리실리콘 구조의 메탈 전극을 식각하기 위해서는 종래 텅스텐실리사이드(WSix)의 식각때와는 다른 새로운 식각조건(Recipe)이 필요한 바, 그 이유는 다음과 같다.However, in order to etch a tungsten (W) / tungsten nitride (WN x ) / polysilicon metal electrode with such a TCP plasma etching equipment, a new etching condition different from the conventional etching of tungsten silicide (WSi x ) is performed. The reason for this is as follows.
통상 텅스텐실리사이드를 식각할때에는 SF6/Cl2/O2가스를 식각 가스로 사용하였는 바, 이러한 방법으로는 텅스텐(W)/질화텅스텐(WNx)/폴리실리콘 구조의 전극의 측벽 노칭(Sidewall Notching), 스텝 프로파일(Step Profile) 및 잔유물(Residue)를 해결하기가 불가능하다. 즉 통상 50∼120 sccm의 SF6와 10∼30 sccm의 Cl2로는 W/WNx의 측벽 노칭 및 스텝 프로파일을 방지할 수 없다. 그 이유는 이전의 전극 재료인 텅스텐실리사이드(WSix) 보다는 Cl2/O2에서 화학적 식각이 덜 되기 때문이다.In general, when etching tungsten silicide, SF 6 / Cl 2 / O 2 gas was used as an etching gas. In this method, sidewall notching of an electrode having a tungsten (W) / tungsten nitride (WN x ) / polysilicon structure was performed. Notching, Step Profile and Residue are impossible to solve. Namely, SF 6 of 50 to 120 sccm and Cl 2 of 10 to 30 sccm cannot prevent sidewall notching and step profile of W / WN x . This is because the chemical etching is less in Cl 2 / O 2 than the previous electrode material tungsten silicide (WSi x ).
그리고, 플라즈마를 발생시키기 위한 소스 파워가 300∼500W, 바이어스 파워가 50∼110W로 설정되는 것이 일반적인데 이 조건 역시 소스 파워의 주 효과에 의해서 화학적 식각(Chemically Etch)을 증폭시키기는 하나 W/WNx막이 스텝(Step) 단차를 유발하여 프로파일에 악영항을 주므로써 후속공정에 문제를 유발시킨다.In addition, the source power for generating plasma is generally set to 300 to 500W and the bias power is set to 50 to 110W. This condition also amplifies chemical etching due to the main effect of the source power, but W / WN x Membrane induces a step step that adversely affects the profile, causing problems in subsequent processes.
또한, SF6/Cl2의 공정조건으로 식각시 W/WNx의 하부층인 폴리실리콘이 측면 식각(Lateral Etch)되어 세정후에 최악에 경우에는 필름이 리프팅되어 공정을 실패하는 경우가 발생한다. 이것은 SF6가스의 원천적인 문제로 공정재현성 및 식각공정마진이 줄어들게 된다. 즉 SF6가스가 원자크기가 커서 Cl2/O2보다는 공정 변화가 생기게 되는 것은 자명하다.In addition, when etching under process conditions of SF 6 / Cl 2 , polysilicon, which is a lower layer of W / WN x , is laterally etched, and in the worst case after cleaning, the film is lifted to fail the process. This is a fundamental problem with SF 6 gas, which reduces process reproducibility and etching process margins. In other words, it is obvious that the SF 6 gas has a large atomic size, resulting in a process change rather than Cl 2 / O 2 .
한편, 신규장비 투자 및 신규 가스를 개발 및 사용하여 0.13㎛ 이하의 디자인을 갖는 텅스텐 메탈 전극을 식각하려면, 그 만큼 비용 발생이 부담되고, 특히 금속식각 공정의 특성상 챔버 온도를 과도하게 올려야 하는 등 많은 부담을 주게된다. 또한 플로린(Florine)계 가스를 사용하면 게이트 산화막이 열화되어 제품에도 악영향을 주는 것도 많은 논문에 발표되고 있다.On the other hand, in order to etch a tungsten metal electrode having a design of 0.13 μm or less by investing in new equipment and developing a new gas, it costs a lot, and in particular, due to the nature of the metal etching process, the chamber temperature must be excessively increased. It is a burden. In addition, many papers have been published that use florine gas to deteriorate the gate oxide film and adversely affect the product.
본 발명은 측벽 노칭, 스텝 프로파일 및 잔유물의 발생없이 그리고 새로운 장비 및 가스의 개발 필요 없이 TCP 방식으로 텅스텐(W)/질화텅스텐(WNx)/폴리실리콘 구조의 전극을 식각하기 위한 방법을 제공하는데 그 목적이 있다.The present invention provides a method for etching electrodes of tungsten (W) / tungsten nitride (WN x ) / polysilicon structures in a TCP manner without sidewall notching, step profile and residue generation and without the need for new equipment and gas development. The purpose is.
도1은 TCP 방식 식각장비를 개략적으로 나태낸 도면.1 is a view schematically showing a TCP type etching equipment.
도2a 및 도2c는 본 발명의 바람직한 실시예에 따른 텅스텐 메탈 게이트 패턴 형성 방법을 보여주는 단면도.2A and 2C are cross-sectional views showing a tungsten metal gate pattern forming method according to a preferred embodiment of the present invention.
도3a 및 도3b는 종래 식각 방법으로 텅스텐/질화텅스텐/폴리실리콘 구조의 전극을 패터닝한 상태의 사진.3A and 3B are photographs of a patterned electrode of a tungsten / tungsten nitride / polysilicon structure by a conventional etching method.
도3c는 본 발명에 따른 전극 프로파일을 보여주는 사진.Figure 3c is a photograph showing an electrode profile according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
201 : 기판 202 : 폴리실리콘201: substrate 202: polysilicon
203 : 질화텅스텐 204 : 텅스텐203: tungsten nitride 204: tungsten
205 : 질화막 206 : 포토레지스트205 nitride film 206 photoresist
상기 목적을 달성하기 위하여 본 발명은, 텅스텐 전극 형성 방법에 있어서, 소정공정이 완료된 기판 상에 폴리실리콘막, 질화텅스텐막 및 텅스텐막을 차례로 적층하는 단계; 상기 텅스텐막 상에 하드마스크로서 질화막 패턴을 형성하는 단계; 및 상기 질화막 패턴을 식각마스크로하여 상기 텅스텐막/질화텅스텐막/폴리실리콘막을 TCP 방식으로 식각하되, 텅스텐막 및 질화텅스텐막을 식각하는 제1식각단계, 변성막 제거를 위한 제2식각단계 및 폴리실리콘막을 식각하기 위한 제3식각단계로 식각을 실시하고, 상기 제1식각단계에서 소스 파워 대 바이어스 파워의 비율을 0.6∼1 : 1로 하는 단계를 포함하여 이루어짐을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a tungsten electrode, comprising: sequentially stacking a polysilicon film, a tungsten nitride film and a tungsten film on a substrate on which a predetermined process is completed; Forming a nitride film pattern on the tungsten film as a hard mask; And etching the tungsten film / tungsten nitride film / polysilicon film using a TCP method using the nitride film pattern as an etching mask, and etching the tungsten film and the tungsten nitride film, the second etching step for removing the modified film, and the poly Etching is performed in a third etching step for etching the silicon film, and the first etching step includes the step of setting the ratio of source power to bias power to 0.6 to 1: 1.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도2a 및 도2c는 본 발명의 바람직한 실시예에 따른 텅스텐 메탈 게이트 패턴 형성 방법을 보여준다.2A and 2C show a method of forming a tungsten metal gate pattern according to a preferred embodiment of the present invention.
도2a를 참조하면, 소정공정이 완료된 기판(201) 상에 폴리실리콘막(202), 질화텅스텐막(203) 및 텅스텐막(204)을 적층하고, 그 위에 하드마스크로서 질화막(205)을 형성한다. 이어서, 게이트 마스크로서 포토레지스트(P/R)(206) 패턴을 형성한 다음, 이를 마스크로하여 질화막(205)을 식각한다.Referring to FIG. 2A, a polysilicon film 202, a tungsten nitride film 203, and a tungsten film 204 are stacked on a substrate 201 where a predetermined process is completed, and a nitride film 205 is formed thereon as a hard mask. do. Next, a photoresist (P / R) 206 pattern is formed as a gate mask, and the nitride film 205 is etched using this as a mask.
이어서, 도2b에 도시된 바와 같이 포토레지스트(206)를 스트립(Strip)한다. 구체적으로 산소 플라즈마에서 건식으로 제거한 다음, BOE 용액에서 폴리머가 완전히 제거되도록 한다.Subsequently, the photoresist 206 is stripped as shown in FIG. 2B. Specifically, it is dry removed from the oxygen plasma and then the polymer is completely removed from the BOE solution.
이어서, 도2c는 TCP 방식의 식각장비를 사용하고, 질화막을 식각마스크로하여 텅스텐/질화텅스텐/폴리실리콘막을 식각한 상태로서, 이때의 구체적인 식각 조건은 다음과 같다.Subsequently, FIG. 2C shows a state in which a tungsten / tungsten nitride / polysilicon film is etched using a TCP type etching equipment and the nitride film is used as an etching mask. Specific etching conditions are as follows.
텅스텐/질화텅스텐/폴리실리콘막의 식각은 TCP 방식의 식각 장비에서 3단계로 실시한다.The tungsten / tungsten nitride / polysilicon film is etched in three steps in a TCP type etching equipment.
먼저, 제1단계 식각으로서 Cl2, Cl2/O2및 Cl2/HBr을 독립 또는 혼합 사용하고, 소스 파워 대 바이어스 파워를 0.6:1 ∼ 1:1로 하여 텅스텐(204)과 질화텅스텐(203)을 식각한다. 바람직하게 소스 파워는 200∼300W, 바이어스 파워는 300∼400W의 범위로 한다. 제1단계 식각시의 엔드 포인트(End Point)는 폴리실리콘(202)이 드러나는 시점으로 한다. 한편, 전체 가스 플로우(Total GasFlow)는 사용 가스를 모두 합해서 30∼40 sccm로 설정하며, Cl2/O2를 적용할 경우 Cl2: O2 비율을 3:1 정도로 한다. 상기 제1단계 식각에서 중요한 점은 종래와는 다르게 소스파워를 바이어스 파워보다 적게 가지고 간다는 점인데, 이는 상대적으로 큰 바이어스 파워에 의해 이온의 직직성을 보다 크게하므로써 측벽 노칭, 스텝 프로파일을 방지하기 위함이다.First, as the first step etching, tungsten 204 and tungsten nitride are prepared by using Cl 2 , Cl 2 / O 2 and Cl 2 / HBr independently or mixed, and source power to bias power is 0.6: 1 to 1: 1. 203). Preferably, the source power is in the range of 200 to 300W, and the bias power is in the range of 300 to 400W. An end point during the first stage etching is a time point at which the polysilicon 202 is exposed. On the other hand, the total gas flow (Total GasFlow) is set to 30 to 40 sccm by adding all the gas used, the Cl 2 / O 2 ratio is about 3: 1 when Cl 2 / O 2 is applied. The important point in the first step etching is that the source power is less than the bias power, unlike the conventional method, which is to prevent sidewall notching and step profile by increasing ion straightness by the relatively large bias power. to be.
다음, 제2단계 식각으로서, 산화막 식각 가스인 C2F6, CF4가스를 Cl2또는 Cl2/O2에 첨가하여 폴리실리콘 표면에 발생되는 변성막을 제거한다. 이 변성막의 구체적인 성분은 밝혀지지 않았으나 이 변성막이 있는 상태에서 폴리실리콘을 식각하게 되면 잔유물(Residue) 및 게이트산화막의 손상을 가져오는 것이 본 발명자에 의해 밝혀졌기 때문이다. 이때 소스파워와 바이어스 파워는 각각 100∼500 W로 조절하는 것을 바람직하다. 그리고, 주식각가스인 Cl2또는 Cl2/O2는 주된 식각 가스를 1∼20 sccm로 조절하고, 첨가가스를 1∼10 sccm로 조절하며, 식각타겟은 폴리실리콘막의 표면(약 50∼100Å)이 되도록 한다.Next, as a second step of etching, C 2 F 6 , CF 4 gas, which is an oxide film etching gas, is added to Cl 2 or Cl 2 / O 2 to remove the modified film generated on the surface of the polysilicon. Although the specific component of this modified film is not known, it was found by the present inventors that the polysilicon is etched in the state where the modified film is present, resulting in damage to residue and gate oxide film. In this case, the source power and the bias power are preferably adjusted to 100 to 500 W, respectively. Cl 2 or Cl 2 / O 2 , which is a stock corner gas, adjusts the main etching gas to 1-20 sccm, and adjusts the additive gas to 1-10 sccm, and the etching target is a surface of the polysilicon film (about 50-100 kPa). )
이어서, 제3단계 식각으로서 폴리실리콘(202)를 식각하는 바, 폴리실리콘의 하부층인 게이트산화막과 60∼100 : 1 정도의 고 식각선택비가 유지되도록 하고 폴리실리콘 두께 대비 70% 정도를 과도 식각한다. 이때 바람직하게 소스 파워는 200-350 W, 바이어스 파워는 50-100W로 하여 그 비율이 4:1 ∼ 1:1 이 되도록 하고, Cl2: O2를 15 : 9 정도의 비율로 한다.Subsequently, the polysilicon 202 is etched as the third stage etching, so that the gate oxide layer, which is a lower layer of the polysilicon, and a high etching selectivity of about 60 to 100: 1 are maintained and overetched about 70% of the polysilicon thickness. . At this time, the source power is preferably 200-350 W, the bias power is 50-100 W, the ratio is 4: 1 to 1: 1, and the Cl 2 : O 2 is about 15: 9.
상기 제1단계, 제2단계 및 제3단계의 식각은 모두 TCP 장비에서 이루어지며, 기판이 올려지는 하부전극의 온도는 30∼60℃로 설정하고 챔버내 압력은 3∼7Torr로 설정한다.Etching of the first step, the second step and the third step is all performed in the TCP equipment, the temperature of the lower electrode on which the substrate is placed is set to 30 ~ 60 ℃ and the pressure in the chamber is set to 3 ~ 7 Torr.
도3a 및 도3b는 종래 식각 방법으로 텅스텐/질화텅스텐/폴리실리콘 구조의 전극을 패터닝한 상태로서, 도3a에서는 전극 패턴이 스텝 프로파일('A')을 갖는 것을 보여주고, 도3b는 폴리실리콘에서 노칭('B')이 발생한 것을 보여준다. 반면에 도3c는 본 발명에 따른 전극 프로파일을 보여주는 SEM 및 TEM 사진인 바, 전체적으로 전극들이 양호한 프로파일을 보이고 있다.3A and 3B are patterns of electrodes of a tungsten / tungsten nitride / polysilicon structure patterned by a conventional etching method, and FIG. 3A shows that the electrode pattern has a step profile 'A', and FIG. 3B shows polysilicon. Shows that notching ('B') has occurred. On the other hand, Figure 3c is a SEM and TEM picture showing the electrode profile according to the present invention, the electrodes show a good profile as a whole.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 기존의 장비를 그대로 사용하여 텅스텐 메탈 전극을 양산할 수 있어 비용 및 생산성을 증대시키는 효과를 가져다 주며, 또한 재현성있고 규정화된 식각조건(Recipe)로 양산시 높은 수율을 얻을 수 있는 효과가 있다.The present invention can mass-produce tungsten metal electrodes using existing equipment as it is, bringing the effect of increasing the cost and productivity, and also have the effect of obtaining high yield in mass production with reproducible and prescribed etching conditions (Recipe). have.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990060641A KR100312973B1 (en) | 1999-12-22 | 1999-12-22 | Method for forming metal electrode in memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990060641A KR100312973B1 (en) | 1999-12-22 | 1999-12-22 | Method for forming metal electrode in memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010063528A KR20010063528A (en) | 2001-07-09 |
| KR100312973B1 true KR100312973B1 (en) | 2001-11-07 |
Family
ID=19628362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990060641A KR100312973B1 (en) | 1999-12-22 | 1999-12-22 | Method for forming metal electrode in memory device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100312973B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100832027B1 (en) * | 2002-06-29 | 2008-05-26 | 주식회사 하이닉스반도체 | Forming method of semiconductor device pattern capable of protecting tapered profile of hardmask |
-
1999
- 1999-12-22 KR KR1019990060641A patent/KR100312973B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010063528A (en) | 2001-07-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100480610B1 (en) | Forming method for fine patterns using silicon oxide layer | |
| US6551913B1 (en) | Method for fabricating a gate electrode of a semiconductor device | |
| US5167762A (en) | Anisotropic etch method | |
| US6753133B2 (en) | Method and manufacturing a semiconductor device having a ruthenium or a ruthenium oxide | |
| KR100316028B1 (en) | Method for forming metal electrode in memory device | |
| JPH08236512A (en) | Polysilicon/polyside etching method for submicron gate stack | |
| US5792708A (en) | Method for forming residue free patterned polysilicon layers upon high step height integrated circuit substrates | |
| JP2005197640A (en) | Flash memory element manufacturing method | |
| KR100312973B1 (en) | Method for forming metal electrode in memory device | |
| KR20040022996A (en) | Forming method for floating gate patterns by etching with mixture of HBr and He gas and manufacturing method for FLASH memory device using the same | |
| JP2006324615A (en) | Method of forming conductive line of semiconductor element | |
| KR100278277B1 (en) | Method for improve contact resistance of silicide in semiconductor device | |
| JPH09330987A (en) | Manufacture of semiconductor device | |
| JP3358179B2 (en) | Plasma etching method for polysilicon layer | |
| JPH05267251A (en) | Formation of contact hole in semiconductor device | |
| KR20020000349A (en) | A method for forming a capacitor of a semiconductor device | |
| KR100341583B1 (en) | Method for fabricating semiconductor device to reduced contact resistance | |
| KR100744671B1 (en) | Method for forming a micro pattern in semiconductor device | |
| KR20050068363A (en) | Method for fabricating thin pattern using the hard mask | |
| JP3780657B2 (en) | Etching method | |
| TW425683B (en) | Method of diminishing the critical dimension of two bit lines on both sides of lower storage node for a memory cell | |
| KR100525106B1 (en) | method for forming a storage node pattern in a semiconductor device | |
| KR19990005143A (en) | Contact hole formation method of semiconductor device | |
| KR100652361B1 (en) | Method for fabricating a semiconductor device using self aligned contact | |
| KR20000074480A (en) | Method for forming gate electrode of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100920 Year of fee payment: 10 |
|
| LAPS | Lapse due to unpaid annual fee |