KR20020000349A - A method for forming a capacitor of a semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to prevent a characteristic of a storage electrode from being degraded by an electric filed concentration phenomenon, by forming a cylindrical conductive layer with no cusp in an end portion of the sidewall of the cylindrical storage electrode. CONSTITUTION: A lower insulation layer(33) having a storage electrode contact plug(50) is formed on a semiconductor substrate(31). An etch barrier layer is formed on the entire surface by a predetermined thickness, and a sacrificial insulation layer is formed on the etch barrier layer. A photoresist layer pattern is formed on the sacrificial insulation layer by an exposure and development process using a storage electrode mask. The sacrificial insulation layer is etched to expose the etch barrier layer by using the photoresist layer pattern as a mask. The photoresist layer pattern and the exposed etch barrier layer are eliminated to expose the contact plug. A conductive layer connected to the contact plug is formed on the entire surface. The conductive layer is etched by a predetermined thickness from the surface to form a cylindrical conductive layer which is connected to the contact plug and has the sidewalls of the etch barrier layer and the sacrificial insulation layer. The sacrificial insulation layer and the etch barrier layer are eliminated.

Description

A method for forming a capacitor of a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device, and more particularly, to a technology capable of securing a capacitance sufficient for high integration of a semiconductor device by forming a capacitor having a three-dimensional structure.

As semiconductor devices are highly integrated and cell size is reduced, it is difficult to secure a capacitance that is proportional to the surface area of the storage electrode.

In particular, in a DRAM device having a unit cell composed of one MOS transistor and a capacitor, it is important to reduce the area while increasing the capacitance of a capacitor that occupies a large area on a chip, which is an important factor for high integration of the DRAM device.

Thus, the capacitance of the capacitor represented by (Eo × Er × A) / T (wherein Eo is the vacuum dielectric constant, Er is the dielectric constant of the dielectric film, A is the area of the capacitor and T is the thickness of the dielectric film) is increased. In order to increase the surface area of the storage electrode, which is a lower electrode, a capacitor was formed.

And the three-dimensional structure generally used is a cylindrical shape.

1A and 1B are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to the prior art.

First, a lower insulating layer 13 is formed on the semiconductor substrate 11.

In this case, the lower insulating layer 13 is formed by forming an isolation layer (not shown), a word line (not shown), and a bit line (not shown) and planarizing an upper portion thereof.

Here, the lower insulating layer 13 is formed of an insulating material having excellent fluidity, such as BPSG.

Next, a storage electrode contact hole 30 exposing a predetermined portion of the semiconductor substrate 11 is formed.

In this case, the storage electrode contact hole 30 is formed by etching the lower insulating layer 13 by a photolithography process using a storage electrode contact mask (not shown) to expose the semiconductor substrate.

Next, a storage electrode contact plug for filling the storage electrode contact hole 30 is formed.

In this case, the storage electrode contact plug is formed by forming a first polycrystalline silicon film 15 filling the contact hole 30 on the entire surface and flattening etching.

Then, a second polycrystalline silicon film 17 and a sacrificial oxide film 19 are formed on the entire surface, respectively.

The stacked structure of the second polysilicon layer 17 and the sacrificial oxide layer 19 is patterned by a photolithography process using a storage electrode mask (not shown).

In this case, the second polysilicon film 17 is connected to a contact plug formed of the first polycrystalline silicon film 15.

Next, a third polycrystalline silicon film 21 is formed on the entire surface including the sidewalls of the laminated structure at a predetermined thickness. (FIG. 1A)

The third polysilicon layer 23 is anisotropically etched to form a third polysilicon layer 23 spacer on the sidewalls of the sacrificial oxide layer 21 and the second polysilicon layer 19.

In this case, the sacrificial oxide film 21 is exposed.

Next, the exposed sacrificial oxide layer 21 is removed to form a cylindrical storage electrode including the first, second, and third polysilicon layers 15, 19, and 23.

At this time, the portion ⓐ, which is the upper end of the sidewall of the cylindrical storage electrode, is sharper than other portions, so that an electric field is concentrated, thereby degrading the characteristics of the storage electrode. In addition, there is a problem of degrading the dielectric properties of the dielectric film formed in a subsequent process. (FIG. 1B)

The present invention to solve the problem according to the prior art as described above, by forming a cylindrical storage electrode in the pattern so that the peak portion of the upper sidewall of the cylindrical storage electrode is not generated by preventing the deterioration of the characteristics of the device of the semiconductor device SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a capacitor of a semiconductor device, which improves characteristics and reliability and thereby enables high integration of the semiconductor device.

1A to 1B are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to the prior art.

2A to 2E are cross-sectional views showing a capacitor forming method of a semiconductor device in an embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

11,31: semiconductor substrate 13,33: lower insulating layer

15,50: storage electrode contact plug, first polysilicon film

17,41 second polysilicon film 19,37 sacrificial oxide film

21: third polycrystalline silicon film 30, 60: storage electrode contact hole

35 etch barrier layer 39 photosensitive film pattern

Ⓐ, ⓑ: silicon side type storage electrode sidewall top

In order to achieve the above object, a method of forming a capacitor of a semiconductor device according to the present invention,

Forming a lower insulating layer having a storage electrode contact plug on the semiconductor substrate;

Forming an etch barrier layer on the entire surface and forming a sacrificial insulating film thereon;

Forming a photoresist pattern on the sacrificial insulating layer by exposure and development using a storage electrode mask;

Exposing the etch barrier layer by etching the sacrificial insulating layer using the photoresist pattern as a mask;

Exposing the contact plug by removing the photoresist pattern and removing the exposed etch barrier layer;

Forming a conductive layer connected to the contact plug on the entire surface;

Etching the conductive layer to a predetermined thickness from a surface to form a cylindrical conductive layer connected to the contact plug and provided to sidewalls of the etch barrier layer and the sacrificial insulating layer;

And removing the sacrificial insulating layer and the etching barrier layer.

On the other hand, the principle of the present invention is to form the upper sidewall of the cylindrical storage electrode to have the same thickness as the sidewall to reduce the electric field concentration phenomenon at the end of the sidewall, thereby preventing the deterioration of dielectric film characteristics in subsequent steps .

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to an exemplary embodiment of the present invention, one side showing a cell unit 100 and the other side showing a peripheral circuit unit 200.

First, a lower insulating layer 33 is formed on the semiconductor substrate 31.

In this case, the lower insulating layer 33 is formed by forming an isolation layer (not shown), a word line (not shown), and a bit line (not shown) and planarizing an upper portion thereof.

Here, the lower insulating layer 33 is formed of an insulating material having excellent fluidity, such as BPSG.

Next, a storage electrode contact hole 60 exposing a predetermined portion of the semiconductor substrate 31 is formed.

In this case, the storage electrode contact hole 60 is formed by etching the lower insulating layer 33 by the photolithography process using a storage electrode contact mask (not shown) to expose the semiconductor substrate.

Thereafter, a contact plug is formed of the first polysilicon film 50 filling the storage electrode contact hole 60.

Next, an etching barrier layer 35 is formed on the entire surface including the first polysilicon film 50 at a predetermined thickness.

In this case, the etch barrier layer 35 has a high selectivity for the sacrificial oxide layer to be used in a subsequent process such as a nitride layer, an oxynitride layer, a Si-rich oxynitride layer, alumina (Al ₂ O ₃ ), tantalum oxide layer (Ta ₂ O ₅ ), or the like. It is formed into a thin film that can secure.

Next, a sacrificial oxide layer 37 is formed on the etch barrier layer 35.

The photoresist pattern 39 is formed on the sacrificial oxide film 37.

In this case, the photoresist pattern 39 is formed by an exposure and development process using a storage electrode mask. (FIG. 2A)

Next, the sacrificial oxide film 37 is etched using the photoresist pattern 39 as a mask.

At this time, in the etching process of the sacrificial oxide film 37, the etching barrier layer 35 is performed as an etching barrier.

Here, the etching process of the sacrificial oxide film 37, CF ₄ , C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₄ F which causes a large amount of polymer F-containing gases such as ₈ , C ₅ F ₈ , CH ₃ F, CH ₂ F ₂ , C ₂ HF ₅ , CHF ₃ , NF ₃ , SF ₆ and carbon rich such as CxHyHz (x, y, z≥2) carbon rich) CF gas is used as the first gas.

In addition, a gas containing O, such as O ₂ , CO, CO ₂ , NO, or NO ₂ necessary for forming an etching cross section, is used as the second etching gas.

In order to improve the etching characteristics by increasing the stability of the plasma and the sputtering effect, an inert gas such as He, Ne, Ar, or Xe is used as the third etching gas.

In order to maintain the etching selectivity with respect to the etching barrier layer 35, an inert gas such as Cl ₂ , BCl 3, HBr, or the like is used as the fourth etching gas.

In addition, the etching process of the sacrificial oxide film 37 may be performed by mixing the first, second, third and fourth etching gases.

Next, the photoresist pattern 39 is removed and a cleaning process is performed.

Here, the cleaning process also serves to etch the etching barrier layer 35.

At this time, the cleaning process is carried out using a solution such as H ₂ O ₂ / H ₂ SO ₄ / DI or HF / NH ₄ F / DI. (FIG. 2B)

Next, a second polysilicon film 41 is formed over the entire surface. In this case, the second polysilicon layer 41 may be formed of W, Pt RuO _2, Ir, or other conductive material. (FIG. 2C)

The second polysilicon film 41 is etched from the surface by a predetermined thickness to remove the second polycrystalline silicon film 41 remaining in the peripheral circuit unit 200.

In this case, the etching process of the second polysilicon film 41 may be performed by rotating the wafer using the HNO ₃ / HF / DI mixed solution or by rotating the solution. The second polycrystalline silicon film 41 having a cylindrical structure is formed by the ACE method. Here, the etching amount during the etching process may be adjusted by adjusting the doping concentration and the deposition temperature during the deposition process of the second polysilicon film 41.

In the case of using W instead of the second polysilicon film 41, HNO ₃ / HF / DI mixed solution or H ₂ O ₂ / TMAH solution may be used or HNO ₃ / H ₂ SO ₄ / DI mixed solution may be used. Use it.

In addition, an isotropic dry etching method may be used without using the ACE method.

The isotropic dry etching method,

A gas containing F, such as CF ₄ , NF ₃ , SF ₆ , which causes a large amount of polymer, is used as the first gas, and a gas containing O, such as O ₂ , CO, CO ₂ , NO, or NO ₂ , required for etching cross-section is formed. It is used as the second etching gas, and inert gas such as He, Ne, Ar, and Xe is used as the third etching gas to improve the etching characteristics by increasing the stability and sputtering effect of the plasma, and to improve the etching characteristics. Inert gas such as ₂ , BCl ₃ , HBr and the like is used as the fourth etching gas, and the _first , _second , _third and fourth etching gases are mixed. (FIG. 2D)

Next, the sacrificial oxide layer 37 and the etching barrier layer 35 are removed. (FIG. 2E)

As described above, in the method of forming a capacitor of a semiconductor device according to the present invention, a cylindrical shape without a dot is formed at the end of the sidewall of the cylindrical storage electrode to prevent deterioration of characteristics of the storage electrode due to electric field concentration and to be formed in a subsequent process. It provides an effect of preventing the deterioration of the characteristics of the dielectric film.

Claims (19)

Forming a lower insulating layer having a storage electrode contact plug on the semiconductor substrate; Forming an etch barrier layer on the entire surface and forming a sacrificial insulating film thereon; Forming a photoresist pattern on the sacrificial insulating layer by exposure and development using a storage electrode mask; Exposing the etch barrier layer by etching the sacrificial insulating layer using the photoresist pattern as a mask; Exposing the contact plug by removing the photoresist pattern and removing the exposed etch barrier layer; Forming a conductive layer connected to the contact plug on the entire surface; Etching the conductive layer to a predetermined thickness from a surface to form a cylindrical conductive layer connected to the contact plug and provided to sidewalls of the etch barrier layer and the sacrificial insulating layer; And removing the sacrificial insulating layer and the etch barrier layer. The method of claim 1, The etch barrier layer can secure a high selectivity for the sacrificial oxide film to be used in subsequent processes such as nitride film, oxynitride film, Si-rich oxynitride film, alumina (Al ₂ O ₃ ), tantalum oxide film (Ta ₂ O ₅ ) A method of forming a capacitor of a semiconductor device, characterized in that formed in a thin film. The method of claim 1, And the sacrificial insulating film is an oxide film. The method of claim 1, The etching process of the sacrificial insulating film is CF ₄ , C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₄ F ₈ , C ₅ F _{8, CH 3 F, CH 2} F 2, C 2 HF 5, CHF 3, NF 3, SF 6 F -containing gas selected from the group consisting of and CxHyHz (x, y, z≥2) carbon-rich (rich carbon, such as A method for forming a capacitor of a semiconductor device, characterized in that the first gas is selected from among CF-based gases. The method of claim 1, The sacrificial insulating layer etching process may be performed by using a gas containing oxygen (O) selected from the group consisting of O ₂ , CO, CO ₂ , NO, and NO ₂ required for forming an etching cross section as a second etching gas. A method of forming a capacitor of a semiconductor device. The method of claim 1, In the sacrificial insulating layer etching process, an inert gas selected from the group consisting of He, Ne, Ar, and Xe is used as a third etching gas in order to improve etching stability by increasing stability and sputtering effect of plasma. Capacitor formation method. The method of claim 1, In the sacrificial insulating layer etching process, a capacitor of a semiconductor device using an inert gas selected from the group consisting of Cl ₂ , BCl ₃ , and HBr as a fourth etching gas to maintain an etching selectivity with respect to the etching barrier layer. Formation method. The method of claim 1, The sacrificial insulating layer etching process, CF ₄ , C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₄ F ₈ , C ₅ F ₈ that causes a large amount of polymer , C ₃ F, CH ₂ F ₂ , C ₂ HF ₅ , CHF ₃ , NF ₃ , SF ₆ and F-containing gas selected from the group consisting of carbon rich such as CxHyHz (x, y, z≥2) A first gas selected from CF series gases, A second etching gas including oxygen (O) selected from the group consisting of O ₂ , CO, CO ₂ , NO, and NO ₂ required for forming an etching cross section; A third etching gas which is an inert gas selected from the group consisting of He, Ne, Ar, and Xe in order to improve etching stability by increasing the stability and sputtering effect of the plasma, The sacrificial insulating layer etching process may be performed by mixing a fourth etching gas which is an inert gas selected from the group consisting of Cl ₂ , BCl ₃ , and HBr to maintain an etching selectivity with respect to the etching barrier layer. Capacitor formation method. The method of claim 1, The removing of the etch barrier layer is a capacitor forming method of the semiconductor device, characterized in that for performing the cleaning step after the photosensitive film pattern. The method of claim 9, The cleaning process is a capacitor forming method of a semiconductor device, characterized in that performed using a H ₂ O ₂ / H ₂ SO ₄ / DI or HF / NH ₄ F / DI solution. The method of claim 1, And the conductive layer is formed of a conductive material selected from the group consisting of a polycrystalline silicon film, W, Pt, RuO ₂ or Ir. The method of claim 11, In the case where the conductive layer is a polysilicon film, the etching process may be performed by rotating a wafer using an HNO ₃ / HF / DI mixed solution or by rotating an advanced chemical etch (ACE) method. A method of forming a capacitor of a semiconductor device, wherein the etching amount is controlled by controlling the doping concentration and the deposition temperature during the deposition process. The method of claim 11, In the case where the conductive layer is tungsten (W), a wet etching method using a HNO ₃ / HF / DI mixed solution or a H ₂ O ₂ / TMAH solution or a HNO ₃ / H ₂ SO ₄ / DI mixed solution is used. A method for forming a capacitor of a semiconductor device, characterized in that carried out by the method. The method of claim 1, And etching the conductive layer by an isotropic dry etching method. The method of claim 14, The isotropic dry etching method is a capacitor forming method of a semiconductor device, characterized in that the first gas containing a F-containing gas selected from the group consisting of CF ₄ , NF ₃ , SF ₆ causing a large amount of polymer. The method of claim 14, The isotropic dry etching method is a semiconductor, characterized in that a gas containing oxygen (O) selected from the group consisting of O ₂ , CO, CO ₂ , NO, NO ₂ required for etching cross-sectional formation as a second etching gas Capacitor Formation Method of Device. The method of claim 14, The isotropic dry etching method includes using an inert gas selected from the group consisting of He, Ne, Ar, and Xe as a third etching gas to improve etching stability by increasing the stability and sputtering effect of the plasma. Capacitor formation method. The method of claim 14, The isotropic dry etching method, the method of forming a capacitor of the semiconductor device, characterized in that for using the inert gas selected from the group consisting of Cl ₂ , BCl ₃ , HBr to improve the etching characteristics as a fourth etching gas. The method of claim 14, The isotropic dry etching method, the sacrificial insulating film etching process, CF ₄ , C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₄ which causes a large amount of polymer F-containing gas selected from the group consisting of F ₈ , C ₅ F ₈ , CH ₃ F, CH ₂ F ₂ , C ₂ HF ₅ , CHF ₃ , NF ₃ , SF ₆ and CxHyHz (x, y, z≥2) and The first gas selected from the same carbon rich CF-based gas, A second etching gas including oxygen (O) selected from the group consisting of O ₂ , CO, CO ₂ , NO, and NO ₂ required for forming an etching cross section; A third etching gas which is an inert gas selected from the group consisting of He, Ne, Ar, and Xe in order to improve etching stability by increasing the stability and sputtering effect of the plasma, The sacrificial insulating layer etching process may be performed by mixing a fourth etching gas which is an inert gas selected from the group consisting of Cl ₂ , BCl ₃ , and HBr to maintain an etching selectivity with respect to the etching barrier layer. Capacitor formation method.