KR20010063707A - Method of manufacturing a capacitor in a semiconductor device - Google Patents
Method of manufacturing a capacitor in a semiconductor device Download PDFInfo
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- KR20010063707A KR20010063707A KR1019990061783A KR19990061783A KR20010063707A KR 20010063707 A KR20010063707 A KR 20010063707A KR 1019990061783 A KR1019990061783 A KR 1019990061783A KR 19990061783 A KR19990061783 A KR 19990061783A KR 20010063707 A KR20010063707 A KR 20010063707A
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- Prior art keywords
- capacitor
- film
- oxide film
- layer
- photoresist
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- 239000003990 capacitor Substances 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000010410 layer Substances 0.000 claims abstract description 37
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 238000005498 polishing Methods 0.000 claims abstract description 10
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000000126 substance Substances 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 12
- 238000007517 polishing process Methods 0.000 claims description 3
- 230000003667 anti-reflective effect Effects 0.000 claims description 2
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010169 landfilling Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로, 특히 실린더 구조 하부전극 형성 공정의 안정화를 확보할 수 있는 반도체 소자의 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly to a method for manufacturing a capacitor of a semiconductor device capable of securing stabilization of a cylinder structure lower electrode forming process.
반도체 소자의 고집적화에 따라 캐패시터의 용량을 확보하기 위해 캐패시터의 높이가 증가되고 캐패시터 간의 간격(spacing)이 감소하게 된다. 종래에는 하부전극용 폴리실리콘층을 형성하고 리필(refill) 산화막을 증착한 후 식각공정을 진행하였는데, 소자가 고집적화 될수록 안정적인 캐패시터 용량 확보를 위해 캐패시터의 높이를 높임에 따라 리필 산화막의 하부전극간 갭 매립에 한계가 있다. 이와 같은 리필 산화막의 갭 매립 불량은 후속 식각 공정시 하부전극용 폴리실리콘의 어택(attack)을 초래하는 문제점이 있다.As the semiconductor device is highly integrated, the height of the capacitor is increased and the spacing between the capacitors is reduced to secure the capacity of the capacitor. Conventionally, after forming a polysilicon layer for the lower electrode and depositing a refill oxide film, the etching process was performed. As the device becomes more integrated, the gap between the lower electrodes of the refill oxide film is increased as the height of the capacitor is increased to secure stable capacitor capacity. There is a limit to landfilling. Such a gap filling gap of the refill oxide film may cause an attack of the polysilicon for the lower electrode during the subsequent etching process.
이러한 문제점을 해결하기 위하여 리필 산화막 대신 포토레지스트막을 이용하여 하부전극 간의 갭을 매립하고 식각 공정을 진행하는 방법을 적용하고 있다. 그러나 이 방법에서는 하부전극용 폴리실리콘층을 식각해야 할 부분에 포토레지스트막이 잔류되도록 하지 않기 위해 과도한 노광(over expose)을 해야 하는데, 이때 하부전극 사이에 매립된 포토레지스트가 손실되어 폴리실리콘보다 낮은 높이로 마스크가 형성되게 된다. 이러한 상태에서 식각 공정을 진행하게 되면 하부전극 상단이 날카롭게 형성되게 된다. 또한, 캐패시터의 용량을 극대화하기 위하여 하부전극용 폴리실리콘층 표면에 단안정 폴리실리콘(Metastable Poly-Si; MPS)을 성장시키는 경우에는 MPS의 브로큰(broken)으로 인해 마이크로 브릿지(Micro bridge)가 발생하게 되는 문제점이 있다.In order to solve this problem, a method of filling the gap between the lower electrodes using the photoresist film instead of the refill oxide film and performing an etching process is applied. However, this method requires over-exposure in order to prevent the photoresist film from remaining in the portion where the lower electrode polysilicon layer should be etched. In this case, the photoresist buried between the lower electrodes is lost and lower than the polysilicon. The mask is formed at the height. When the etching process is performed in this state, the upper end of the lower electrode is sharply formed. In addition, when monostable polysilicon (MPS) is grown on the surface of the polysilicon layer for the lower electrode in order to maximize the capacity of the capacitor, a micro bridge is generated due to the MPS broken. There is a problem.
따라서, 본 발명은 하부전극 사이를 매립하기 위한 포토레지스트막 형성 후 포토레지스트막의 빠른 제거율을 이용한 터치 폴리싱 방법으로 포토레지스트막을 확학적 기계적 연마 공정으로 연마하므로써, 후속 하부전극용 폴리실리콘 식각 공정을 용이하게 진행하여 캐패시터의 공정 안정화를 확보할 수 있는 반도체 소자의 캐패시터 제조 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention facilitates the subsequent polysilicon etching process for the lower electrode by polishing the photoresist film by a mechanical mechanical polishing process by using a touch polishing method using a fast removal rate of the photoresist film after forming the photoresist film to fill between the lower electrodes. It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device capable of ensuring the process stabilization of the capacitor.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 캐패시터 제조 방법은 캐패시터를 형성하기 위한 하부구조가 형성된 반도체 기판 상에 층간 절연막을 형성하고, 상기 층간 절연막의 선택된 부분을 제거하여 캐패시터 플러그를 형성하는 단계; 상기 캐패시터 플러그를 포함한 전체구조 상에 제 1 반사 방지막, 산화막, 희생 산화막 및 제 2 반사 방지막을 순차적으로 형성한 후, 포토레지스트 패턴을 이용한 식각 공정으로 상기 제 2 반사 방지막, 희생 산화막 및 산화막을 순차적으로 식각하는 단계; 노출된 상기 제 1 및 제 2 반사 방지막을 동시에 제거하고, 이로 인하여 상기 캐패시터 플러그의 상부면이 노출되는 단계; 상기 캐패시터 플러그를 포함한 전체구조 상에 폴리실리콘층을 형성한 후, 갭이 매립되도록 포토레지스트막을 형성하는 단계; 상기 포토레지스트막을 화학적 기계적 연마 공정으로 연마하여 상기 희생 산화막 상부의 폴리실리콘층을 노출시키는 단계; 및 상기 폴리실리콘층의 노출 부분, 상기 포토레지스트막 및 상기 희생 산화막을 순차적으로 제거하여 캐패시터의 하부전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In the method of manufacturing a capacitor of a semiconductor device according to the present invention for achieving the above object, an interlayer insulating film is formed on a semiconductor substrate on which a substructure for forming a capacitor is formed, and a selected portion of the interlayer insulating film is removed to form a capacitor plug. Doing; After sequentially forming a first antireflection film, an oxide film, a sacrificial oxide film, and a second antireflection film on the entire structure including the capacitor plug, the second antireflection film, the sacrificial oxide film, and the oxide film are sequentially formed by an etching process using a photoresist pattern. Etching with; Simultaneously removing the exposed first and second anti-reflective layers, thereby exposing the top surface of the capacitor plug; Forming a polysilicon layer on the entire structure including the capacitor plug, and then forming a photoresist film to fill the gap; Polishing the photoresist film by a chemical mechanical polishing process to expose a polysilicon layer on the sacrificial oxide film; And sequentially removing the exposed portion of the polysilicon layer, the photoresist film and the sacrificial oxide film to form a lower electrode of the capacitor.
도 1a 내지 1h는 본 발명에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도.1A to 1H are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
101 : 반도체 기판 102 : 비트라인101 semiconductor substrate 102 bit line
103 : 비트라인 스페이서 104 : 층간 절연막103: bit line spacer 104: interlayer insulating film
105 : 캐패시터 플러그 106 : 제 1 반사 방지막105: Capacitor plug 106: First antireflection film
107 : 산화막 108 : 희생 산화막107: oxide film 108: sacrificial oxide film
109 : 제 2 반사 방지막 110 : 포토레지스트 패턴109: second antireflection film 110: photoresist pattern
111 : 폴리실리콘층(하부전극) 112 : 포토레지스트막111 polysilicon layer (lower electrode) 112 photoresist film
이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
도 1a 내지 1h는 본 발명에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A to 1H are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.
도 1a에 도시된 바와 같이, 비트라인(102), 비트라인 스페이서(103) 등의 하부구조가 형성된 반도체 기판(101) 상에 층간 절연막(104)을 형성하고. 층간 절연막(104)의 선택된 부분을 제거하여 캐패시터용 콘택 홀을 형성한 후, 콘택 홀에 도전물질을 매립하여 캐패시터 플러그(105)를 형성한다. 이후, 캐패시터 플러그(105)를 포함한 전체구조 상에 제 1 반사 방지막(106) 및 산화막(107)을 순차적으로 형성한다. 여기에서, 제 1 반사 방지막(106)은 300 내지 600Å의 두께로 형성하며, 산화막(107)은 PE-TEOS를 이용하여 형성한다.As shown in FIG. 1A, an interlayer insulating film 104 is formed on a semiconductor substrate 101 on which substructures such as a bit line 102 and a bit line spacer 103 are formed. After the selected portion of the interlayer insulating film 104 is removed to form a capacitor contact hole, a conductive material is embedded in the contact hole to form the capacitor plug 105. Thereafter, the first antireflection film 106 and the oxide film 107 are sequentially formed on the entire structure including the capacitor plug 105. Here, the first antireflection film 106 is formed to a thickness of 300 to 600 kPa, and the oxide film 107 is formed using PE-TEOS.
도 1b에 도시된 바와 같이, 산화막(107)이 형성된 전체구조 상에 희생 산화막(108) 및 제 2 반사 방지막(109)을 순차적으로 형성하고 하부전극이 형성될 부분을 확정하기 위한 포토레지스트 패턴(110)을 형성한다. 여기에서, 희생 산화막(108)은 식각율이 빠른 산화막을 이용하여 형성하는데, 예를 들어 BPSG, PSG, USG, SOG 중 어느 하나를 이용한다.As shown in FIG. 1B, the sacrificial oxide film 108 and the second anti-reflection film 109 are sequentially formed on the entire structure on which the oxide film 107 is formed, and a photoresist pattern for deciding a portion where the lower electrode is to be formed 110). Here, the sacrificial oxide film 108 is formed by using an oxide film having a high etching rate, for example, any one of BPSG, PSG, USG, and SOG.
도 1c에 도시된 바와 같이, 포토레지스트 패턴(110)을 마스크로 이용하여 노출된 제 2 반사 방지막(109), 희생 산화막(108) 및 산화막(107)을 순차적으로 식각한다. 이후, 포토레지스트 패턴(110)을 제거한다. 이때에는 제 1 반사 방지막(106)이 식각 정지층으로 이용된다.As illustrated in FIG. 1C, the exposed second anti-reflection film 109, the sacrificial oxide film 108, and the oxide film 107 are sequentially etched using the photoresist pattern 110 as a mask. Thereafter, the photoresist pattern 110 is removed. In this case, the first antireflection film 106 is used as an etch stop layer.
도 1d에 도시된 바와 같이, 노출된 제 1 반사 방지막(106) 및 희생 산화막(108) 상에 잔류하는 제 2 반사 방지막을 동시에 제거한다.As shown in FIG. 1D, the exposed first anti-reflection film 106 and the second anti-reflection film remaining on the sacrificial oxide film 108 are simultaneously removed.
도 1e에 도시된 바와 같이, 캐패시터의 하부전극으로 사용될 폴리실리콘층(111)을 형성하고, 하부전극 사이의 갭이 매립되도록 전체구조 상에 포토레지스트막(112)을 형성한다.As shown in FIG. 1E, the polysilicon layer 111 to be used as the lower electrode of the capacitor is formed, and the photoresist film 112 is formed on the entire structure such that the gap between the lower electrodes is filled.
도 1f에 도시된 바와 같이, 하부전극용 폴리실리콘층(111) 상부가 노출되도록 포토레지스트막(112)을 연마한다. 포토레지스트막(112)을 연마할 때에는 포토레지스트막(112)의 빠른 제거 속도 특성을 갖는 터치 폴리싱(touch polishing) 방법을 이용한다. 이러한 방법으로 포토레지스트막(112)을 제거한 후에는 하부전극용 폴리실리콘층(111)과 포토레지스트막(112)의 높이가 동일하므로, 후속 식각 공정시 폴리실리콘층(111) 상부가 날카로와 지는 등의 문제를 방지할 수 있다.As shown in FIG. 1F, the photoresist film 112 is polished to expose the upper portion of the polysilicon layer 111 for lower electrodes. When polishing the photoresist film 112, a touch polishing method having a fast removal rate characteristic of the photoresist film 112 is used. After the photoresist film 112 is removed in this manner, the heights of the polysilicon layer 111 and the photoresist film 112 for the lower electrode are the same, so that the upper portion of the polysilicon layer 111 may be sharp during the subsequent etching process. It can prevent problems such as losing.
도 1g에 도시된 바와 같이, 포토레지스트막(112) 연마 후 노출된 하부전극용 폴리실리콘층(111)을 에치백(etch back) 공정에 의해 제거한다.As shown in FIG. 1G, the polysilicon layer 111 for lower electrodes exposed after polishing the photoresist layer 112 is removed by an etch back process.
도 1h에 도시된 바와 같이, 포토레지스트막(112)을 제거하고 산화막 딥 아웃(dip out)을 통해 희생 산화막(108)을 제거하여 캐패시터의 하부전극을 완성한다.As shown in FIG. 1H, the lower resist of the capacitor is completed by removing the photoresist film 112 and removing the sacrificial oxide film 108 through an oxide film dip out.
이후, 도시하지는 않았지만 통상의 공정을 통해 유전체막 및 성부전극을 형성하여 캐패시터를 제조한다.Subsequently, although not shown, a capacitor is manufactured by forming a dielectric film and a male electrode through a conventional process.
상술한 바와 같이,본 발명은하부전극 간에 매립된 포토레지스트막을 터치 폴리싱(touch polishing) 방법으로 연마하므로써, 하부전극 간의 포토레지스트막과 하부전극용 폴리실리콘층이 동일한 높이를 갖도록 한다. 이에 따라, 하부전극의 높이가 웨이퍼 전면에 걸쳐 균일하게 형성되게 되어 캐패시터의 용량을 안정적으로 확보할 수 있다. 또한, 하부전극용 폴리실리콘층의 상부를 식각한 후 그 형태가 날카롭게 되는 것을 방지할 수 있으므로, 폴리실리콘 브로큰(broken)에 의한 브릿지의 발생이 억제되고, 이에 따라 소자의 수율을 향상시킬 수 있는 효과가 있다.As described above, the present invention polishes the photoresist film embedded between the lower electrodes by the touch polishing method, so that the photoresist film between the lower electrodes and the polysilicon layer for the lower electrode have the same height. Accordingly, the height of the lower electrode is uniformly formed over the entire surface of the wafer, so that the capacitance of the capacitor can be secured. In addition, since the shape of the lower portion of the polysilicon layer for lower electrodes can be etched away, it is possible to prevent the shape from being sharpened. Therefore, the occurrence of bridges due to polysilicon broken can be suppressed, thereby improving the yield of devices It works.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990061783A KR20010063707A (en) | 1999-12-24 | 1999-12-24 | Method of manufacturing a capacitor in a semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990061783A KR20010063707A (en) | 1999-12-24 | 1999-12-24 | Method of manufacturing a capacitor in a semiconductor device |
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| KR20010063707A true KR20010063707A (en) | 2001-07-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019990061783A KR20010063707A (en) | 1999-12-24 | 1999-12-24 | Method of manufacturing a capacitor in a semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030018743A (en) * | 2001-08-31 | 2003-03-06 | 삼성전자주식회사 | Method for fabricating semiconductor device having capacitor |
| KR100849078B1 (en) * | 2002-06-21 | 2008-07-30 | 매그나칩 반도체 유한회사 | Method for forming metal insalator metal capacitor of semiconductor device |
| KR100955922B1 (en) * | 2003-04-03 | 2010-05-03 | 주식회사 하이닉스반도체 | Method for fabricating capacitor in semiconductor device |
-
1999
- 1999-12-24 KR KR1019990061783A patent/KR20010063707A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030018743A (en) * | 2001-08-31 | 2003-03-06 | 삼성전자주식회사 | Method for fabricating semiconductor device having capacitor |
| KR100849078B1 (en) * | 2002-06-21 | 2008-07-30 | 매그나칩 반도체 유한회사 | Method for forming metal insalator metal capacitor of semiconductor device |
| KR100955922B1 (en) * | 2003-04-03 | 2010-05-03 | 주식회사 하이닉스반도체 | Method for fabricating capacitor in semiconductor device |
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