KR100641083B1 - Method for forming a contact portion of storage node electrode - Google Patents

Abstract

The present invention relates to a method of manufacturing a contact portion for a storage node electrode of a semiconductor device, and in particular, the method forms a sacrificial insulating film and an antireflection film for defining a storage node electrode pattern region in a structure of a semiconductor substrate, After forming the anti-reflective material and the etch selectivity on the top of the anti-reflection film only in the outer region except the substrate region to be formed, a photoresist pattern for the storage node electrode is formed on the structure and the etching process using the same is performed. Only the anti-reflection film and the sacrificial insulating film of the formed substrate region are etched to form the contact portion for the storage node electrode, and then the photoresist pattern is removed. Therefore, in the present invention, even if a poor photoresist pattern is formed in the region where the capacitor is not formed, the added anti-etching film prevents etching of the anti-reflection film and the sacrificial insulating film to increase the yield of the manufacturing process.

Description

Method for forming a contact portion for a storage node electrode of a semiconductor device             

1A to 1C are process flowcharts for forming a contact portion manufacturing method for a storage node electrode of a semiconductor device according to the prior art;

2A to 2E are process flowcharts for explaining a method of manufacturing a contact portion for a storage node electrode of a semiconductor device according to the present invention;

  -Explanation of symbols on the main parts of the drawing-

100: lower structure of the semiconductor substrate 12: interlayer insulating film

104: contact plug 106: sacrificial insulating film

108: etching prevention film 110: photoresist pattern

112: contact portion for a storage node electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, to a method for manufacturing a contact portion for a storage node electrode of a semiconductor device capable of increasing a yield of a storage node electrode manufacturing process for a memory device such as a DRAM.

At present, research and development on the reduction of the cell area and the reduction of the operating voltage have been actively conducted in order to achieve high integration of semiconductor devices. In addition, since the area of the capacitor decreases rapidly as the integration of semiconductor devices increases, the charge required for the operation of the memory device, that is, the capacitance secured in the unit area must be further increased.

Meanwhile, a basic structure of a capacitor used in a memory cell is composed of a storage node electrode, a dielectric film, and a plate node electrode. Capacitors having such a structure have a first thin dielectric film thickness to increase the fixed capacitance in a small area, increase the effective area through the structure of the three-dimensional capacitor, or use a high dielectric constant material. Some conditions, such as forming a dielectric film, must be satisfied.

Capacitors in semiconductor devices generally have a better dielectric film with less leakage current at a given dielectric film thickness and larger breakdown voltage, but Fowler-Nordheim when the dielectric film is thinned to 100 kΩ or less. This method is limited because the leakage current increases due to tunneling, which lowers the reliability.

In addition, a method of using a material having a high dielectric constant in a capacitor of a memory cell is being studied continuously so that a fixed capacitance can be sufficiently secured even in a narrow area of a highly integrated memory device.

Finally, in order to increase the effective area of the capacitor, a method of increasing the cross-sectional area of the storage node electrode in a three-dimensional structure is in progress.

However, in general, a step occurs due to a difference between the lower structure in the substrate region where the capacitor is formed and the substrate region where the capacitor is not formed. As a result, a problem due to the step occurs in the manufacturing process of the storage node electrode.

1A to 1C are flowcharts illustrating a method of manufacturing a contact portion for a storage node electrode of a semiconductor device according to the prior art. In the drawing, A represents a substrate region in which a capacitor is formed, and B represents a substrate region in which a capacitor is not formed.

First, an element isolation process is performed on the semiconductor substrate 10 and an element process having a gate electrode, a source / drain junction, and a bit line (not shown) is performed on the substrate.

As shown in FIG. 1A, an interlayer insulating film 12 is formed on the entire surface of the structure 10 of the substrate on which the device is formed, and then contact holes are formed by a photo and etching process and a conductive material is buried to form a source / drain junction at the bottom. And a contact plug 14 connected to it. An oxide film is thickly deposited as a sacrificial insulating film 16 for defining the pattern of the storage node electrode on the interlayer insulating film 12, and an antireflection film 18 is formed thereon.

As shown in FIG. 1B, photoresist patterns 20 and 21 for storage node electrodes are formed on the anti-reflection film 18. At this time, there is a step between the substrate region A in which the capacitor is formed and the substrate region B in which the capacitor is not formed. As a result, in the photolithography step for forming the photoresist patterns 20 and 21, between the two regions, The difference in focus causes the focus to change. Therefore, depending on which area to focus on, a relatively different area is defocused. In general, defocus occurs in a region B in which no capacitor is formed. Thus, as shown, the photoresist pattern 20 of the substrate region A in which the capacitor is formed is formed in a good state, but the photoresist pattern 21 of the substrate region B in which the capacitor is not formed is a desired pattern. Have difficulty getting it.

Subsequently, as shown in FIG. 1C, the anti-reflection film 18 and the sacrificial insulating film 16 are etched using the photoresist patterns 20 and 21 as masks to form contact portions for storage node electrodes. Then, the photoresist patterns 20 and 21 are removed, and the etching residue and the anti-reflection film 18 are removed by a cleaning process.

Then, the doped polysilicon is deposited as a conductive material on the resultant formed contact portion, and the storage node electrode 22 is formed by a chemical mechanical polishing process. However, in the storage node electrode manufacturing process, the substrate region B in which the capacitor is not formed is difficult to etch the sacrificial insulating layer in a desired shape due to the defect of the photoresist pattern 21, so that the lower contact plug is completely exposed. It was often not.
In this case, the adhesive strength of the contact plug and the polysilicon is weak, so that the polysilicon film falls during the chemical mechanical polishing process of the polysilicon. The fallen polysilicon film acts as a bridge between the storage node electrodes, thereby lowering the yield of the device.

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In order to solve the problems of the prior art, by forming an etch stop layer only on the top of the anti-reflection film of the substrate area in which the capacitor is not formed, and proceeding the photo process for the storage node electrode pattern, the capacitor is formed during the photo process The present invention provides a method of manufacturing a storage node electrode contact portion of a semiconductor device, in which an added etch barrier prevents etching of an underlying structure even when a bad photoresist pattern is formed in a non-substrate region, thereby forming a desired storage node electrode contact portion. .

In order to achieve the above object, the present invention provides a method of manufacturing a storage node electrode of a semiconductor device, the method comprising: forming a sacrificial insulating film for defining a storage node electrode pattern region on a structure of a semiconductor substrate; Depositing an anti-reflective material and an etch selectivity on an upper portion of the anti-reflective film only in the outer region except the substrate region where the capacitor is formed, and forming a photoresist pattern for the storage node electrode on the structure; Performing an etching process using the photoresist pattern to etch only the anti-reflection film and the sacrificial insulating film of the substrate region where the capacitor is formed to form a contact for the storage node electrode, and removing the photoresist pattern.

According to the present invention, by selectively forming an etch stop layer only on the anti-reflection film of the substrate region where the capacitor is not formed and proceeding the photo process for the storage node electrode pattern, a poor photoresist in the substrate region where the capacitor is not formed during the photo process Even if the pattern is formed, the added anti-etching film prevents etching of the lower structure to prevent a decrease in yield due to a poor photoresist pattern.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are flowcharts illustrating a method of manufacturing a contact portion for a storage node electrode of a semiconductor device according to the present invention. Here again, reference numeral A denotes a substrate region in which a capacitor is formed, and B denotes a substrate region in which a capacitor is not formed.

First, a device isolation process is performed on the semiconductor substrate 10, and a device process including a gate electrode, a source / drain junction, and a bit line (not shown) is performed on the substrate.

As shown in FIG. 2A, an interlayer insulating film 102 is formed on the entire surface of the structure 100 of the substrate on which the device is formed, and then contact holes are formed through photolithography and etching processes, and a conductive material is buried to form a lower source / drain junction. And a contact plug 104 connected to it. An oxide film is thickly deposited as a sacrificial insulating film 106 to define a pattern of the storage node electrode on the interlayer insulating film 102, and an anti-reflection film 108 is formed thereon.

Next, as shown in FIG. 2B, the etch stop layer 110 is deposited on the antireflection layer 108 only in the outer region B except the substrate area A in which the capacitor is formed in the structure. In this case, the etch stop layer 110 should have a selective etching ratio with respect to the anti-reflection film so as to become a barrier during the etching process of the sacrificial insulating film for the storage node electrode. Therefore, the etch stop film 110 is deposited as a thin film (polysilicon film) 300-500 Å, or nitride film 500-1000 Å. Alternatively, the etch stop layer 110 deposits an organic bottom anti-reflective coating material at a thickness of 1000 Å or more instead of the thin film. When the etch stop layer 110 is formed of the organic lower reflective material, the etch ratio may be controlled by tuning the inorganic antireflective layer 108 during the etching process of the sacrificial insulating layer.

As shown in FIG. 2C, a photoresist using a storage node electrode mask is performed on the structure to form a photoresist pattern 112 for a storage node electrode.

As shown in FIG. 2D, the etching process using the photoresist pattern 112 is performed to etch only the sacrificial insulating layer 106 of the substrate region A where the capacitor is formed to form the contact portion 114 for the storage node electrode. do. At this time, in the substrate region B in which the capacitor is not formed, the etching process is not performed by the etch stop layer 110. That is, the etch stop layer 110 prevents etching of the sacrificial insulating layer 106 due to the poor photoresist pattern 112 formed during the exposure process.

Then, as shown in FIG. 2E, the photoresist pattern 112 is removed. Then, the etch stop layer 110 and the anti-reflection film 108 are removed.

Next, although not shown in the drawing, the doped polysilicon is deposited as a conductive material on the resultant in which the contact portion 114 is formed, and the storage node electrode is formed by a chemical mechanical polishing process.

The present invention selectively forms an etch stop layer only on the anti-reflection film of the substrate area where the capacitor is not formed and proceeds the photo process for the storage node electrode pattern, so that a poor photoresist pattern on the substrate area where the capacitor is not formed during the photo process Even if this is formed, the etch stop layer added during the etching process of the sacrificial insulating layer prevents etching of the sacrificial insulating layer in the substrate region where the capacitor is not formed.

Therefore, in the prior art, in the sacrificial insulating film of the substrate region where the capacitor is not formed due to the poor photoresist pattern, the contact portion is not etched to the extent that the contact plug is completely exposed, thereby preventing a decrease in the yield of the manufacturing process.

In addition, the present invention can improve the yield of the manufacturing process of the semiconductor device having a storage node electrode by forming an etch barrier layer in the substrate region where the capacitor is not formed without complex map modification in the mask process for the storage node electrode. There is an advantage.

Claims (2)

Forming a sacrificial insulating film for defining a storage node electrode pattern region in a structure of the semiconductor substrate; Forming an anti-reflection film on the sacrificial insulating film; Depositing an etch stop layer having an etch selectivity with the anti-reflective material on the anti-reflective film only in the outer region except the substrate area where the capacitor is formed; Forming a photoresist pattern for a storage node electrode on the structure; Etching the anti-reflection film and the sacrificial insulating film in the substrate area where the capacitor is formed by performing an etching process using the photoresist pattern to form a contact for a storage node electrode; And Removing the photoresist pattern; and manufacturing a contact portion for a storage node electrode of a semiconductor device. The method of claim 1, wherein the etch stop layer, And a method of depositing a polysilicon film with a thickness of 300 to 500 GPa, a method of depositing a nitride film with a thickness of 500 to 1000 GPa, or a method of depositing an organic lower reflective material at a thickness of 1000 GPa or more. A method of manufacturing a contact portion for a storage node electrode of a semiconductor device.

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