KR20050033689A - Method for forming capacitor of semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a capacitor of a semiconductor device capable of preventing the occurrence of defects and the reduction of capacitance in forming a storage electrode. The disclosed method includes sequentially forming an etch stop film and a cap oxide film on a semiconductor substrate having a poly plug, etching the cap oxide film to expose a portion of the etch stop film on the poly plug, and etching Depositing a spacer nitride film on the cap oxide film; forming a trench to expose the poly plug by etching the cap nitride film upper surface and the spacer nitride film and the etch stop film portion on the poly plug; Recessing a predetermined thickness of the substrate, depositing a polysilicon film for a storage electrode on the substrate resultant to the step, depositing a barrier oxide film to fill a trench on the polysilicon film, and depositing the spacer nitride film. Polysilicon on barrier oxide film and cap oxide film by using CMP film formation to form a concave storage electrode, removing the barrier oxide film buried in the trench, growing an HSG on the inner surface of the concave storage electrode, and a dielectric film on the storage electrode; Sequentially forming plate electrodes.

Description

Method for forming capacitor of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device, and more particularly, to a method for preventing the occurrence of defects and a reduction in capacity during storage electrode formation.

As the demand for semiconductor memory devices has soared, various techniques for obtaining high capacity capacitors have been proposed. The capacitor has a structure in which a dielectric film is interposed between a storage node and a plate node, the capacitance of which is proportional to the electrode surface area and the dielectric constant of the dielectric film, and the spacing between the electrodes, that is, the dielectric. Inversely proportional to the thickness of the membrane.

Therefore, in the process of manufacturing a semiconductor device that is extremely miniaturized, in order to secure a certain amount or more of capacity for the semiconductor device to operate properly, a method such as increasing the electrode surface area or using a dielectric film having a high dielectric constant is required.

A concave type is currently applied to increase the electrode surface area, and in addition, the electrode surface area is formed by forming a HSG (Hemi-spherical Silicon Grain) using a meta-stable poly silicon (MPS) process on the storage electrode surface. Maximizing.

Hereinafter, a conventional capacitor forming method will be briefly described with reference to FIGS. 1A to 1E.

Referring to FIG. 1A, a semiconductor substrate 1 on which a poly plug 3 is formed is prepared according to a known process. Then, an etch stop film 4 made of a nitride film and a cap oxide film 5 are sequentially deposited on the interlayer insulating film 2 including the poly plug 3. At this time, the cap oxide film 5 is deposited to a thickness corresponding to the desired electrode height. Subsequently, after depositing a hard mask film 6 made of polysilicon on the cap oxide film 5, the photoresist film pattern 7 exposing an upper portion of the poly plug 3 is exposed on the hard mask film 6. Form.

Referring to FIG. 1B, after etching the hard mask layer below using the photoresist pattern, the etch stop layer 4 is exposed using the etched hard mask layer and the photoresist pattern remaining thereon as an etch barrier. The cap oxide film 35 is etched, and subsequently, the exposed etch stop film 4 is etched to form a trench that exposes the poly plug 3. Then, after removing the hard mask used as an etch barrier and the photoresist pattern thereon, a polysilicon film 8 for storage electrodes is deposited on the trench and cap oxide film 5. In this case, the polysilicon film 8 is deposited as a double layer of a doped polysilicon film and an undoped polysilicon film.

Referring to FIG. 1C, in order to avoid the problem that abrasive particles in the slurry supplied in a subsequent CMP process and abrasive by-products generated during the process are not introduced into the trench and removed in a subsequent cleaning process, the substrate is placed on the substrate resultant. The photosensitive film 9 is applied.

Referring to FIG. 1D, CMP of a substrate resultant is performed using the photoresist as a barrier, and through this, the polysilicon film portion formed on the cap oxide film 5 is removed to form a plurality of concave storage electrodes 8a. At the same time, the adjacent storage electrodes are separated.

Thereafter, the photoresist film used as the CMP barrier is stripped according to a known process.

Referring to FIG. 1E, the HSG 10 is formed on the surface of the storage electrode 8a by performing an MPS process, and then doping is performed.

Subsequently, although not shown, a capacitor is formed by sequentially forming a dielectric film and a plate electrode on the storage electrode 8a having the HSG 10 formed on the surface thereof.

However, according to the conventional capacitor forming method as described above, when the CMP process is applied to separate the storage electrodes, the polishing rate difference between the polysilicon film and the cap oxide film, which is the storage electrode material, is shown in FIG. 1D. As can be seen, dishing occurs on the surface of the cap oxide film 5, which becomes more severe as a result of the subsequent cleaning process, so that in the subsequent MPS process, as shown in FIG. 1E, the HSG 10 Is overgrown to the outside of the storage electrode 8a, resulting in a bridge between adjacent storage electrodes 8a, resulting in device fail.

In addition, in the CMP process to separate the storage electrodes, a photoresist barrier is generally applied. In the trend of deepening the trench depth according to the miniaturization of the device, the photoresist barrier is not completely removed in the strip process, so that the photoresist barrier is subsequently removed. During the cleaning process, as shown in FIG. 2, the photoresist residue defect 20 is generated, which also causes device failure.

In addition, when the conventional oxide film removal slurry is used in the separation between the storage electrodes using the CMP process, the difference in polishing rate between the storage electrode material and the cap oxide material is not so large that the cap oxide film under the storage electrode is used as the polishing stop film. It does not perform a proper role, and this causes a reduction in the capacitor capacity corresponding to the height lost due to the height loss of the cap oxide layer in the storage electrode separation process.

Accordingly, an object of the present invention is to provide a method for forming a capacitor of a semiconductor device capable of preventing device failure due to a CMP process applied to separate storage electrodes. have.

In addition, another object of the present invention is to provide a method for forming a capacitor of a semiconductor device capable of preventing a loss of a cap oxide film and a reduction in capacity due to a loss of a storage electrode height.

In order to achieve the above object, the present invention comprises the steps of sequentially forming an etch stop film and a cap oxide film on a semiconductor substrate having a poly plug; Etching the cap oxide film to expose a portion of the etch stop film on the poly plug; Depositing a spacer nitride film on the etched cap oxide film; Etching the cap nitride layer upper surface and the spacer nitride layer and the etch stop layer on the poly plug to form a trench to expose the poly plug; Recessing a predetermined thickness of the exposed poly plug surface; Depositing a polysilicon film for a storage electrode on the substrate resultant up to this step; Depositing a barrier oxide film to bury a trench on the polysilicon film; Forming a concave storage electrode by CMP of the barrier oxide film and the polysilicon film on the cap oxide film using the spacer nitride film as the polishing stop film; Removing the barrier oxide film embedded in the trench; Growing an HSG on an inner surface of the concave storage electrode; And forming a dielectric film and a plate electrode sequentially on the storage electrode.

Here, the cap oxide film may be formed in a single layer or a double layer structure, in the case of forming a double layer structure, the lower cap oxide film uses a fast etching speed PSG film or BPSG film and the upper cap oxide film is a slow etching speed PE-TEOS Use a membrane. At this time, the lower cap oxide film is deposited to a thickness of 3000 ~ 7000 Å, the upper cap oxide film is deposited to 13000 ~ 22000 Å thickness.

The spacer nitride film is deposited at a thickness of 50 to 100 GPa at 550 to 650 캜.

Cleaning the substrate resultant to improve contact resistance after forming the trench, and before recessing the poly plug surface, wherein the cleaning comprises 20: 1 to 300: 1 BOE or 50: Run for 2-20 seconds with 1-500: 1 DHF solution.

The step of recessing the surface of the poly plug is carried out such that NH 4 OH and H 2 O are mixed in a volume ratio of 1:10 and wet etching using a solution having a temperature of 25 to 26 ° C. to 200 to 2000 Pa.

The barrier oxide film is formed of an O3 TEOS film or an SOG film. In this case, the O3 TEOS film is deposited to a thickness of 2500 to 5000 GPa, and the SOG film is deposited to a thickness of 3000 to 7000 GPa.

Removing the barrier oxide layer is performed by wet etching using a 9: 1 BOE solution.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3G are cross-sectional views illustrating processes of forming a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 3A, a semiconductor substrate 31 on which a poly plug 33 is formed is prepared according to a known process. Thereafter, an etch stop film 34 made of a nitride film is deposited on the interlayer insulating film 32 including the poly plug 33 on the substrate 31 to a thickness of 400 to 1000 Å, and then the etch stop film 34 is formed. The cap oxide film 35 is deposited on it.

Here, the cap oxide film 35 may be formed in a single layer structure having a thickness corresponding to a desired electrode height, for example, 16000 to 29000 mm thick, or may have a high height of the cap oxide film to be etched, and thus the bottom of the storage electrode after etching. In order to prevent the CD from becoming smaller, a double layer structure of materials having different etching rates is formed. In the case of forming a double layer structure, the lower cap oxide film uses a PSG film or a BPSG film having a high etching rate, and the deposition thickness thereof is about 3000 to 7000 Pa. The deposition thickness is about 13000-22000 kPa.

Next, a hard mask film 36 made of, for example, a polysilicon film is deposited on the cap oxide film 35 to a thickness of 2500 to 3500 GPa, and then, on the hard mask film 36, a well-known photo process is performed. Accordingly, the photosensitive film pattern 37 exposing the hard mask film portion on the poly plug 33 is formed.

Referring to FIG. 3B, after the hard mask layer is etched using the photoresist pattern, the etch stop layer 34 is exposed using the etched hard mask layer and the photoresist pattern remaining thereon as an etch barrier. The cap oxide film 35 is etched. Then, the hard mask used as an etching barrier and the photoresist pattern thereon are removed.

Subsequently, the spacer nitride layer 38 may be formed at 50 ° C. at 550 to 650 ° C. to prevent HSG from growing out of the storage electrode in the MPS process while using the polishing stop layer in the subsequent CMP process on the etched cap oxide layer 35. It deposits in thickness of about -100 GPa. In this case, the spacer nitride film 38 may not be removed together when the cap oxide layer is removed between the storage electrodes due to the difference in wet etching rates when the deposition temperature is 650 ° C. or higher. It should be controlled as follows.

Referring to FIG. 3C, the poly plug exposed by etching the spacer nitride layer on the etch stop layer 34 and the spacer nitride layer portion on the etch stop layer 34 by etching the substrate result by dry etching. A portion of the etching stop film made of a nitride film on the substrate 33 is etched to form a trench 39 exposing the poly plug 33. The substrate result is then cleaned with 20: 1 to 300: 1 BOE or 50: 1 to 500: 1 DHF (Dilluted HF) solution for 2 to 20 seconds to improve contact resistance.

Here, in the etching of the etch stop layer 34 in connection with the formation of the spacer nitride layer 38 on the sidewall of the etched cap oxide layer 35, that is, the portion where the storage electrode is to be formed later, and the contact resistance In the cleaning process, the enlargement of the bowing area and the enlargement of the story electrode hole size due to the loss of the upper end of the cap oxide film are prevented, and thus, the occurrence of bridges between neighboring storage electrodes can be prevented.

Referring to FIG. 3D, some thickness of the exposed poly plug 33 surface is recessed to create a supporter structure of the storage electrode to be subsequently formed. Here, the recesses of the poly plug 33 are mixed by wet etching using a solution in which NH 4 OH and H 2 O are mixed at a volume ratio of 1:10 and the temperature is 25 to 26 ° C., and the recess is about 200 to 2000 kPa.

Referring to FIG. 3E, a polysilicon film 40 is deposited to a thickness of 350 to 550 Å as a conductive film for the storage electrode on the substrate resultant up to this step. In this case, although not shown in detail, the polysilicon film 40 is deposited in a laminated structure of doped polysilicon and undoped polysilicon, and the doped polysilicon is 100 to 150 micron thick and undoped polysilicon. Is deposited to a thickness of 250-400 mm 3.

Then, the barrier oxide film 41 is deposited on the polysilicon film 40 so as to completely fill the trench 39. Here, the barrier oxide layer 41 is deposited in place of a conventional photoresist layer for use as a barrier in a subsequent CMP process for separation between storage electrodes, and a gap fill capability and a wetness of the cap oxide layer 35 are used. In consideration of the difference in etching speed, the film is formed of an O3 TEOS film or an SOG film. In this case, the O3 TEOS film is deposited to a thickness of 2500 to 5000 kPa, and the SOG film is deposited to a thickness of 3000 to 7000 kPa.

Referring to FIG. 3F, the surfaces of the barrier oxide film 41 and the polysilicon film 40 are CMP until the cap oxide film 35 is exposed, thereby forming the storage electrodes 40a and inter-electrodes. To separate. At this time, in performing the CMP process, the spacer nitride film 38 remaining on the sidewall of the trench 39 is used as the polishing stop film.

Here, in performing the CMP process, conventionally, the polishing rate of the oxide film and the polysilicon film is the same, so that the loss of the upper surface of the polysilicon film to be the storage electrode occurs later, but in the present invention, the oxide film and the polysilicon film and the polishing selectivity Since the CMP process is performed using a nitride film having a polishing stop film, the loss of the upper surface of the polysilicon film to be a storage electrode is suppressed.

Referring to FIG. 3G, a barrier oxide layer between the storage electrodes 40a is removed by performing wet etching on a substrate resultant using a 9: 1 BOE solution. Then, the MPS process for the storage electrode 40a is performed to grow the HSG 42 only inside the trench.

Here, the photoresist residue defect generated when the photoresist barrier is removed is caused by the reaction of the carbon, which is a polymer component contained in the photoresist, with the CMP slurry. No defects will occur.

Subsequently, although not shown, a dielectric film and a plate electrode are sequentially formed on the storage electrode 40a to complete the formation of a capacitor according to the present invention.

As described above, the present invention can prevent the surface loss of the storage electrode in the CMP process by depositing a nitride film which can be used as a polishing stop film in the subsequent CMP process after etching the cap oxide film, thereby, The desired capacitance can be secured.

In addition, the present invention can prevent the expansion of the upper end portion by the cap oxide film loss in the etching stop film etching and cleaning process by forming the nitride film, it is possible to prevent the generation of bridges between neighboring storage electrodes.

In addition, the present invention can strengthen the support structure of the storage electrode by recessing the surface of the poly plug.

In addition, since the present invention uses an oxide film as a barrier material in the CMP process, it is possible to fundamentally solve defects caused by the barrier material, and in particular, a dedicated equipment must be used in the CMP process to remove the existing photoresist residue defects. This can reduce the burden on the equipment and thus benefit from the operation of the equipment.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

1A to 1E are cross-sectional views of processes for explaining a method of forming a conventional capacitor.

Figure 2 is a photograph for explaining the conventional problem.

3A to 3G are cross-sectional views of processes for explaining a method of forming a capacitor according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

31 semiconductor substrate 32 interlayer insulating film

33: poly plug 34: etch stop film

35: cap oxide film 36: hard mask film

37 photosensitive film pattern 38 spacer spacer film

39: trench 40: polysilicon film

40a: storage electrode 41: barrier oxide film

42: HSG

Claims (11)

Sequentially forming an etch stop layer and a cap oxide layer on the semiconductor substrate having a poly plug; Etching the cap oxide film to expose a portion of the etch stop film on the poly plug; Depositing a spacer nitride film on the etched cap oxide film; Etching the cap nitride layer upper surface and the spacer nitride layer and the etch stop layer on the poly plug to form a trench to expose the poly plug; Recessing a predetermined thickness of the exposed poly plug surface; Depositing a polysilicon film for a storage electrode on the substrate resultant up to this step; Depositing a barrier oxide film to bury a trench on the polysilicon film; Forming a concave storage electrode by CMP of the barrier oxide film and the polysilicon film on the cap oxide film using the spacer nitride film as the polishing stop film; Removing the barrier oxide film embedded in the trench; Growing an HSG on an inner surface of the concave storage electrode; And And sequentially forming a dielectric film and a plate electrode on the storage electrode. The method of claim 1, wherein the cap oxide film is formed in a single layer or a double layer structure. 3. The method of claim 2, wherein the cap oxide film is formed of a double layer structure consisting of a PSG film or a lower cap oxide film of the BPSG film with a high etching rate and an upper cap oxide film of a PE-TEOS film with a slow etching speed Way. The method of claim 3, wherein the lower cap oxide film is deposited at a thickness of 3000 to 7000 GPa, and the upper cap oxide film is deposited at a thickness of 13000 to 22000 GPa. The method of claim 1, wherein the spacer nitride film is deposited at a thickness of 50 to 100 GPa at 550 to 650 캜. 2. The method of claim 1, further comprising: cleaning the substrate resultant to improve contact resistance after forming the trench and before recessing the poly plug surface. Way. 7. The method of claim 6, wherein the cleaning is performed for 20 to 20 seconds with a 20: 1 to 300: 1 BOE or 50: 1 to 500: 1 DHF solution. The method of claim 1, wherein the recessing of the surface of the poly plug is performed by wet etching using a solution having a mixture of NH 4 OH and H 2 O at a volume ratio of 1:10 and a temperature of 25 to 26 ° C. A method for forming a capacitor of a semiconductor device, characterized in that. The method of claim 1, wherein the barrier oxide film is formed of an O3 TEOS film or an SOG film. 10. The method of claim 9, wherein the O3 TEOS film is deposited to a thickness of 2500 to 5000 GPa, and the SOG film is deposited to a thickness of 3000 to 7000 GPa. The method of claim 1, wherein the removing of the barrier oxide layer is performed by wet etching using a 9: 1 BOE solution.