KR19990005486A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents
Capacitor Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR19990005486A KR19990005486A KR1019970029684A KR19970029684A KR19990005486A KR 19990005486 A KR19990005486 A KR 19990005486A KR 1019970029684 A KR1019970029684 A KR 1019970029684A KR 19970029684 A KR19970029684 A KR 19970029684A KR 19990005486 A KR19990005486 A KR 19990005486A
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- layer
- sacrificial layer
- sacrificial
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000003990 capacitor Substances 0.000 title abstract description 19
- 238000004519 manufacturing process Methods 0.000 title abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 39
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 239000011229 interlayer Substances 0.000 claims description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 2
- 229910052698 phosphorus Inorganic materials 0.000 claims 2
- 239000011574 phosphorus Substances 0.000 claims 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 1
- 229910052796 boron Inorganic materials 0.000 claims 1
- 239000011521 glass Substances 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract description 2
- 239000007789 gas Substances 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Inorganic Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
본 발명은 반도체 제조 분야에 관한 것임.The present invention relates to the field of semiconductor manufacturing.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
본 발명은 캐패시터 간의 브릿지 현상을 방지하고, 차세대 고집적 반도체 장치의 충분한 정전용량을 확보하는 반도체 장치의 캐패시터 제조방법을 제공하고자 함.An object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device, which prevents a bridge phenomenon between capacitors and ensures sufficient capacitance of a next-generation highly integrated semiconductor device.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
본 발명은 전하저장 전극 콘택 주변 부위에 고랑을 형성하고, 이후 PSG막 및 SOG막을 사용한 희생막의 증착 및 식각 특성을 이용하여 H 형상의 실린더형 캐패시터를 형성함.The present invention forms a furrow on the periphery of the charge storage electrode contact, and then forms an H-shaped cylindrical capacitor using deposition and etching characteristics of the sacrificial film using the PSG film and the SOG film.
4. 발명의 중요한 용도4. Important uses of the invention
차세대 고집적 반도체 장치 제조에 이용됨.Used to manufacture next generation highly integrated semiconductor devices.
Description
본 발명은 반도체 제조 분야에 관한 것으로, 특히 차세대 고집적 반도체 장치에 적용할 수 있는 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method of manufacturing a capacitor that can be applied to a next-generation highly integrated semiconductor device.
일반적으로, 반도체 장치의 고집적화에 따라 반도체 장치의 동작 특성에 적합한 정전용량을 확보하기 위하여 전하저장 전극의 표면적을 충분히 확보해야 한다.In general, the surface area of the charge storage electrode should be sufficiently secured in order to secure the capacitance suitable for the operating characteristics of the semiconductor device due to the high integration of the semiconductor device.
최근까지 가장 일반화된 캐패시터는 측벽 스페이서를 구비하여 어느 정도의 정전용량을 확보할 수 있는 실린더형 캐패시터라고 볼 수 있다. 실린더형 캐패시터는 2단계의 폴리실리콘막 증착 및 식각 공정을 포함하게 되는데, 덜 식각된 폴리실리콘막 또는 하부층의 결함으로 인하여 캐패시터 간의 브릿지(bridge)가 종종 발생한다.Until recently, the most common capacitor can be regarded as a cylindrical capacitor having sidewall spacers to secure a certain amount of capacitance. Cylindrical capacitors include a two-step polysilicon film deposition and etching process, with bridges between capacitors often occurring due to defects in the less etched polysilicon film or underlayer.
또한, 반도체 장치의 고집적화가 가속됨에 따라 실린더형 캐패시터로는 차세대 고집적 반도체 장치의 동작 특성을 만족시키는 충분한 정전용량을 확보할 수 없게 되었다.In addition, as the integration of semiconductor devices is accelerated, the cylindrical capacitors cannot secure sufficient capacitance to satisfy the operating characteristics of the next generation of highly integrated semiconductor devices.
본 발명은 캐패시터 간의 브릿지 현상을 방지하고, 차세대 고집적 반도체 장치의 충분한 정전용량을 확보하는 반도체 장치의 캐패시터 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device, which prevents a bridge phenomenon between capacitors and ensures sufficient capacitance of a next-generation highly integrated semiconductor device.
도 1a 내지 도 1k는 본 발명의 일실시예에 따른 캐패시터 제조 공정도.Figure 1a to 1k is a capacitor manufacturing process according to an embodiment of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
10 : 실리콘 기판 11 : BPSG막10 silicon substrate 11 BPSG film
12,18 : PSG막 13,16,19 : 포토레지스트 패턴12,18 PSG film 13,16,19 photoresist pattern
14 : SOG막 15 : 자연산화막14: SOG film 15: natural oxide film
17,20 : 폴리실리콘막17,20: polysilicon film
상기와 같은 목적을 달성하기 위하여 본 발명의 캐패시터 제조방법은 소정의 하부층이 형성된 반도체 기판 상부에 소정의 층간 절연막을 형성하는 제1 단계; 상기 층간 절연막 상부에 제1 희생막을 소정 두께로 형성하는 제2 단계; 전하저장 전극 콘택홀 형성 부분의 주변의 상기 제1 희생막을 선택적으로 부분 식각하여 상기 콘택홀 형성 부분을 둘러싸는 고랑을 형성하는 제3 단계; 상기 고랑 내에 제2 희생막을 채우는 제4 단계; 상기 콘택홀을 형성하는 제5 단계; 전체구조 상부에 제1 전도막 및 제3 희생막을 차례로 형성하는 제6 단계; 상기 제1 전도막 및 상기 제3 희생막을 패터닝하되, 상기 고랑 상부에 그 일부분이 오버랩되도록하는 제7 단계; 상기 제2 희생막을 등방성 식각하여 패터닝된 상기 제1 전도막 하부에 언더컷 부위를 형성하는 제8 단계; 전체구조 상부에 제2 전도막을 형성하고 이를 전면성 식각하여 패터닝된 상기 제1 전도막 측벽 부위에 스페이서를 형성하는 제9 단계; 및 상기 제1, 제2 및 제3 희생막을 제거하는 제10 단계를 포함하여 이루어진다.In order to achieve the above object, the capacitor manufacturing method of the present invention includes a first step of forming a predetermined interlayer insulating film on the semiconductor substrate formed with a predetermined lower layer; Forming a first sacrificial layer on the interlayer insulating layer to a predetermined thickness; A third step of selectively etching the first sacrificial layer around the charge storage electrode contact hole forming portion to form a groove surrounding the contact hole forming portion; Filling a second sacrificial layer into the furrow; A fifth step of forming the contact hole; A sixth step of sequentially forming a first conductive layer and a third sacrificial layer on the entire structure; A seventh step of patterning the first conductive layer and the third sacrificial layer, wherein a part of the first conductive layer and the third sacrificial layer overlap with each other; An eighth step of forming an undercut portion under the patterned first conductive layer by isotropically etching the second sacrificial layer; A ninth step of forming a spacer on the sidewall of the patterned first conductive layer by forming a second conductive layer on the entire structure and etching the entire surface; And a tenth step of removing the first, second, and third sacrificial layers.
이하, 첨부된 도면 도 1a 내지 도 1k를 참조하여 본 발명의 일실시예를 상술한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings, FIGS. 1A to 1K.
우선, 도 1a에 도시된 바와 같이 소정의 하부층 공정을 마친 실리콘 기판(10)상에 층간 절연막인 BPSG막(11)과 희생막인 PSG막(12)을 차례로 증착하고, 전하저장 전극 콘택 형성 부위에 소정 선폭을 갖는 포토레지스트 패턴(13)을 형성한 다음, 이를 식각 장벽으로하여 PSG막(12)을 소정 두께만큼 부분 식각하여 전하저장 전극 콘택홀 주변 부위에 고랑을 형성한다. 여기서, CxFy가스를 주 반응 가스로하여 식각하며, 포토레지스트 패턴(13)은 전하저장 전극 콘택홀의 선폭보다 큰 선폭을 가진 고립 패턴으로 형성된다.First, as shown in FIG. 1A, a BPSG film 11, which is an interlayer insulating film, and a PSG film 12, which is a sacrificial film, are sequentially deposited on the silicon substrate 10 that has undergone a predetermined lower layer process. After the photoresist pattern 13 having a predetermined line width is formed on the substrate, the PSG film 12 is partially etched by a predetermined thickness using the photoresist pattern 13 as an etching barrier to form grooves around the charge storage electrode contact hole. Here, the C x F y gas is etched as the main reaction gas, and the photoresist pattern 13 is formed as an isolated pattern having a line width larger than that of the charge storage electrode contact hole.
다음으로, 도 1b에 도시된 바와 같이 포토레지스트 패턴(13)을 제거하고, 전체구조 상부에 희생막인 SOG막(14)을 형성한 다음, CxFy가스 및 CHFx가스를 첨가한 Ar 가스 분위기에서 이를 에치백하여 SOG막(14)이 고랑 내에만 남도록 한다. 여기서, SOG막(14)의 에치백은 화학적·기계적 연마(CMP) 방식을 사용하여 수행할 수도 있다.Next, as shown in FIG. 1B, the photoresist pattern 13 is removed, an SOG film 14 as a sacrificial film is formed on the entire structure, and then Ar is added with C x F y gas and CHF x gas. It is etched back in a gas atmosphere so that the SOG film 14 remains only in the furrow. Here, the etch back of the SOG film 14 may be performed using a chemical mechanical polishing (CMP) method.
이어서, 도 1c에 도시된 바와 같이 전체구조 상부에 자연산화막(15)을 형성한다. 이때, 자연산화막(15)는 후속 포토레지스트 패턴 제거 공정시 SOG막(14)이 손실되는 것을 방지하기 위한 것이다.Subsequently, a natural oxide film 15 is formed on the entire structure as shown in FIG. 1C. At this time, the native oxide film 15 is to prevent the SOG film 14 from being lost during the subsequent photoresist pattern removal process.
계속하여, 도 1d에 도시된 바와 같이 자연산화막(15) 상부에 전하저장 전극 콘택홀 형성을 위한 포토레지스트 패턴(16)을 형성하고, 이를 식각 장벽으로하여 자연산화막(15), PSG막(12) 및 BPSG막(11)을 차례로 선택적 식각하여 전자저장 전극 콘택홀을 형성한다. 이때, 콘택홀 식각은 CxFy가스 및 CxHyFz 가스를 사용하며, 도시된 바와 같이 SOG막(14)는 드러나지 않는다.Subsequently, as shown in FIG. 1D, a photoresist pattern 16 for forming a charge storage electrode contact hole is formed on the native oxide layer 15, and the native oxide layer 15 and the PSG layer 12 are formed as an etching barrier. ) And the BPSG film 11 are sequentially etched sequentially to form an electron storage electrode contact hole. In this case, the contact hole etching uses a C x F y gas and a C x H y Fz gas, and as illustrated, the SOG film 14 is not exposed.
다음으로, 도 1e에 도시된 바와 같이 포토레지스트 패턴(16) 및 자연산화막(15)을 차례로 제거한다.Next, as shown in FIG. 1E, the photoresist pattern 16 and the natural oxide film 15 are sequentially removed.
이어서, 도 1f에 도시된 바와 같이 전체구조 상부에 전도막인 폴리실리콘막(17)과 희생막인 PSG막(18)을 차례로 증착한다.Subsequently, as shown in FIG. 1F, a polysilicon film 17 as a conductive film and a PSG film 18 as a sacrificial film are sequentially deposited on the entire structure.
다음으로, 도 1g에 도시된 바와 같이 PSG막(18) 상부에 전하저장 전극의 선폭을 정의하기 위한 포토레지스트 패턴(19)을 형성하고, 이를 식각장벽으로하여 PSG막(18) 및 폴리실리콘막(17)을 차례로 선택적 식각한다. 이때, PSG막(18)의 식각은 Ar 가스, CHFx가스 및 CFx가스를 사용하며, 폴리실리콘막(17)의 식각은 Clx등의 염소계 가스와 HBr 가스 등을 사용하여 이루어진다. 여기서, 정의된 폴리실리콘막(17)의 패턴은 도시된 바와 같이 SOG막(14) 상에 오버랩되도록 한다.Next, as shown in FIG. 1G, a photoresist pattern 19 is formed on the PSG film 18 to define the line width of the charge storage electrode, and the PSG film 18 and the polysilicon film are formed as an etch barrier. Selective etching of (17) in sequence. In this case, the PSG film 18 is etched using Ar gas, CHF x gas and CF x gas, and the polysilicon film 17 is etched using chlorine-based gas such as Cl x and HBr gas. Here, the pattern of the defined polysilicon film 17 is allowed to overlap on the SOG film 14 as shown.
계속하여, 도 1h에 도시된 바와 같이 O2가스를 사용하여 포토레지스트 패턴(19)을 제거한다. 이때, CF4가스를 더 첨가하여 포토레지스트 패턴(19)을 제거하게 되면, SOG막(14)의 식각 속도를 빨라지게 함으로써 도시된 바와 같이 SOG막(14)을 등방성 식각할 수 있게 되어 언더켯(undercut) 부위가 형성된다. 물론 이러한 SOG막(14)의 등방성 식각은 포토레지스트 패턴(19)의 제거와는 별도의 공정을 통해 이루어질 수 있다.Subsequently, the photoresist pattern 19 is removed using an O 2 gas as shown in FIG. 1H. In this case, when the CF 4 gas is further added to remove the photoresist pattern 19, the SOG film 14 may be isotropically etched as shown in the drawing by increasing the etching speed of the SOG film 14. (undercut) site is formed. Of course, the isotropic etching of the SOG film 14 may be performed through a separate process from the removal of the photoresist pattern 19.
다음으로, 도 1i에 도시된 바와 같이 전체구조 상부에 폴리실리콘막(20)을 증착한다.Next, as illustrated in FIG. 1I, a polysilicon film 20 is deposited on the entire structure.
이어서, 도 1j에 도시된 바와 같이 폴리실리콘막(20)를 전면성 식각함으로써 스페이서 패턴을 형성한다.Subsequently, as shown in FIG. 1J, the polysilicon film 20 is etched by the entire surface to form a spacer pattern.
끝으로, 도 1k에 도시된 바와 같이 희생막인 PSG막(12,18)을 습식 식각 방식으로 제거하여 전하저장 전극을 형성한다. 이때, 불산(HF) 계열의 습식 식각제가 사용되며, 역시 희생막인 SOG막(14)도 함께 제거 된다.Finally, as shown in FIG. 1K, the sacrificial film PSG films 12 and 18 are removed by a wet etching method to form a charge storage electrode. At this time, a hydrofluoric acid (HF) -based wet etchant is used, and the SOG film 14, which is also a sacrificial film, is also removed.
이후, 유전막 및 플레이트 전극을 통상적인 방식으로 형성함으로써 고집적 반도체 장치의 동작 특성을 지지할 수 있는 충분한 정전용량을 확보할 수 있는 캐패시터를 형성할 수 있다.Thereafter, by forming the dielectric film and the plate electrode in a conventional manner, it is possible to form a capacitor capable of ensuring sufficient capacitance to support the operating characteristics of the highly integrated semiconductor device.
또한, 본 발명에서는 희생막(도면에서 12,14,18에 해당함) 제거 공정을 통해 폴리실리콘막의 브릿지를 효과적으로 방지할 수 있으며, 희생막의 두께 및 형성 위치를 조절함으로써 캐패시터의 구조를 최적화할 수 있다.In addition, in the present invention, it is possible to effectively prevent the bridge of the polysilicon film through the sacrificial film (corresponding to 12, 14, 18 in the drawing), and to optimize the structure of the capacitor by adjusting the thickness and the formation position of the sacrificial film. .
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기한 바와 같이 본 발명은 실시하면 고집적 반도체 장치의 동작 특성을 지지할 수 있는 충분한 정전용량을 가지는 캐패시터를 제조할 수 있어 차세대 고집적 반도체 장치의 개발에 박차를 가할 수 있다. 또한, 본 발명은 종래의 실린더형 캐패시터에서 문제점으로 지적되었던 캐패시터 간의 브릿지를 방지할 수 있으며, 이로 인하여 반도체 장치의 신뢰도 및 수율 향상을 기대할 수 있다.As described above, according to the present invention, it is possible to manufacture a capacitor having a sufficient capacitance to support the operating characteristics of the highly integrated semiconductor device, thereby accelerating the development of the next generation highly integrated semiconductor device. In addition, the present invention can prevent the bridges between the capacitors, which has been pointed out as a problem in the conventional cylindrical capacitors, thereby improving the reliability and yield of the semiconductor device can be expected.
Claims (8)
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| KR1019970029684A KR19990005486A (en) | 1997-06-30 | 1997-06-30 | Capacitor Manufacturing Method of Semiconductor Device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7393742B2 (en) | 2005-02-21 | 2008-07-01 | Samsung Electronics Co., Ltd. | Semiconductor device having a capacitor and a fabrication method thereof |
| KR100917057B1 (en) * | 2002-12-26 | 2009-09-10 | 매그나칩 반도체 유한회사 | Method for forming a capacitor of a semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100917057B1 (en) * | 2002-12-26 | 2009-09-10 | 매그나칩 반도체 유한회사 | Method for forming a capacitor of a semiconductor device |
| US7393742B2 (en) | 2005-02-21 | 2008-07-01 | Samsung Electronics Co., Ltd. | Semiconductor device having a capacitor and a fabrication method thereof |
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