KR20030057624A - Method of fabricating capacitor - Google Patents
Method of fabricating capacitor Download PDFInfo
- Publication number
- KR20030057624A KR20030057624A KR1020010087697A KR20010087697A KR20030057624A KR 20030057624 A KR20030057624 A KR 20030057624A KR 1020010087697 A KR1020010087697 A KR 1020010087697A KR 20010087697 A KR20010087697 A KR 20010087697A KR 20030057624 A KR20030057624 A KR 20030057624A
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- KR
- South Korea
- Prior art keywords
- storage node
- pattern
- node contact
- insulating layer
- insulating film
- Prior art date
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- 239000003990 capacitor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title description 2
- 238000003860 storage Methods 0.000 claims abstract description 50
- 150000004767 nitrides Chemical class 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 16
- 229920005591 polysilicon Polymers 0.000 abstract description 16
- 230000007423 decrease Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 고집적 메모리소자의 스토리지노드간 브릿지 발생을 방지하기 위한 커패시터의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a capacitor for preventing a bridge between storage nodes of a highly integrated memory device.
종래기술에 의한 고집적 DRAM의 원통형 커패시터 스토리지노드 형성방법을 도1a 내지 도1c를 참조하여 설명하면 다음과 같다.A method of forming a cylindrical capacitor storage node of a highly integrated DRAM according to the prior art will be described with reference to FIGS. 1A to 1C.
먼저, 도1a에 나타낸 바와 같이 반도체기판(11)상에 게이트(워드라인)(도시하지 않음)를 형성하고, 반도체기판(11)상에 제1절연막(12)을 증착한 후, 제1절연막을 관통하여 반도체기판(11)에 연결되는 폴리실리콘플러그(13)를 형성한다.First, as shown in FIG. 1A, a gate (word line) (not shown) is formed on the semiconductor substrate 11, the first insulating film 12 is deposited on the semiconductor substrate 11, and then the first insulating film is deposited. The polysilicon plug 13 connected to the semiconductor substrate 11 is formed through the through hole.
다음으로, 폴리실리콘플러그(13)가 형성된 제1절연막(12)상에 제2절연막(14)을 형성한 후, 그 상부 소정영역에 양측벽에 스페이서(16)가 접속된 비트라인(15)을 형성한다.Next, after the second insulating film 14 is formed on the first insulating film 12 having the polysilicon plug 13 formed thereon, the bit line 15 having spacers 16 connected to both side walls of the upper predetermined region. To form.
다음에 비트라인(15)을 포함한 전면에 제3절연막(17)을 형성한 후, 제3절연막(17)과 제2절연막(14)을 선택적으로 식각하여 폴리실리콘플러그(13) 표면을 노출시키는 스토리지노드콘택홀(18)을 형성한다.Next, after the third insulating film 17 is formed on the entire surface including the bit line 15, the third insulating film 17 and the second insulating film 14 are selectively etched to expose the surface of the polysilicon plug 13. The storage node contact hole 18 is formed.
도 1b에 도시된 바와 같이, 스토리지노드콘택홀(18)에 스토리지노드콘택(19)을 형성한 후, 스토리지노드콘택(19)이 형성된 제3절연막(17)상에 질화막(20)과 제4절연막(21)을 차례로 증착한다.As shown in FIG. 1B, after the storage node contact 19 is formed in the storage node contact hole 18, the nitride film 20 and the fourth film are formed on the third insulating layer 17 on which the storage node contact 19 is formed. The insulating film 21 is deposited in order.
다음으로, 제4절연막(21)을 질화막(20)에서 멈추도록 먼저 식각하고,질화막(20)을 식각하여 스토리지노드콘택(19)을 노출시키는 스토리지노드가 형성될 영역(22)을 오픈시킨다.Next, the fourth insulating layer 21 is first etched to stop the nitride layer 20, and the nitride layer 20 is etched to open a region 22 where a storage node for exposing the storage node contact 19 is formed.
도 1c에 도시된 바와 같이, 스토리지노드가 형성될 영역(22) 내에만 스토리지노드(23)를 형성하고, 스토리지노드(23)의 표면에 MPS(metastable polysilicon)(24)를 성장시킨다.As shown in FIG. 1C, the storage node 23 is formed only in the region 22 in which the storage node is to be formed, and the metastable polysilicon (MPS) 24 is grown on the surface of the storage node 23.
그러나, 상기한 바와 같은 종래 기술에 있어서는 DRAM이 고집적되면 될수록 스토리지노드간 마진이 감소되어 인접한 스토리지노드간에 브릿지가 발생할 수 있다. 이러한 브릿지는 수율을 저하시키는 주요한 원인이 된다.However, in the conventional technology as described above, as the DRAM is highly integrated, the margin between storage nodes decreases, so that bridges may occur between adjacent storage nodes. This bridge is a major cause of lowering the yield.
본 발명은 상기 문제점을 해결하기 위한 것으로써, 원통형 커패시터 스토리지노드 패턴의 내벽이 아닌 외벽을 커패시터 전극으로 사용하여 스토리지노드간 브릿지를 방지하고 커패시터 용량을 증가시킬 수 있도록 한 커패시터의 형성방법을 제공하는데 목적이 있다.The present invention is to solve the above problems, to provide a method of forming a capacitor to prevent the bridge between storage nodes and increase the capacitor capacity by using the outer wall of the cylindrical capacitor storage node pattern as the capacitor electrode. There is a purpose.
도1a 내지 도1c는 종래기술에 의한 커패시터 스토리지노드 형성방법을 나타낸 공정단면도,1A through 1C are cross-sectional views illustrating a method of forming a capacitor storage node according to the prior art;
도2a 내지 도2e는 본 발명에 의한 커패시터의 형성방법을 나타낸 공정 단면도.2A to 2E are cross-sectional views illustrating a method of forming a capacitor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
31 : 반도체기판 32 : 제1절연막31 semiconductor substrate 32 first insulating film
33 : 폴리실리콘플러그 34a : 제2절연막패턴33 polysilicon plug 34a second insulating film pattern
35 : 비트라인 36 : 제1질화막35 bit line 36 first nitride film
37 : 제3절연막 38 : 스토리지노드콘택홀37: third insulating layer 38: storage node contact hole
39 : 스토리지노드콘택 40 : 제2질화막39: storage node contact 40: second nitride film
41 : 제4절연막 42 : 스토리지노드41: fourth insulating film 42: storage node
43 : MPS43: MPS
상기 목적을 달성하기 위한 본 발명은, 반도체기판 전면에 제1절연막을 형성하고 이를 선택적으로 식각하여 기판 소정영역을 노출시키는 콘택홀을 형성하는 단계, 상기 콘택홀을 도전물질로 매립하여 플러그를 형성하는 단계, 상기 플러그를 포함한 전면에 제2절연막을 증착하고 제2절연막패턴으로 패터닝하는 단계, 상기제2절연막패턴의 측면에 비트라인을 형성하는 단계, 상기 비트라인을 포함한 전면에 제1질화막을 증착하는 단계, 상기 제1질화막상에 제3절연막을 증착하는 단계, 상기 제2절연막패턴과 제1질화막 및 제3절연막을 선택적으로 식각하여 상기 플러그 표면을 노출시키는 스토리지노드 콘택홀을 형성하는 단계, 상기 스토리지노드 콘택홀을 도전물질로 매립하여 스토리지노드 콘택을 형성하는 단계, 상기 스토리지노드콘택 상부에 제2질화막과 제4절연막의 적층패턴을 형성하는 단계, 및 상기 적층패턴의 측벽에 상기 스토리지노드콘택에 연결되는 스토리지노드를 형성하는 단계를 포함하여 구성됨을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a contact hole for exposing a predetermined region by forming a first insulating layer on an entire surface of a semiconductor substrate and selectively etching the semiconductor substrate, and filling the contact hole with a conductive material to form a plug. And depositing a second insulating film on the entire surface including the plug and patterning the second insulating film pattern, forming a bit line on a side surface of the second insulating film pattern, and forming a first nitride film on the entire surface including the bit line. Depositing a third insulating layer on the first nitride layer, selectively etching the second insulating pattern, the first nitride layer, and the third insulating layer to form a storage node contact hole exposing the plug surface; Filling the storage node contact hole with a conductive material to form a storage node contact; a second material on the storage node contact; Characterized by the step of forming a laminate pattern of the film and the fourth insulating film, and configured by comprising: a side wall of the stacking pattern to form a storage node coupled to the storage node contacts.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도2a 내지 도2e에 본 발명에 의한 커패시터의 형성방법을 도시한 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method of forming a capacitor according to the present invention.
도2a에 나타낸 바와 같이, 반도체기판(31)상에 게이트(워드라인)(도시하지 않음)를 형성하고, 반도체기판(31)상에 제1절연막(32)을 증착한 후, 제1절연막(32)을 관통하여 반도체기판(31)에 연결되는 폴리실리콘플러그(33)를 형성한다.As shown in FIG. 2A, a gate (word line) (not shown) is formed on the semiconductor substrate 31, the first insulating film 32 is deposited on the semiconductor substrate 31, and then the first insulating film ( A polysilicon plug 33 connected to the semiconductor substrate 31 through the 32 is formed.
다음으로, 폴리실리콘플러그(33)가 형성된 제1절연막(32)상에 제2절연막(34)을 형성한다.Next, a second insulating film 34 is formed on the first insulating film 32 on which the polysilicon plug 33 is formed.
도 2b에 도시된 바와 같이, 제2절연막(34)을 선택적으로 식각하여 폴리실리콘플러그(33)상에 폴리실리콘플러그(33)보다 더 넓은 면적을 갖는 제2절연막패턴(34a)을 형성한다.As shown in FIG. 2B, the second insulating layer 34 is selectively etched to form a second insulating layer pattern 34a having a larger area than the polysilicon plug 33 on the polysilicon plug 33.
이때, 제2절연막패턴(34a)은 폴리실리콘플러그(33) 상부에 형성되되, 폴리실리콘플러그(33)를 하나씩 건너뛰어 형성된다.In this case, the second insulating film pattern 34a is formed on the polysilicon plug 33, and is formed by skipping the polysilicon plug 33 one by one.
다음에 도2c에 나타낸 바와 같이, 제2절연막패턴(34a)의 측면에 비트라인(35)을 형성한 다음, 전면에 제1질화막(36)을 증착한다. 이와 같이 제2절연막패턴(34a)의 측면에 비트라인(35)을 형성하면 비트라인(35)은 폴리실리콘 플러그(33) 사이의 제1절연막(32) 상부에 각각 위치하게 된다.Next, as shown in FIG. 2C, the bit line 35 is formed on the side surface of the second insulating film pattern 34a, and then the first nitride film 36 is deposited on the entire surface. As such, when the bit line 35 is formed on the side surface of the second insulating layer pattern 34a, the bit line 35 is positioned on the first insulating layer 32 between the polysilicon plugs 33, respectively.
한편, 제1질화막(36) 형성전에 절연막을 증착할 수 있다.On the other hand, an insulating film may be deposited before the first nitride film 36 is formed.
다음으로, 제1질화막(36)상에 제3절연막(37)을 증착한 후, 제3절연막(37), 제1질화막(36) 및 제2절연막패턴(34a)을 동시에 식각하여 폴리실리콘플러그(33) 표면을 노출시키는 스토리지노드 콘택홀(38)을 형성한다.Next, after the third insulating film 37 is deposited on the first nitride film 36, the third insulating film 37, the first nitride film 36, and the second insulating film pattern 34a are simultaneously etched to form a polysilicon plug. (33) A storage node contact hole 38 is formed to expose the surface.
도 2d에 도시된 바와 같이, 스토리지노드 콘택홀(38)을 통해 폴리실리콘플러그(33)에 연결되는 스토리지노드콘택(39)을 형성한다. 이때, 스토리지노드콘택(39)은 스토리지노드콘택홀(38)에 매립된 구조를 갖는다.As shown in FIG. 2D, the storage node contact 39 is connected to the polysilicon plug 33 through the storage node contact hole 38. In this case, the storage node contact 39 has a structure embedded in the storage node contact hole 38.
스토리지노드콘택(39)가 매립된 제3절연막(37)상에 제2질화막(40)과 제4절연막(41)을 차례로 증착한 후, 제4절연막(41)과 제2질화막(40)을 스토리지노드 패턴으로 패터닝한다. 이때, 제2질화막(40)과 제4절연막(41)의 순서로 적층된 적층패턴(40/41)이 스토리지노드콘택(39) 상부에 남는다.After the second nitride film 40 and the fourth insulating film 41 are sequentially deposited on the third insulating film 37 having the storage node contact 39 embedded therein, the fourth insulating film 41 and the second nitride film 40 are deposited. Pattern with a storage node pattern. At this time, the stacked patterns 40/41 stacked in the order of the second nitride film 40 and the fourth insulating film 41 remain on the storage node contact 39.
도 2f에 도시된 바와 같이, 적층패턴(40/41)을 포함한 전면에 폴리실리콘을증착한 후, 에치백공정을 진행하여 적층패턴(40/41)의 측벽에 접하는 스토리지노드(42)를 형성한다.As shown in FIG. 2F, after depositing polysilicon on the entire surface including the stacked patterns 40/41, an etch back process is performed to form a storage node 42 contacting the sidewalls of the stacked patterns 40/41. do.
다음으로, 스토리지노드(42)의 표면에 MPS(43)을 성장시킨다.Next, the MPS 43 is grown on the surface of the storage node 42.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 커패시터 스토리지노드 패턴의 내벽이 아닌 외벽을 커패시터 전극으로 사용함으로써 스토리지노드간 브릿지를 방지하고 커패시터 용량을 증가시킬 수 있다.The present invention can prevent the bridge between storage nodes and increase the capacitor capacity by using the outer wall, not the inner wall of the capacitor storage node pattern as the capacitor electrode.
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| KR1020010087697A KR100804147B1 (en) | 2001-12-29 | 2001-12-29 | Method of fabricating capacitor |
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| KR980012521A (en) * | 1996-07-29 | 1998-04-30 | 김광호 | Method for manufacturing capacitor of semiconductor device |
| TW412827B (en) * | 1997-09-29 | 2000-11-21 | Texas Instruments Inc | Selective hemispherical grain electrode for increased capacitance |
| KR20010046152A (en) * | 1999-11-10 | 2001-06-05 | 박종섭 | Method of fabrication capacitor in high capacity of memory device |
| KR20030050643A (en) * | 2001-12-19 | 2003-06-25 | 주식회사 하이닉스반도체 | Method for fabricating capacitor |
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2001
- 2001-12-29 KR KR1020010087697A patent/KR100804147B1/en not_active IP Right Cessation
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| KR100804147B1 (en) | 2008-02-19 |
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