KR100532980B1 - Capacitor forming method - Google Patents
Capacitor forming method Download PDFInfo
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- KR100532980B1 KR100532980B1 KR10-1999-0047133A KR19990047133A KR100532980B1 KR 100532980 B1 KR100532980 B1 KR 100532980B1 KR 19990047133 A KR19990047133 A KR 19990047133A KR 100532980 B1 KR100532980 B1 KR 100532980B1
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- insulating film
- etching
- forming
- interlayer insulating
- capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
본 발명은 커패시터 형성방법에 관한 것으로, 종래 커패시터 형성방법은 커패시터 하부전극을 형성하기위하여 절연막을 식각할 경우 마스크로 사용하는 감광막을 패터닝하는 노광장비의 한계해상력때문에 형성할 수 있는 감광막의 높이에 한계가 있어 식각선택비를 확보하기 어려워 커패시터의 높이를 높일 수 없으며, 근접하는 커패시터 하부전극과의 거리마진을 줄일 수 없으므로 커패시터의 용량확보가 어려워 집적도를 높일 수 없는 문제점이 있었다. 따라서, 본 발명은 트랜치가 형성된 반도체기판 상에 일정한 거리로 이격되는 제 1~제 4게이트를 형성한 후, 상부전면에 제 1층간절연막을 형성하는 공정과; 상기 제 1~제 4게이트간 이격영역의 제 1층간절연막을 식각하고, 도전성물질을 채워 제 1~제 3플러그를 형성한 다음 상부전면에 제 2층간절연막을 형성하는 공정과; 상기 제 2플러그가 형성된 영역의 제 2층간절연막을 식각하고, 그 상부에 도전성물질을 증착 후 패터닝하여 비트라인을 형성한 다음 상부전면에 제 3층간절연막을 형성하는 공정과; 상기 제 1,제 3플러그가 형성된 영역의 제 2,제 3층간절연막을 식각하고, 제 1도전체층을 채워넣은 다음 상부전면에 차례로 제 4층간절연막, 제 1절연막, 하드마스크층을 형성하는 공정과; 상기 하드마스크층을 사진식각을 통해 패터닝한 다음 이를 마스크로 제 1절연막 및 제 4층간절연막을 건식식각하여 패터닝하는 공정과; 상기 제 1절연막을 습식식각하여 상기 형성한 패턴을 넓힌다음 상기 구조물 상부전면에 제 2도전체층을 형성하는 공정과; 상기 제 2도전체층의 상부전면에 제 2절연막을 증착하고 이를 에치백한 후 이를 통해 드러난 제 2도전체층을 식각하는 공정과; 상기 잔류하는 하드마스크, 제 2절연막 및 제 1절연막을 식각하여 제거하는 공정을 포함하여 이루어지는 커패시터 형성방법을 통해 노광기의 한계해상력의 제한을 극복하여 커패시터의 높이를 높일 수 있고, 습식각을 이용하여 커패시터 하부전극의 크기를 넓힐 수 있으므로 커패시터 간의 거리마진을 줄이면서 커패시터의 용량을 높일 수 있어 집적도를 향상시킬 수 있을 뿐만 아니라 커패시터 하부전극의 하단에 접합되어 있는 층간절연막이 턱을 형성하여 공정 중에 커패시터 하부전극의 이탈이나 쓰러짐을 개선할 수 있는 효과가 있다.The present invention relates to a method for forming a capacitor, and the conventional method for forming a capacitor is limited to the height of the photoresist film that can be formed due to the limitation of the exposure equipment for patterning the photoresist film used as a mask when etching the insulating film to form the capacitor lower electrode. Since it is difficult to secure the etching selectivity, the height of the capacitor cannot be increased, and the distance margin from the adjacent capacitor lower electrode cannot be reduced, so that the capacity of the capacitor is difficult to secure, thereby increasing the density. Accordingly, the present invention comprises the steps of forming a first interlayer insulating film on the upper surface after forming the first to fourth gates spaced apart by a predetermined distance on the trench formed semiconductor substrate; Etching the first interlayer insulating film in the spaced area between the first and fourth gates, filling the conductive material to form the first to third plugs, and then forming a second interlayer insulating film on an upper surface of the first interlayer insulating film; Etching the second interlayer insulating film in the region where the second plug is formed, forming a bit line by depositing and patterning a conductive material thereon, and forming a third interlayer insulating film on the upper surface; Etching the second and third interlayer insulating films in the region where the first and third plugs are formed, filling the first conductive layer, and then forming the fourth interlayer insulating film, the first insulating film, and the hard mask layer on the upper surface in order. and; Patterning the hard mask layer through photolithography followed by dry etching the first insulating layer and the fourth interlayer insulating layer with a mask; Forming a second conductive layer on the upper surface of the structure by wet etching the first insulating layer to widen the formed pattern; Depositing a second insulating layer on the upper surface of the second conductive layer, etching back the second insulating layer, and etching the exposed second conductive layer; Through the capacitor forming method including the step of etching and removing the remaining hard mask, the second insulating film and the first insulating film, the height of the capacitor can be increased by overcoming the limitation of the limit resolution of the exposure machine, and using wet etching. Since the size of the lower electrode of the capacitor can be increased, the capacitance of the capacitor can be increased while reducing the distance margin between the capacitors, thereby improving the integration degree, and the interlayer insulating film bonded to the bottom of the capacitor lower electrode forms the jaw to form the capacitor during the process. There is an effect to improve the separation or fall of the lower electrode.
Description
본 발명은 커패시터 형성방법에 관한 것으로, 특히 메모리의 고집적화에 따른 커패시터 형성에 있어서 하드마스크를 이용함으로써 노광장비 한계해상력을 극복하여 각 커패시터간의 거리마진을 최소화함과 아울러 용량을 증가 시키기에 적당하도록 한 커패시터 형성방법에 관한 것이다.The present invention relates to a method of forming a capacitor, in particular, by using a hard mask in the capacitor formation according to the high integration of the memory to overcome the limit resolution of the exposure equipment to minimize the distance margin between each capacitor and to increase the capacity It relates to a capacitor forming method.
종래 커패시터 형성방법을 도 1a 내지 도 1c의 수순단면도를 참고로 하여 설명하면 다음과 같다. The conventional capacitor forming method will be described with reference to the procedure cross-sectional view of FIGS. 1A to 1C as follows.
먼저, 도 1a에 도시한 바와같이 반도체기판(1)상에 트랜치(2)를 형성하여 액티브영역을 정의하고, 반도체기판(1) 및 트랜치(2)의 상부에 일정한 거리로 이격되는 게이트(3A~3D)를 형성한다.First, as shown in FIG. 1A, a trench 2 is formed on the semiconductor substrate 1 to define an active region, and the gate 3A is spaced at a predetermined distance from the upper portion of the semiconductor substrate 1 and the trench 2. ˜3D).
그리고, 상기 게이트(3A~3D)가 형성된 구조물 상에 층간절연막(4)을 형성하고, 액티브영역과 트랜치(2)상의 게이트(3A~3D)간 이격영역을 식각하여 컨택홀을 형성한 후, 도전성물질을 채워 플러그(5A~5C)를 형성한다.After forming the interlayer insulating film 4 on the structure where the gates 3A to 3D are formed, and forming a contact hole by etching a spaced area between the active region and the gates 3A to 3D on the trench 2, The conductive material is filled to form plugs 5A to 5C.
그리고, 상기 플러그(5A~5C)가 형성된 구조물 상에 층간절연막(6)을 형성하고, 상기 형성된 플러그(5B)의 일부가 드러나도록 컨택홀을 형성한 후 그 상부에 배선물질을 증착하고 이를 패터닝하여 비트라인(7)을 형성한다.In addition, an interlayer insulating film 6 is formed on the structure where the plugs 5A to 5C are formed, a contact hole is formed to expose a part of the formed plug 5B, and a wiring material is deposited thereon and patterned thereon. The bit line 7 is formed.
그리고, 상기 비트라인(7)이 형성된 구조물 상에 층간절연막(8)을 형성하고, 상기 플러그(5A,5C)가 형성된 영역을 식각하여 컨택홀을 형성한 다음 컨택홀이 채워지도록 제 1도전체층(9)을 형성한다.In addition, an interlayer insulating film 8 is formed on the structure where the bit line 7 is formed, and the first conductive layer is formed by etching the regions where the plugs 5A and 5C are formed to form contact holes, and then filling the contact holes. (9) is formed.
그리고, 상기 제 1도전체층(9)의 상부에 차례로 층간절연막(10), 절연막(11)을 증착하여 형성하고, 절연막(11) 상부에 감광막(PR1)을 도포하고 커패시터 하부전극이 형성될 영역에 맞도록 패터닝한다.The interlayer insulating film 10 and the insulating film 11 are sequentially formed on the first conductive layer 9, and the photoresist film PR1 is coated on the insulating film 11 and the capacitor lower electrode is formed. Pattern to fit.
그 다음, 도 1b에 도시한 바와같이 상기 형성한 감광막(PR1) 패턴을 이용하여 절연막(11) 및 층간절연막(10)을 건식각하여 커패시터 하부전극을 위한 패턴을 형성한 후 그 상부전면에 제 2도전체층(12)을 형성하고, 그 상부에 절연막(13)을 증착한 후 이를 에치백한다.Next, as shown in FIG. 1B, the insulating film 11 and the interlayer insulating film 10 are dry-etched using the formed photoresist film PR1 pattern to form a pattern for the capacitor lower electrode. A two-conductor layer 12 is formed, and an insulating film 13 is deposited thereon and then etched back.
그 다음, 도 1c에 도시한 바와같이 상기 형성한 제 2도전체층(12)을 상기 절연막(11)이 드러날 때 까지 에치백하고, 상기과정을 통해 드러난 절연막(11)을 식각하여 제거한다. Next, as shown in FIG. 1C, the formed second conductive layer 12 is etched back until the insulating film 11 is exposed, and the insulating film 11 exposed through the above process is etched and removed.
그러나, 상기한 바와같은 종래 커패시터 형성방법은 커패시터 하부전극을 형성하기위하여 절연막을 식각할 경우 마스크로 사용하는 감광막을 패터닝하는 노광장비의 한계해상력때문에 형성할 수 있는 감광막의 높이에 한계가 있어 식각선택비를 확보하기 어려워 커패시터의 높이를 높일 수 없으며, 근접하는 커패시터 하부전극과의 거리마진을 줄일 수 없으므로 커패시터의 용량확보가 어려워 집적도를 높일 수 없는 문제점이 있었다.However, the conventional capacitor formation method as described above has a limitation on the height of the photoresist film that can be formed due to the limit resolution of the exposure equipment patterning the photoresist film used as a mask when etching the insulating film to form the capacitor lower electrode. Since it is difficult to secure the ratio, the height of the capacitor cannot be increased, and the distance margin from the adjacent capacitor lower electrode can not be reduced, thereby making it difficult to secure the capacity of the capacitor.
본 발명은 상기한 바와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 하드마스크를 이용하여 식각선택비를 확보하므로써 커패시터의 높이를 높일 수 있으며 동시에 습식각을 이용하여 커패시터의 용량을 높일 수 있는 커패시터 형성방법을 제공하는데 있다. The present invention has been made to solve the conventional problems as described above, the object of the present invention is to increase the height of the capacitor by securing the etching selectivity by using a hard mask and at the same time the capacity of the capacitor by using wet etching It is to provide a method of forming a capacitor that can increase the.
상기한 바와같은 본 발명의 목적을 달성하기 위한 커패시터 형성방법은 트랜치가 형성된 반도체기판 상에 일정한 거리로 이격되는 제 1~제 4게이트를 형성한 후, 상부전면에 제 1층간절연막을 형성하는 공정과; 상기 제 1~제 4게이트간 이격영역의 제 1층간절연막을 식각하고, 도전성물질을 채워 제 1~제 3플러그를 형성한 다음 상부전면에 제 2층간절연막을 형성하는 공정과; 상기 제 2플러그가 형성된 영역의 제 2층간절연막을 식각하고, 그 상부에 도전성물질을 증착한 후 패터닝하여 비트라인을 형성한 다음 상부전면에 제 3층간절연막을 형성하는 공정과; 상기 제 1,제 3플러그가 형성된 영역의 제 2,제 3층간절연막을 식각하고, 제 1도전체층을 채워넣은 다음 상부전면에 차례로 제 4층간절연막, 제 1절연막, 하드마스크층을 형성하는 공정과; 상기 하드마스크층을 사진식각을 통해 패터닝한 다음 이를 마스크로 제 1절연막 및 제 4층간절연막을 건식식각하여 패터닝하는 공정과; 상기 제 1절연막을 습식식각하여 상기 형성한 패턴을 넓힌다음 상기 구조물 상부전면에 제 2도전체층을 형성하는 공정과; 상기 제 2도전체층의 상부전면에 제 2절연막을 증착하고 이를 에치백한 후 이를 통해 드러난 제 2도전체층을 식각하는 공정과; 상기 잔류하는 하드마스크, 제 2절연막 및 제 1절연막을 식각하여 제거하는 공정을 포함하여 이루어지는 것을 특징으로한다. A capacitor forming method for achieving the object of the present invention as described above is a step of forming a first interlayer insulating film on the upper surface after forming the first to fourth gates spaced at a predetermined distance on the semiconductor substrate formed with a trench and; Etching the first interlayer insulating film in the spaced area between the first and fourth gates, filling the conductive material to form the first to third plugs, and then forming a second interlayer insulating film on an upper surface of the first interlayer insulating film; Etching the second interlayer insulating film in the region where the second plug is formed, depositing a conductive material on the upper surface of the second plug, patterning the bit line to form a bit line, and then forming a third interlayer insulating film on the upper surface; Etching the second and third interlayer insulating films in the region where the first and third plugs are formed, filling the first conductive layer, and then forming the fourth interlayer insulating film, the first insulating film, and the hard mask layer on the upper surface in order. and; Patterning the hard mask layer through photolithography followed by dry etching the first insulating layer and the fourth interlayer insulating layer with a mask; Forming a second conductive layer on the upper surface of the structure by wet etching the first insulating layer to widen the formed pattern; Depositing a second insulating layer on the upper surface of the second conductive layer, etching back the second insulating layer, and etching the exposed second conductive layer; And etching away the remaining hard mask, the second insulating film, and the first insulating film.
상기한 바와같은 본 발명에 의한 커패시터 형성방법을 첨부한 도 2a 내지 도 2d의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.Referring to the cross-sectional view of the procedure of Figures 2a to 2d with the method for forming a capacitor according to the present invention as described above in detail as follows.
먼저, 도 2a에 도시한 바와같이 반도체기판(21)상에 트랜치(22)를 형성하여 액티브영역을 정의하고, 반도체기판(21) 및 트랜치(22)의 상부에 일정한 거리로 이격되는 게이트(23A~23D)를 형성한다.First, as shown in FIG. 2A, a trench 22 is formed on the semiconductor substrate 21 to define an active region, and the gate 23A is spaced at a predetermined distance from the upper portion of the semiconductor substrate 21 and the trench 22. ˜23D).
그리고, 상기 게이트(23A~23D)가 형성된 구조물 상에 층간절연막(24)을 형성하고, 액티브영역과 트랜치(22)상의 게이트(23A~23D)간 이격영역을 식각하여 컨택홀을 형성한 후, 도전성물질을 채워 플러그(25A~25C)를 형성한다.After the interlayer insulating film 24 is formed on the structure on which the gates 23A to 23D are formed, a contact hole is formed by etching the spaced area between the active region and the gates 23A to 23D on the trench 22. The conductive material is filled to form plugs 25A to 25C.
그리고, 상기 플러그(25A~25C)가 형성된 구조물 상에 층간절연막(26)을 형성하고, 상기 형성된 플러그(25B)의 일부가 드러나도록 컨택홀을 형성한 후 그 상부에 배선물질을 증착하고 이를 패터닝하여 비트라인(27)을 형성한다.In addition, an interlayer insulating layer 26 is formed on the structure in which the plugs 25A to 25C are formed, a contact hole is formed to expose a part of the formed plug 25B, and a wiring material is deposited thereon and patterned thereon. The bit line 27 is formed.
그리고, 상기 비트라인(27)이 형성된 구조물 상에 층간절연막(28)을 형성하고, 상기 플러그(25A,25C)가 형성된 영역을 식각하여 컨택홀을 형성한 다음 컨택홀이 채워지도록 제 1도전체층(29)을 형성한다.In addition, an interlayer insulating layer 28 is formed on the structure on which the bit line 27 is formed, and the first conductive layer is formed by etching the regions where the plugs 25A and 25C are formed to form contact holes, and then filling the contact holes. (29) is formed.
그리고, 상기 제 1도전체층(29)의 상부에 차례로 층간절연막(30), 절연막(31), 하드마스크(32)를 형성하고, 하드마스크(32) 상부에 감광막(PR2)을 도포하고 커패시터 하부전극이 형성될 영역에 맞도록 패터닝한다. In addition, an interlayer insulating film 30, an insulating film 31, and a hard mask 32 are sequentially formed on the first conductive layer 29, a photoresist film PR2 is coated on the hard mask 32, and a capacitor is lowered. Patterned to match the area where the electrode is to be formed.
이때, 하드마스크(32)는 폴리실리콘을 이용하며, 하드마스크(32)는 높지 않으므로 이를 패터닝하기위해 이용하는 감광막(PR2)또한 높지 않아도 되므로 커패시터 하부전극간의 거리마진을 줄일 수 있으며 폴리실리콘과 하부 절연막(31)은 산화막을 이용하는 경우 높은 식각선택비를 확보할 수 있어 10:1 이상의 종횡비에서도 식각이 가능하므로 커패시터 용량을 확보하기위하여 절연막(31)을 높게 형성하여 커패시터의 용량을 높일 수 있다. In this case, since the hard mask 32 uses polysilicon and the hard mask 32 is not high, the photoresist film PR2 used for patterning it does not have to be high, thereby reducing the distance margin between the lower electrodes of the capacitor and the polysilicon and the lower insulating film. In the case of using an oxide film (31), a high etching selectivity can be ensured, and therefore etching is possible even at an aspect ratio of 10: 1 or more, so that the insulating film 31 can be formed high to secure the capacitor capacity, thereby increasing the capacitor capacity.
또한, 상기 하드마스크(32)를 이용하여 산화막으로 형성된 절연막(31)과 질화막으로 형성된 층간절연막(30)을 높은 종횡비에서 식각하는 경우, 이온에너지모듈레이션(Ion Energy Modulation)식각장비에서 압력은 20~50mT, 전력은 1500~2000W, C4F8은 15~20sccm, Ar은 400~600sccm, O2는 8~15sccm의 조건으로 식각한다.Further, when the insulating film 31 formed of an oxide film and the interlayer insulating film 30 formed of a nitride film are etched at a high aspect ratio by using the hard mask 32, the pressure in the ion energy modulation etching equipment is 20 to 20 °. 50mT, power is 1500 ~ 2000W, C 4 F 8 is etched under the condition of 15 ~ 20sccm, Ar is 400 ~ 600sccm, O 2 is 8 ~ 15sccm.
그 다음, 도 2b에 도시한 바와같이 상기 형성한 하드마스크(32) 패턴을 이용하여 절연막(31) 및 층간절연막(30)을 건식각하여 커패시터 하부전극을 위한 패턴을 형성한 후 절연막(31)을 습식각하여 상기 형성된 패턴을 넓힌다.Next, as shown in FIG. 2B, the insulating layer 31 and the interlayer insulating layer 30 are dry-etched using the formed hard mask 32 pattern to form a pattern for the capacitor lower electrode, and then the insulating layer 31. Wet etching to widen the formed pattern.
이때, 상기 습식각에 사용하는 식각액은 HF와 NH4F의 화합물 중에 HF의 혼합비율이 작은 BOE(Buffered Oxide Etchant)를 순수에 희석하여 그 조성비를 HF:NH4F:H2O = 1:39:60 으로 하여 사용한다.At this time, the etchant used for the wet etching is diluted BOE (Buffered Oxide Etchant) having a small mixing ratio of HF in HF and NH 4 F compound in pure water and the composition ratio of HF: NH 4 F: H 2 O = 1: It is used as 39:60.
그리고, 상기 형성한 구조물 상부전면에 폴리실리콘을 증착하여 제 2도전체층(33)을 형성한다.The second conductive layer 33 is formed by depositing polysilicon on the upper surface of the structure.
그 다음, 도 2c에 도시한 바와같이 상기 형성한 제 2도전체층(33)의 상부에 산화막 혹은 스핀온 글라스로 절연막(34)을 형성하고 이를 에치백한 후 이를 통해 드러난 제 2도전체층(33)의 상부 일부를 식각하여 제거한다.Next, as shown in FIG. 2C, an insulating film 34 is formed on the formed second conductive layer 33 by using an oxide film or spin-on glass, etched back, and then exposed through the second conductive layer 33. Etch off the upper part of the shell.
그 다음, 도 2d에 도시한 바와같이 상기 잔류하는 절연막(34), 하드마스크 (32) 및 절연막(31)을 식각하여 제거한다. Then, as shown in FIG. 2D, the remaining insulating film 34, hard mask 32, and insulating film 31 are etched and removed.
상기한 바와같은 본 발명에 의한 커패시터 형성방법은 하드마스크를 이용하여 식각선택비를 확보하므로써 노광기의 한계해상력의 제한을 극복하여 커패시터의 높이를 높일 수 있고, 습식각을 이용하여 커패시터 하부전극의 크기를 넓힐 수 있으므로 커패시터 간의 거리마진을 줄이면서 커패시터의 용량을 높일 수 있어 집적도를 향상시킬 수 있을 뿐만 아니라 커패시터 하부전극의 하단에 접합되어 있는 층간절연막이 턱을 형성하여 공정 중에 커패시터 하부전극의 이탈이나 쓰러짐을 개선할 수 있는 효과가 있다.Capacitor forming method according to the present invention as described above can increase the height of the capacitor by overcoming the limitation of the limit resolution of the exposure machine by securing the etching selectivity by using a hard mask, the size of the capacitor lower electrode by using wet etching As a result, it is possible to increase the capacitance of the capacitor while reducing the distance margin between the capacitors, thereby improving the degree of integration. In addition, the interlayer insulating film bonded to the lower end of the capacitor lower electrode forms a jaw, so that the capacitor lower electrode There is an effect to improve the fall.
도 1은 종래 커패시터 형성방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional capacitor forming method.
도 2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
*** 도면의 주요부분에 대한 부호의 설명 ****** Explanation of symbols for main parts of drawing ***
21 : 반도체기판 22 : 트랜치21: semiconductor substrate 22: trench
23A~23D : 게이트 24,26,28,30 : 층간절연막23A ~ 23D: Gate 24, 26, 28, 30: Interlayer insulating film
25A~25C : 플러그 27 : 비트라인25A ~ 25C: Plug 27: Bitline
29 : 제 1도전체층 31 : 절연막29 first conductive layer 31 insulating film
32 : 하드마스크층 33 : 제 2도전체층32: hard mask layer 33: second conductive layer
34 : 산화막34: oxide film
PR2 : 감광막PR2: photosensitive film
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| JPH10223854A (en) * | 1997-02-05 | 1998-08-21 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
| JPH1187650A (en) * | 1997-09-08 | 1999-03-30 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
| US6010943A (en) * | 1998-04-23 | 2000-01-04 | United Silicon Incorporated | Method of fabricating a cylindrical capacitor |
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| JPH10223854A (en) * | 1997-02-05 | 1998-08-21 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
| JPH1187650A (en) * | 1997-09-08 | 1999-03-30 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
| US6010943A (en) * | 1998-04-23 | 2000-01-04 | United Silicon Incorporated | Method of fabricating a cylindrical capacitor |
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