KR20020042192A - Method for forming capacitor - Google Patents

Abstract

PURPOSE: A fabrication method of capacitors is provided to increase a capacitance by forming a lower electrode of a capacitor to a second storage node contact plug formation region. CONSTITUTION: A transistor having gate insulating layers(2), gate electrodes(3) and impurity regions is formed on a substrate(1). After depositing a first insulating layer(6), storage node contact holes are formed to expose the impurity regions. Then, storage node contact plugs(7) are filled into the storage node contact holes. After depositing and selectively patterning a second insulating layer(8), a third insulating layer(10), a TEOS(Tetra Ethyl Ortho Silicate)(11), holes are formed to expose the storage node contact plugs(7). An amorphous silicon is formed on the sidewalls and the bottom surfaces of the holes. Lower electrodes of storage capacitors having an uneven shape are formed by crystallizing the amorphous silicon, thereby increasing the size of the lower electrodes. That is, the capacitance of the capacitor is also increased.

Description

Capacitor manufacturing method {Method for forming capacitor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device (DRAM), and more particularly, to a method of manufacturing a capacitor having a deeper contact hole to have a larger capacity.

As semiconductor memory devices become more integrated, the area occupied by unit cells must be reduced. Therefore, many methods for increasing the capacity of capacitors in the same area are being researched and developed.

Hereinafter, a method of forming a lower electrode of a conventional DRAM capacitor will be described with reference to the accompanying drawings.

1A-1F are cross-sectional views of a conventional capacitor bottom electrode process.

As shown in FIG. 1A, a cap / sidewall insulating film 4 and both sides of the gate electrode 3 for electrically isolating the gate insulating film 2, the gate electrode 3, and the gate electrode 3 from the semiconductor substrate 1. A transistor having impurity regions 5 formed in the semiconductor substrate 1 is formed. The planarization insulating layer 6 is deposited on the entire surface, and the planarization insulating layer 6 is selectively removed to expose the impurity region 5 to form a first storage node contact hole. Polysilicon is deposited on the entire surface to fill the first storage node contact hole, and the polysilicon is etched back to expose the surface of the planarization insulating layer 6 to form a first storage contact plug 7. Subsequently, a thick insulating film 8 is deposited on the entire surface, and the insulating film 8 is selectively removed to expose the first storage contact plug 7 to form a second storage node contact hole, and then the second storage. Polysilicon is deposited on the entire surface to be filled in the node contact hole, and the polysilicon is etched back to expose the surface of the insulating layer 8 to form a second storage contact plug 9. An etch stopper nitride film 10 is deposited on the entire surface, and TEOS 11 is deposited on the nitride film 10.

As shown in FIG. 1B, a hole is formed by removing the TEOS 11 film and the nitride film 10 of the portion where the second storage contact plug 9 is formed. In this case, the width of the hole is wider than that of the second storage contact plug 9.

As illustrated in FIG. 1C, amorphous silicon 12 is deposited on the entire surface of the substrate. At this time, the amorphous silicon 12 is deposited to a uniform thickness on the surface and the side and bottom of the hole of the TEOS (11).

As shown in Fig. 1D, a thick SOG 13 is deposited on the front surface to be filled in the hole, and the SOG 13 is etched back so as to remain lower than the height of the hole in the hole.

As shown in FIG. 1E, the non-crystalline silicon 12 is etched back using the SOG 13 as a mask.

As shown in FIG. 1F, both the SOG 13 and the TEOS 11 are removed and the amorphous silicon 12 is crystallized to form the uneven surface of the SEAS 12a to form the lower electrode of the storage capacitor.

However, the method of forming the storage capacitor lower electrode of the memory device of the present invention as described above has the following problems.

First, since the lower electrode is formed by forming the second contact hole forming process and the hole for forming the lower electrode, the thickness of the insulating layer is thick when the second storage node contact hole is formed, so the contact hole may be reduced in size or etch stop may occur. Grows

Secondly, since several discontinuous contact processes are required, the process is complicated and reliability of contact resistance is degraded.

Third, since the lower electrode of the capacitor is placed on the second storage node contact plug, it may easily fall off when an etching amount is insufficient or a physical force (for example, centrifugal force) is applied in a drying process after cleaning.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is to simplify a process and increase a capacitor capacity by forming a capacitor lower electrode at a portion thereof without forming a second storage node contact plug.

1A through 1F are cross-sectional views of a lower electrode of a conventional DRAM capacitor.

2A to 2I are cross-sectional views of a lower electrode process of a DRAM capacitor according to the present invention.

Explanation of symbols for the main parts of the drawings

1 semiconductor substrate 2 gate insulating film

3: gate electrode 4: cap and sidewall insulating film

5 impurity region 6, 8 insulating film

7: plug 10: nitride film

11: TEOS 12: amorphous silicon

12a: SEAS 13: SOG

14: Hall

The capacitor manufacturing method of the present invention for achieving the above object comprises the steps of forming a gate insulating film, a gate electrode and a transistor having impurity regions in the semiconductor substrate on both sides of the gate electrode on the semiconductor substrate, and the first planarization on the entire surface Depositing an insulating film and forming a storage node contact hole to expose the impurity region, forming a storage node contact plug in the storage node contact hole, depositing a second insulating film and a third insulating film on the front surface in sequence, and Selectively removing the second and third insulating layers of the portion where the storage contact plugs are formed to form holes to expose the plugs; forming amorphous silicon on the sidewalls and bottom surfaces of the holes; Story of uneven surface by removing and crystallizing the amorphous silicon It is characterized by including the process of forming the bottom electrode of the ground capacitor.

Referring to the attached drawings of the capacitor manufacturing method of the present invention having such a feature in more detail as follows.

2A to 2F are cross-sectional views of a capacitor manufacturing process according to the present invention.

As shown in FIG. 2A, both sides of the cap / sidewall insulating film 4 and the gate electrode 3 for electrically insulating the gate insulating film 2, the gate electrode 3, and the gate electrode 3 from the semiconductor substrate 1 are provided. A transistor having impurity regions 5 formed in the semiconductor substrate 1 is formed. The planarization insulating layer 6 is deposited on the entire surface, and the planarization insulating layer 6 is selectively removed so that the impurity region 5 is exposed to form a storage node contact hole. In addition, polysilicon is deposited on the entire surface to fill the storage node contact hole, and the polysilicon is etched back to expose the surface of the planarization insulating layer 6 to form a storage contact plug 7. Subsequently, the insulating film 8 is thickly deposited on the entire surface, and the TEOS 11 is sequentially deposited on the etch stopper nitride film 10 and the nitride film 10 on the entire surface.

As shown in FIG. 2B, the hole 14 is exposed to selectively expose the plug 7 by selectively removing the TEOS 11 film, the nitride film 10, and the insulating film 8 of the portion where the storage contact plug 7 is formed. To form. In this case, the width of the hole 14 may be wider or narrower than the width of the storage contact plug 7.

As illustrated in FIG. 2C, amorphous silicon 12 is deposited on the entire surface of the substrate. At this time, the amorphous silicon 12 is deposited to a uniform thickness on the surface and the side and bottom of the hole of the TEOS (11).

As shown in FIG. 2D, a thick SOG 13 is deposited on the entire surface of the hole 14 to fill the hole 14.

As illustrated in FIG. 2E, the SOG 13 is etched back so as to remain lower than the height of the hole 14 in the hole 14.

As shown in FIG. 2F, the SOG 13 is used as a mask to etch back or draw to selectively remove the amorphous silicon 12 formed on the surface of the TEOS 11.

As illustrated in FIG. 2G, all of the SOG 13 is removed using wet etching, and as shown in FIG. 2H, all of the TEOS 11 is removed using wet etching.

As shown in FIG. 2I, the amorphous silicon 12 is crystallized to form a SEAS 12a having an uneven surface, thereby forming a lower electrode of the storage capacitor.

In the capacitor manufacturing method of the present invention as described above has the following effects.

First, since the second storage node contact plug is not formed, the process is simplified and the yield is improved.

Second, the phenomenon that the lower electrode of the capacitor is separated by the external physical force can be prevented.

Third, since the lower electrode of the capacitor is formed to the second storage node contact plug forming region, the capacitor capacity can be increased.

Claims (4)

Forming a transistor including a gate insulating film, a gate electrode, and a impurity region on a semiconductor substrate on both sides of the gate electrode on the semiconductor substrate; Depositing a planarization first insulating film on the entire surface and forming a storage node contact hole to expose the impurity region; Forming a storage node contact plug in the storage node contact hole; Depositing a second insulating film and a third insulating film in order on the entire surface, and selectively removing the second and third insulating films of the portion where the storage contact plug is formed to form holes to expose the plugs; Forming amorphous silicon on sidewalls and bottom surfaces of the holes; And removing the third insulating film and crystallizing the amorphous silicon to form a lower electrode of the storage capacitor having an uneven surface. The method of claim 1, And the third insulating film includes an etch stopper insulating film formed on the second insulating film and a fourth insulating film formed on the etch stopper insulating film. The method of claim 2, And wherein the insulating film for etch stopper is a nitride film and the fourth insulating film is a TEOS film. The method of claim 1, Forming amorphous silicon on the side wall and bottom surface of the hole, Depositing amorphous silicon on the surface and the side and bottom of the hole of the third insulating film; Forming a SOG layer in the hole; Selectively removing the amorphous silicon layer formed on the surface of the third insulating film; And removing the SOG layer.