KR100253326B1 - Method for semiconductor device - Google Patents

Method for semiconductor device Download PDF

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KR100253326B1
KR100253326B1 KR1019970049555A KR19970049555A KR100253326B1 KR 100253326 B1 KR100253326 B1 KR 100253326B1 KR 1019970049555 A KR1019970049555 A KR 1019970049555A KR 19970049555 A KR19970049555 A KR 19970049555A KR 100253326 B1 KR100253326 B1 KR 100253326B1
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South Korea
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contact hole
film
substrate
layer
capacitor
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KR1019970049555A
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Korean (ko)
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KR19990027158A (en
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이창표
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to simplify the fabricating process and to improve isolation reliability between a plate capacitor electrode and a contact plug. CONSTITUTION: In the method, after a plurality of gates(3A¯3D) are formed on a substrate(1) and a field oxide layer(2), a node polysilicon layer(4) and a plate polysilicon layer(5) are deposited thereon to have a rugged surface profile and thereby to form a capacitor. Next, an oxide layer(6) and a BPSG layer(7) are sequentially formed over the capacitor. Then, a region where a contact hole is to be formed is defined, and the BPSG layer(7), the oxide layer(6) and the plate polysilicon layer(5) in the region are etched in sequence to form the contact hole exposing a corresponding portion of the substrate(1). Thereafter, a nitride layer is deposited over the BPSG layer(7) and in the contact hole, and then blanket-etched to form a nitride sidewall(8) on a side of the contact hole. The nitride sidewall(8) prevents a short circuit between the plate polysilicon layer(5) and a tungsten plug filled in the contact hole.

Description

반도체소자의 제조방법Manufacturing method of semiconductor device

본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 커패시터가 제조된 반도체기판상에 비교적 단순한 공정을 통해 다층배선을 위한 콘택홀(contact-hole)을 형성하기에 적당하도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for forming a contact hole for multilayer wiring through a relatively simple process on a semiconductor substrate on which a capacitor is manufactured. It is about.

종래 반도체소자의 제조방법을 첨부한 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a conventional method for manufacturing a semiconductor device is as follows.

도1a 내지 도1d는 종래 반도체소자의 제조방법을 보인 수순단면도로서, 이에 도시한 바와같이 기판(1) 및 필드산화막(2)의 상부에 형성된 게이트(3A∼3D) 상부에 노드폴리실리콘(4)과 플레이트(plate)폴리실리콘(5)을 요철(凹凸)형태로 증착하여 커패시터를 형성하는 단계(도1a)와; 포토레지스트(PR1)를 이용하여 게이트(3B,3C) 사이의 기판(1)이 노출되도록 플레이트폴리실리콘(5)을 식각하는 단계(도1b)와; 상기 포토레지스트(PR1)를 제거한 후, 기판(1)의 상부전면에 순차적으로 고온저압산화막(HLD:6)과 비피에스지막(BPSG:7)을 증착하는 단계(도1c)와; 포토레지스트(PR2)를 이용하여 게이트(3B,3C) 사이의 기판(1)이 노출되도록 비피에스지막(7)과 고온저압산화막(6)을 식각하는 단계(도1d)로 이루어진다. 이하, 종래 반도체소자의 제조방법을 좀더 상세히 설명한다.1A to 1D are cross-sectional views showing a conventional method of manufacturing a semiconductor device, and as shown therein, the node polysilicon 4 is formed on the gates 3A to 3D formed on the substrate 1 and the field oxide film 2. ) And a plate polysilicon (5) in the form of irregularities to form a capacitor (Fig. 1A); Etching the plate polysilicon 5 using the photoresist PR1 to expose the substrate 1 between the gates 3B and 3C (FIG. 1B); Removing the photoresist PR1 and depositing a high temperature low pressure oxide film (HLD) 6 and a BPSG film 7 on the upper surface of the substrate 1 (FIG. 1C); Etching the BP film 7 and the high temperature low pressure oxide film 6 so as to expose the substrate 1 between the gates 3B and 3C using the photoresist PR2 (FIG. 1D). Hereinafter, a method of manufacturing a conventional semiconductor device will be described in more detail.

먼저, 도1a에 도시한 바와같이 기판(1) 및 필드산화막(2)의 상부에 형성된 게이트(3A∼3D) 상부에 노드폴리실리콘(4)과 플레이트폴리실리콘(5)을 요철(凹凸)형태로 증착하여 커패시터를 형성한다. 이때, 커패시터는 노드폴리실리콘(4)을 증착하고, 그 노드폴리실리콘(4)의 표면에 유전물질을 바른 후, 플레이트폴리실리콘(5)을 증착하여 형성한다.First, as shown in FIG. 1A, the node polysilicon 4 and the plate polysilicon 5 are uneven on the gates 3A to 3D formed on the substrate 1 and the field oxide film 2, respectively. To form a capacitor. In this case, the capacitor is formed by depositing the node polysilicon 4, applying a dielectric material on the surface of the node polysilicon 4, and then depositing the plate polysilicon 5.

그리고, 도1b에 도시한 바와같이 포토레지스트(PR1)를 이용하여 게이트(3B,3C) 사이의 기판(1)이 노출되도록 플레이트폴리실리콘(5)을 식각한다.As shown in FIG. 1B, the plate polysilicon 5 is etched using the photoresist PR1 to expose the substrate 1 between the gates 3B and 3C.

그리고, 도1c에 도시한 바와같이 상기 포토레지스트(PR1)를 제거한 후, 기판(1)의 상부전면에 순차적으로 고온저압산화막(6)과 비피에스지막(7)을 증착한다. 이때, 고온저압산화막(6) 및 비피에스지막(7)을 증착한 후, 어닐링공정을 실시한다.After the photoresist PR1 is removed as shown in FIG. 1C, the high temperature low pressure oxide film 6 and the BP film 7 are sequentially deposited on the upper surface of the substrate 1. At this time, after the high temperature low pressure oxide film 6 and the BPS film 7 are deposited, an annealing process is performed.

그리고, 도1d에 도시한 바와같이 포토레지스트(PR2)를 이용하여 게이트(3B,3C) 사이의 기판(1)이 노출되도록 비피에스지막(7)과 고온저압산화막(6)을 식각하여 콘택홀을 형성한다. 이후, 콘택홀의 내부에 텅스텐을 매립하여 상부배선과 하부배선을 접속시킨다.As shown in FIG. 1D, the BP film 7 and the high temperature low pressure oxide film 6 are etched using the photoresist PR2 to expose the substrate 1 between the gates 3B and 3C. To form. Thereafter, tungsten is embedded in the contact hole to connect the upper wiring and the lower wiring.

그러나, 상기한 바와같이 제조되는 종래 반도체소자의 제조방법은 콘택홀이 형성될 영역을 2회에 걸쳐 사진식각함으로써, 공정효율 감소로 인한 제조비용이 증가하는 문제점과 아울러 얼라인(aline) 오차로 인해 커패시터의 플레이트전극과 콘택홀에 매립되는 텅스텐이 단락되는 문제점이 있었다.However, the conventional method of manufacturing a semiconductor device manufactured as described above, by photo-etching the region in which the contact hole is to be formed twice, increases the manufacturing cost due to the reduction in process efficiency and also due to the alignment error. Due to this, there is a problem in that tungsten embedded in the plate electrode and the contact hole of the capacitor is short-circuited.

본 발명은 상기한 바와같은 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 공정을 단순화하고, 커패시터의 플레이트전극과 콘택홀에 매립되는 텅스텐의 절연신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to simplify the process and to improve the insulation reliability of tungsten embedded in the plate electrode and contact hole of the capacitor. To provide.

도1은 종래 반도체소자의 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.

도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

1:기판 2:필드산화막1: Substrate 2: Field Oxide

3A∼3D:게이트 4:노드폴리실리콘3A to 3D: Gate 4: node polysilicon

5:플레이트폴리실리콘 6:고온저압산화막5: Plate polysilicon 6: High temperature low pressure oxide film

7:비피에스지막 8:질화막7: BP film 8: nitride film

PR1:포토레지스트PR1: Photoresist

상기한 바와같은 본 발명의 목적은 기판 및 필드산화막의 상부에 형성된 다수의 게이트 상부에 노드폴리실리콘과 플레이트폴리실리콘을 요철형태로 증착하여 커패시터를 형성한 후, 그 커패시터의 상부에 고온저압산화막과 비피에스지막을 순차적으로 증착하는 단계와; 콘택홀이 형성될 영역을 정의한 후, 포토레지스트를 이용하여 콘택홀이 형성될 영역의 비피에스지막, 고온저압산화막 및 플레이트폴리실리콘을 기판이 노출되도록 순차적으로 식각하는 단계와; 상기 포토레지스트를 제거하고, 비피에스지막 및 노출된 기판의 상부에 질화막을 증착한 후, 블랭크(blank) 식각하여 콘택홀의 측벽에 질화막 측벽을 형성하는 단계로 이루어짐으로써 달성되는 것으로, 본 발명에 의한 반도체소자의 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.As described above, an object of the present invention is to form a capacitor by depositing a node polysilicon and a plate polysilicon in an uneven shape on a plurality of gates formed on the substrate and the field oxide film, and then forming a high temperature low pressure oxide film on the capacitor. Depositing a BPS film sequentially; Defining a region where the contact hole is to be formed, and then sequentially etching the BPS film, the high temperature low pressure oxide film, and the plate polysilicon of the region where the contact hole is to be formed by using a photoresist; It is achieved by removing the photoresist, depositing a nitride film on top of the BPS film and the exposed substrate, and forming a nitride film sidewall on the sidewall of the contact hole by blank etching. Hereinafter, a method of manufacturing a semiconductor device will be described in detail with reference to the accompanying drawings.

도2a 내지 도2d는 본 발명의 일 실시예를 보인 수순단면도로서, 이에 도시한 바와같이 기판(1) 및 필드산화막(2)의 상부에 형성된 게이트(3A∼3D) 상부에 노드폴리실리콘(4)과 플레이트폴리실리콘(5)을 요철형태로 증착하여 커패시터를 형성하는 단계(도2a)와; 그 커패시터가 형성된 기판(1)의 상부에 순차적으로 고온저압산화막(6)과 비피에스지막(7)을 증착하는 단계(도2b)와; 포토레지스트(PR1)를 이용하여 게이트(3B,3C) 사이의 기판(1)이 노출되도록 비피에스지막(7), 고온저압산화막(6) 및 플레이트폴리실리콘(5)을 순차적으로 식각하는 단계(도2c)와; 상기 포토레지스트(PR1)를 제거하고, 비피에스지막(7) 및 노출된 기판(1)의 상부에 질화막(8)을 증착한 후, 블랭크 식각하여 콘택홀의 측벽에 질화막(8) 측벽을 형성하는 단계(도2d)로 이루어진다. 이하, 본 발명의 실시예를 좀더 상세히 설명한다.2A through 2D are cross-sectional views showing an embodiment of the present invention, and as shown therein, the node polysilicon 4 is formed on the gates 3A to 3D formed on the substrate 1 and the field oxide film 2. ) And the plate polysilicon (5) in the form of irregularities to form a capacitor (Fig. 2a); Depositing a high temperature low pressure oxide film 6 and a BPS film 7 sequentially on the substrate 1 on which the capacitor is formed (FIG. 2B); Etching the BPS film 7, the high temperature low pressure oxide film 6, and the plate polysilicon 5 in order to expose the substrate 1 between the gates 3B and 3C using the photoresist PR1 ( 2c); The photoresist PR1 is removed, the nitride film 8 is deposited on the BPS layer 7 and the exposed substrate 1, and then a blank is etched to form sidewalls of the nitride film 8 on the sidewalls of the contact holes. It consists of a step (Fig. 2d). Hereinafter, embodiments of the present invention will be described in more detail.

먼저, 도2a에 도시한 바와같이 기판(1) 및 필드산화막(2)의 상부에 형성된 게이트(3A∼3D) 상부에 노드폴리실리콘(4)과 플레이트폴리실리콘(5)을 요철형태로 증착하여 커패시터를 형성하고, 도2b에 도시한 바와같이 커패시터가 형성된 기판(1)의 상부에 순차적으로 고온저압산화막(6)과 비피에스지막(7)을 증착한다.First, as shown in FIG. 2A, the node polysilicon 4 and the plate polysilicon 5 are deposited in an uneven shape on the gates 3A to 3D formed on the substrate 1 and the field oxide film 2. A capacitor is formed, and as shown in FIG. 2B, a high temperature low pressure oxide film 6 and a BPS film 7 are sequentially deposited on the substrate 1 on which the capacitor is formed.

그리고, 도2c에 도시한 바와같이 포토레지스트(PR1)를 이용하여 게이트(3B,3C) 사이의 기판(1)이 노출되도록 비피에스지막(7), 고온저압산화막(6) 및 플레이트폴리실리콘(5)을 식각한다. 이와같이 커패시터의 상부에 고온저압산화막(6) 및 비피에스지막(7)을 증착한 후, 1회의 식각공정으로 콘택홀이 형성될 영역을 식각한다.As shown in FIG. 2C, the BP film 7, the high temperature low pressure oxide film 6, and the plate polysilicon (PSI) are exposed so that the substrate 1 between the gates 3B and 3C is exposed using the photoresist PR1. Etch 5). As described above, after depositing the high temperature low pressure oxide film 6 and the BPS layer 7 on the capacitor, the region where the contact hole is to be formed is etched by one etching process.

그리고, 도2d에 도시한 바와같이 상기 포토레지스트(PR1)를 제거하고, 비피에스지막(7) 및 노출된 기판(1)의 상부에 질화막(8)을 증착한 후, 블랭크 식각하여 콘택홀의 측벽에 질화막(8) 측벽을 형성한다. 이때, 질화막(8) 측벽은 이후의 공정에서 콘택홀에 매립되는 텅스텐과 커패시터의 플레이트폴리실리콘(5)이 단락되는 것을 방지한다.As shown in FIG. 2D, the photoresist PR1 is removed, the nitride film 8 is deposited on the BPS film 7 and the exposed substrate 1, and the blank is etched to form sidewalls of the contact holes. Sidewalls of the nitride film 8 are formed. At this time, the side wall of the nitride film 8 prevents the tungsten embedded in the contact hole and the plate polysilicon 5 of the capacitor from being short-circuited in a subsequent process.

상기한 바와같이 제조되는 본 발명에 의한 반도체소자의 제조방법은 콘택홀이 형성될 영역의 사진식각공정을 단순화함으로써, 제조비용이 감소하는 효과와; 콘택홀의 측벽에 질화막 측벽을 형성함으로써, 커패시터의 플레이트전극과 콘택홀에 매립되는 텅스텐의 절연신뢰성을 향상시킬 수 있는 효과가 있다.The semiconductor device manufacturing method according to the present invention manufactured as described above has the effect of reducing the manufacturing cost by simplifying the photolithography process of the region where the contact hole is to be formed; By forming the nitride film sidewalls on the sidewalls of the contact holes, the insulation reliability of the tungsten embedded in the plate electrodes of the capacitors and the contact holes can be improved.

Claims (1)

기판 및 필드산화막의 상부에 형성된 다수의 게이트 상부에 노드폴리실리콘과 플레이트폴리실리콘을 요철형태로 증착하여 커패시터를 형성한 후, 그 커패시터의 상부에 고온저압산화막과 비피에스지막을 순차적으로 증착하는 단계와; 콘택홀이 형성될 영역을 정의한 후, 포토레지스트를 이용하여 콘택홀이 형성될 영역의 비피에스지막, 고온저압산화막 및 플레이트폴리실리콘을 기판이 노출되도록 순차적으로 식각하는 단계와; 상기 포토레지스트를 제거하고, 비피에스지막 및 노출된 기판의 상부에 질화막을 증착한 후, 블랭크 식각하여 콘택홀의 측벽에 질화막 측벽을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체소자의 제조방법.Forming a capacitor by depositing a node polysilicon and a plate polysilicon in a concave-convex shape on a plurality of gates formed on the substrate and the field oxide film, and sequentially depositing a high temperature low pressure oxide film and a BPS film on the capacitor; ; Defining a region where the contact hole is to be formed, and then sequentially etching the BPS film, the high temperature low pressure oxide film, and the plate polysilicon of the region where the contact hole is to be formed by using a photoresist; Removing the photoresist, depositing a nitride film on top of the BPS film and the exposed substrate, and then etching the blank to form the nitride film sidewall on the sidewall of the contact hole.
KR1019970049555A 1997-09-29 1997-09-29 Method for semiconductor device KR100253326B1 (en)

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