KR20010068610A - Fabricating method of capacitor - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor is provided to obtain a high capacitance by maximizing a surface area of a lower electrode of a capacitor. CONSTITUTION: An isolation region(22) is formed on a semiconductor substrate(21). A cap insulating layer(25) covers a gate oxide layer(23) and a gate electrode(24) formed on the semiconductor substrate(21). An insulating layer(26) is deposited on the whole structure. A node contact hole is formed by a photo etching process. The node contact hole is filled by the polysilicons(27,28). An oxide layer(29) is formed thereon. The first node electrode is patterned by etching the polysilicons(27,28). The polysilicon(28) is exposed by etching the oxide layer. The second node electrode is formed by growing a GeSi polysilicon(30). The remaining oxide layer(30) is removed. A dielectric layer(31) is formed thereon. A plate electrode is formed by using a polysilicon(32).

Description

Capacitor Manufacturing Method {FABRICATING METHOD OF CAPACITOR}

The present invention relates to a method for manufacturing a capacitor, and particularly, in a limited area and height, it is possible to maximize the surface area of the capacitor lower electrode to secure high capacitance, and in a fixed capacitance, to minimize the area and height of the capacitor to improve chip integration. The present invention relates to a capacitor manufacturing method suitable for the present invention.

If described in detail with reference to the cross-sectional view shown in Figures 1a to 1e attached to a conventional capacitor manufacturing method as follows.

First, as shown in FIG. 1A, an isolation region 2 is formed on a semiconductor substrate 1 to define an active region, and then the top and side surfaces of the active region and the isolation region 2 are covered with a cap insulating film 5. The stacked gates of the true gate oxide film 3 and the gate electrode 4 are patterned to be spaced apart from each other.

As shown in FIG. 1B, the insulating layer 6 is deposited and planarized on the upper surface of the resultant layer, and then a photolithography process is performed to expose the active region of the semiconductor substrate 1 corresponding to the inter-gate separation region. A contact hole is formed.

1C, the polysilicon 7 and the PSG film 8 are sequentially formed on the upper surface of the resultant, and the PSG film 8 and the polysilicon 7 are sequentially formed through photolithography. By etching, the first node electrode is patterned. At this time, the patterning area through photolithography is reduced due to the high integration of the memory device, so that the surface area of the first node electrode is reduced, so that the formation thickness of the PSG film 8 is increased to secure the required capacitance. Increasing the surface area of the electrode.

Then, as shown in FIG. 1D, polysilicon 9 is formed on the upper surface of the resultant, and then polysilicon is formed on side surfaces of the laminated PSG film 8 and polysilicon 7 through blanket etching. A sidewall of 9) is formed to pattern the second node electrode.

Then, as shown in FIG. 1E, the PSG film 8 is removed, a dielectric film 10 is formed on the upper surface, and a polysilicon 11 is applied to form a plate electrode.

However, in the conventional capacitor manufacturing method as described above, when the PSG film is thickly formed to secure the capacitance, there is a problem in that it is difficult to proceed with the subsequent process due to an increase in the step with the peripheral area, in particular focusing in the subsequent photolithography process. The defects cause the defects of the wirings and deteriorate the reliability of the memory device.

The present invention has been made to solve the conventional problems as described above, the object of the present invention is to maximize the surface area of the capacitor lower electrode in a limited area and height to ensure a high capacitance, in a fixed capacitance of the capacitor It is to provide a capacitor manufacturing method that can improve the chip integration by minimizing the area and height.

Figure 1a to 1e is a cross-sectional view showing a conventional capacitor manufacturing method.

2a to 2f are cross-sectional views showing an embodiment of the present invention.

*** Explanation of symbols for main parts of drawing ***

21: semiconductor substrate 22: isolation area

23: gate oxide film 24: gate electrode

25: cap insulation film 26: insulation film

27,30,32: Polysilicon 28: Polysilicon with uneven surface

29: oxide film 31: dielectric film

A capacitor manufacturing method for achieving the object of the present invention as described above comprises the steps of: patterning a gate having a cap insulating film and a sidewall on the semiconductor substrate spaced apart from each other; Forming a node contact hole by forming a first insulating layer on the upper surface of the resultant, planarizing the same, and then photoetching the first insulating layer to expose the semiconductor substrate in the gap between gates; Sequentially forming first polysilicon and rugged polysilicon on the top surface of the resultant to fill node contact holes, and then forming an oxide film on the top; On the resultant, the oxide layer, the uneven surface polysilicon and the first polysilicon are sequentially etched through the photolithography to pattern the first node electrode, and the oxide layer is blanket-etched to protrude the uneven surface of the polysilicon. Exposing it; Selectively growing a second polysilicon on an exposed region of the polysilicon having an uneven surface to form a second node electrode, removing a residual oxide film, and sequentially forming a dielectric film and a plate electrode on the upper surface; It is characterized by comprising a.

Referring to the cross-sectional view shown in Figure 2a to 2f attached to the capacitor manufacturing method according to the present invention as an embodiment in detail as follows.

First, as shown in FIG. 2A, an isolation region 22 is formed on the semiconductor substrate 21 to define an active region, and then the top and side surfaces of the active region and the isolation region 22 are covered with a cap insulating layer 25. The stacked gates of the true gate oxide layer 23 and the gate electrode 24 are patterned to be spaced apart from each other.

As shown in FIG. 2B, the insulating layer 26 is deposited and planarized on the upper surface of the resultant layer, and then a photolithography process is performed to expose the active region of the semiconductor substrate 21 corresponding to the inter-gate separation region. A contact hole is formed.

As shown in FIG. 2C, polysilicon 27 and polysilicon 28 having uneven surfaces are sequentially formed on the upper surface of the resultant to fill the node contact hole, and then an oxide layer 29 is formed thereon. do.

As shown in FIG. 2D, the oxide film 29, the uneven surface polysilicon 28 and the polysilicon 27 are sequentially etched through the photolithography on the resultant product on which the oxide film 29 is formed. After patterning the node electrode, the oxide film 29 is blanket-etched to expose a protruding region of the polysilicon 28 having a rough surface.

As shown in FIG. 2E, GeSi polysilicon 30 is grown on the resultant through selective epitaxial using SiH ₄ + GeH ₄ gas to form a second node electrode, and then the remaining oxide film ( 29) is removed by wet etching.

As shown in FIG. 2F, the dielectric layer 31 is formed on the resultant from which the oxide layer 29 is removed, and the polysilicon 32 is applied to form a plate electrode.

Capacitor manufacturing method according to the present invention as described above can maximize the surface area of the lower electrode of the capacitor in a limited area and height to ensure a high capacitance, and in a fixed capacitance to minimize the area and height of the capacitor to improve the chip integration It can be effected.

Claims (2)

Patterning the gate insulating film and the gate having a sidewall on the semiconductor substrate so as to be spaced apart from each other; Forming a node contact hole by forming a first insulating layer on the upper surface of the resultant, planarizing the same, and then photoetching the first insulating layer to expose the semiconductor substrate in the gap between gates; Forming a first polysilicon and an uneven surface of polysilicon on the upper surface of the resultant to fill the node contact hole, and then forming an oxide layer on the upper surface of the resultant; On the resultant, the oxide layer, the uneven surface polysilicon and the first polysilicon are sequentially etched through the photolithography to pattern the first node electrode, and the oxide layer is blanket-etched to protrude the uneven surface of the polysilicon. Exposing it; Selectively growing a second polysilicon on an exposed region of the polysilicon having an uneven surface to form a second node electrode, removing a residual oxide film, and sequentially forming a dielectric film and a plate electrode on the upper surface; Capacitor manufacturing method comprising a. The method of claim 1, wherein the second polysilicon is formed of SiSi ₄ + GeH ₄ gas, wherein the GeSi polysilicon is grown through selective epitaxial.