KR100269621B1 - Method of fabricating capacitor - Google Patents

Abstract

The present invention relates to a method of forming a capacitor which simplifies a process for forming a storage electrode and improves a step with surroundings. Forming a first insulating layer so as to have a contact hole; forming a plug contacting an impurity region by filling a contact hole; and sequentially forming an etch stop layer and a second insulating layer to expose the plug on the first insulating layer. Exposing an upper surface of the second insulating layer, forming a polysilicon pattern, which is a storage electrode of the capacitor, to cover the side surface and the interspace of the second insulating layer; and removing the second insulating layer to expose the etch stop layer. And forming a dielectric layer and a plate electrode on the storage electrode.

In the present invention, since the node contact can be formed by one photo and etching process, the process procedure is simplified. Therefore, as the storage electrode can be formed by one node contact, since the insulating layer stacked for forming the node contact can be partially omitted, the storage electrode of the capacitor has an advantage of improving the step with respect to the surroundings.

Description

Capacitor Formation Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor, and more particularly, to a method of forming a capacitor in which a process procedure is simplified and a step with surroundings is improved.

Many studies have been conducted to increase the storage density so that the capacitor has a constant capacitance even if the cell area is reduced due to the high integration of the semiconductor.

In order to increase the storage density, there is a method of forming a capacitor in a three-dimensional structure of a stack or a trench.

The laminated structure among the capacitors having the three-dimensional structure is a structure that is easy to manufacture and suitable for mass productivity, while increasing the storage capacity and being immune to the disturbance of charge information caused by alpha particles.

The stacked capacitor is classified into a double stacked structure, a fin structure or a crown structure according to the shape of the storage electrode.

1A to 1F are manufacturing process diagrams showing capacitor formation according to the prior art. Hereinafter, the formation of a conventional capacitor will be described with reference to the drawings.

In the semiconductor substrate 100, a field oxide film (not shown) defining an active region and a field region of a device is formed, and a gate electrode 102 is formed on the device region.

A transistor is manufactured by forming an impurity diffusion region 120 used as a source / drain region in active regions on both sides of the gate electrode 102.

As shown in FIG. 1A, silicon oxide or the like is deposited on the entire surface of the above-described structure by a chemical vapor deposition (CVD) method to form a first insulating layer 108.

Subsequently, a photo and etching process is performed to expose the impurity diffusion region 120 in the first insulating layer 108 to form a first node contact h1.

As shown in FIG. 1B, a first polycrystalline silicon layer is formed on the first insulating layer 108 to fill the first node contact h1. Subsequently, the first polysilicon layer is etched back to expose the first insulating layer 108 to form a first plug 122. The first plug 122 is in contact with the impurity diffusion region 120.

Subsequently, although not shown in the drawing, a bit line is formed to be connected to the neighboring impurity diffusion region.

As shown in FIG. 1C, after the second insulating layer 110 is formed on the first insulating layer 108 including the first plug 122, the first plug is formed at a portion corresponding to the first node contact h1. A second node contact h2 exposing 122 is formed.

As shown in FIG. 1D, the second polysilicon layer and the third insulating layer are sequentially formed on the second insulating layer 110 to fill the second node contact h2, and then cover the second node contact h2. The pattern is etched to define a region s1 in which the storage electrode is to be formed.

Reference numeral 124 denotes a pattern etched second polycrystalline silicon layer, and reference numeral 126 denotes a pattern etched third insulating layer.

As shown in FIG. 1E, a third polysilicon layer is formed on the second insulating layer 110 to cover the patterned second polysilicon layer 124 and the third insulating layer 126.

The polysilicon sidewalls 128 are formed on the side surfaces of the patterned second polysilicon layer 124 and the third insulating layer 126 by etching back the third polysilicon layer to expose the second insulating layer.

Next, a photoresist 130 is coated on the second insulating layer 110 to cover the third insulating layer 126 and the polysilicon sidewall 128.

As illustrated in FIG. 1F, the third insulating layer is removed by a wet etching method. Thereafter, the photoresist 130 is removed to form the storage electrode 106 of the capacitor.

Here, the photoresist 130 serves to prevent the second insulating layer from being etched from the wet solution in the process of removing the third insulating layer.

Subsequently, although not shown in the figure, capacitor manufacturing is completed by sequentially forming a dielectric layer and a plate electrode on the storage electrode 106 of the capacitor.

However, in the conventional capacitor forming method, since the photo and etching processes are performed twice each when the first node contact and the second node contact are formed, the process is cumbersome, and when the first node contact and the second node contact are formed, misalignment ( There was a risk of misalignment. In addition, there was a serious problem with the step.

Accordingly, an object of the present invention is to provide a method of forming a capacitor which can simplify the process procedure by reducing the number of photo and etching processes for forming a node contact and overcome the step with surroundings.

To achieve the above object, the present invention provides a process for forming a first insulating layer to have a contact hole exposing an impurity region on a semiconductor substrate on which a transistor having an impurity region is formed, and a plug filling a contact hole to contact an impurity region. Forming a etch stop layer and a second insulating layer sequentially so that the plug is exposed on the first insulating layer, and exposing an upper surface of the second insulating layer, the side surface and the space between the second insulating layer; Forming a polysilicon pattern as a storage electrode of the capacitor so as to cover the gap; removing the second insulating layer to expose the etch stop layer; and forming a dielectric layer and a plate electrode on the storage electrode. to be.

1a to 1f is a manufacturing process showing the formation of a capacitor according to the prior art,

2a to 2f is a manufacturing process showing the formation of a capacitor according to the present invention.

Explanation of symbols on the main parts of the drawings

100, 200. Semiconductor substrate 102, 202. Gate electrode

106, 206. Storage electrodes 110, 210. Impurity diffusion region

122, 222. Plugs 124, 128, 224. Polysilicon layer

108, 110, 126, 208, 210. Insulation layer

2a to 2f is a manufacturing process showing the formation of a capacitor according to the present invention.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

As shown in FIG. 2A, a field oxide film defining an active region and a field region of an element is formed on the semiconductor substrate 200 by a method such as local oxidation. The transistor is manufactured by sequentially forming a gate electrode 204 and an impurity diffusion region 220 used as a source / drain region in the active region on both sides of the semiconductor substrate.

After the silicon oxide is deposited on the entire surface of the structure described above by the CVD method to form the first insulating layer 208, the node contact h3 exposing the impurity active region 220 is formed.

As shown in FIG. 2B, a polysilicon layer is formed on the first insulating layer 208 to fill the node contact h3. Subsequently, the polysilicon layer is etched back until the first insulating layer 208 is exposed to form the plug 222.

At this time, the plug 222 is in contact with the impurity diffusion region 220 and is electrically connected to the storage electrode of the capacitor formed in a subsequent process.

Although not shown, a bit line is formed to be connected to the neighboring impurity diffusion region.

As illustrated in FIG. 2C, a nitride film and a second insulating layer are sequentially formed on the first insulating layer 208 and then pattern-etched to expose the plug 222 to define a region s2 in which the storage electrode is to be formed. .

At this time, since the thickness of the second insulating layer is closely related to the height of the storage electrode of the capacitor, the thickness adjustment is appropriately performed when forming the second insulating layer.

Reference numeral 230 shows a pattern etched nitride film, and reference numeral 210 shows a pattern etched second insulating layer.

In the above, the pattern-etched nitride film 230 is used as an etch stop layer during the etching of the patterned second insulating layer 210 in a subsequent process.

As illustrated in FIG. 2D, the polysilicon layer 224 is formed on the patterned second insulating layer 210 to cover the plug 222.

As shown in FIG. 2E, the polysilicon layer is removed until the second insulating layer 210 is exposed to form the polysilicon pattern 224-1.

There are two methods for forming the polysilicon pattern 224-1.

First, the polysilicon layer may be removed by a chemical-mechanical polishing (CMP) method until the second insulating layer 210 is exposed.

Second, since the polysilicon layer may fall down during the etching process, first, an oxide is formed on the polysilicon layer using a photoresist or spin on glass (SOG) method to fill the valley to planarize the surface. do.

Here, the photoresist or the SOG oxide serves to support the polysilicon layer from falling down during the subsequent etching process.

Subsequently, the polysilicon layer may be removed by a CMP method or a dry etching method using an etching gas until the second insulating layer 210 is exposed.

As shown in FIG. 2F, the storage electrode 206 of the capacitor is formed by removing the second insulating layer 210 using the nitride film 230 as the etch stop layer 23.

In the present invention, since the storage electrode of the capacitor having the nitride film interposed directly on the bit line, the step with respect to the surroundings is improved.

Subsequently, although not shown in the drawing, the capacitor manufacturing is completed by sequentially forming the dielectric layer and the plate electrode on the storage electrode 206 of the capacitor.

As described above, in the capacitor forming method of the present invention, since the node contact can be formed by one photo and etching process, the process procedure is simplified.

In addition, since the insulating layer stacking process for forming the node contact can be partially omitted, and an integrated capacitor is formed on the bit line, the step is improved.

Claims (4)

Forming a first insulating layer on the semiconductor substrate on which the transistor having an impurity region is formed so as to have a contact hole exposing the impurity region; Filling the contact hole to form a plug in contact with the impurity region; Sequentially forming an etch stop layer and a second insulating layer on the first insulating layer to expose the plug; Exposing the second insulating layer, and forming a polysilicon pattern, which is a storage electrode of the capacitor, to cover the side surface and the space between the second insulating layer; Removing the second insulating layer to expose the etch stop layer; And forming a dielectric layer and a plate electrode on the storage electrode. The method according to claim 1, The polysilicon pattern formation Forming a polysilicon layer on the second insulating layer so as to cover the plug; And removing the polysilicon layer by a chemical-mechanical polishing (CMP) method until the second insulating layer is exposed. The method according to claim 1, The polysilicon pattern formation Forming a polysilicon layer on the second insulating layer so as to cover the plug; Forming a filling material layer on the polycrystalline silicon layer; Removing the polysilicon layer by a method such as CMP or dry etching until the second insulating layer is exposed; And a process of removing the filling material layer. The method according to claim 3, And the filling material layer is photoresist or spin on glass (SOG).