KR960013639B1 - Manufacture and structure of semiconductor memory cell - Google Patents

Abstract

The method of manufacturing capacitor of semiconductor memory cell comprises the steps of : forming a hemispherical structure by thermal process after forming a first polysilicone layer(36), an insulating layer(38) and a second polysilicone layer(40); etch back after depositing a mask layer on the hemispherical polysilicone layer(40) to leave the mask layer(42) on the groove; blanket etching of the second polysilicone layer (40), and forming plural holes on the insulating layer(38) by etching the insulating layer(38); and forming a storage electrode(50) of a capacitor by photolithography after forming a third polysilicone layer(44), etching the third polysilicon layer(44) and the second polysilicon layer(40) to expose some of the insulating layer(38) and removing the insulating layer(38).

Description

Capacitor Manufacturing Method and Structure of Semiconductor Memory Cell

1 is a partial cross-sectional view for explaining a method of manufacturing a capacitor of a conventional semiconductor memory cell.

2 is a partial cross-sectional view for explaining a method of manufacturing a capacitor of a semiconductor memory cell of the present invention.

The present invention relates to a capacitor manufacturing method and structure of a semiconductor memory cell, and more particularly to a manufacturing method and structure of a capacitor having a large charge capacity used in a DRAM cell.

An example of a method of manufacturing a capacitor of a semiconductor memory cell is shown in FIG. 1, which first defines an active region on a semiconductor substrate 10, and then includes a gate electrode 12, a source / drain region 13, and an insulating layer 14. ).

Then, polysilicon 16 is deposited and a hemispherical (HEMISPHERICAL) structure is formed through appropriate heat treatment. Then, an oxide film or a spin on glass (SOG) film is formed and a blanket (BLANKET) etching is performed. The back of the polysilicon film 16 so as to be filled only in the grooves of the unevenness of the polysilicon film 16, and then etched in the polysilicon etch atmosphere to form the shape as shown in FIG.

Then, as shown in (B) of FIG. 1, the residual oxide film 17 of the groove portion is wet-etched and removed, and then the photo Norm of the capacitor is formed of polysilicon by a photolithography process.

Next, the capacitor dielectric film 18 is formed and the plate electrode 19 is formed of polysilicon to complete the fabrication of the capacitor.

Thereafter, the contact phase between the metal and the drain DRAIN is opened through BPSG deposition 20 and flowing to form the metal wire 22.

However, since the capacitor according to the conventional method described above has a small surface area of the norwood poly, the charging capacity is not only small, and the damage caused by the damage due to RIE (REATIVE ION ETCHING) is performed on the norwood poly. there was.

Accordingly, an object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor memory cell capable of preventing damage to the surface area of the nord poly.

Another object of the present invention is to provide a capacitor of a semiconductor memory cell capable of increasing the charge capacity by increasing the surface area of the nord poly.

2 is a partial cross-sectional view illustrating a method of manufacturing a capacitor of a semiconductor memory cell of the present invention.

The present invention provides a method of forming a capacitor of a memory cell on a semiconductor substrate by forming a gate electrode and a source / drain region, covering a surface with an insulating layer, opening a contact hole to be connected to the capacitor's nord electrode, and (1) After forming the first polysilicon layer 36, forming a hemispherical structure by forming a second polysilicon layer 40 and appropriate heat treatment, (2) a mask on the hemispherical polysilicon layer 40 Deposition and etch back the layer so that the mask layer 42 remains only on the flaw of the hemispherical irregularities, (3) Blank etching the second polysilicon layer 40 using the mask layer 42 as an etching mask When the insulating film 38 under the peak portion of the second polysilicon layer is exposed, a plurality of holes are formed in the insulating film 38 by etching the insulating film 38 using the remaining portion of the second polysilicon layer 40 as an etching mask. Forming, (4) third poly After forming the silicon 44, the third polysilicon 44 and the second polysilicon 40 are etched to expose a portion of the upper portion of the insulating film 38, the insulating film 38 is removed, and a photolithography process is performed. Forming a capacitor storage electrode 50 of the capacitor, (5) forming a capacitor dielectric film 52 on the surface of the capacitor storage electrode 50, and forming a plate electrode 54 of the capacitor thereon. Lose.

In step (1), the insulating film 38 is selected from an oxide film, BPSG, SOG, or TEOS. In step (2), the mask layer on the polysilicon layer 40 is formed of an oxide film or SOG.

When removing the insulating film 38 in the step (4), the blanket etching or wet etching.

One embodiment of the capacitor manufacturing method of the semiconductor memory cell thus produced is shown in FIG.

One embodiment of a method of manufacturing a capacitor of a semiconductor memory cell of the present invention is shown in FIG.

As shown in Article 2 A, first, an active region is defined on the semiconductor substrate 30, the gate electrode 32, the source / drain region 33, and the insulating film 34 are formed, and then the surface is insulated. After covering the layer and opening the contact hole connected to the nod electrode of the capacitor, the first polysilicon layer 36 is formed to form the capacitor of the memory cell thereon, the insulating film 38 is formed, and then the second polysilicon is formed. The hemispherical structure is formed by forming the layer 40 and performing appropriate heat treatment.

At this time, in order to further improve the flatness of the polysilicon 36, a process of deposition-etch back deposition may be used. In the above, the insulating film 38 may use a general oxide film (eg, LTO, HTO, HLD, etc.), but may use BPSG in terms of flatness, or SOG and TEDS (TETRA-ETHLY-ORTHO-SILICATE). Then, the polysilicon 40 is deposited and then subjected to appropriate heat treatment to make a hemispherical structure (HEMISPHERICAL).

Subsequently, the oxide film or SOG is deposited and etched back so that the oxide film or SOG 42 remains only in the uneven groove portion.

Next, as shown in FIG. 2B, the polysilicon layer 40 is blanket-etched using the oxide film or the SOG 42 as an etching mask, and the polysilicon layer 40 is exposed when the insulating film 38 under the peak portion of the polysilicon layer is exposed. Anisotropic etch is performed on the insulating film 38 using the remaining portion of the?

Thereafter, the third polysilicon 44 is conformally deposited, and then the polysilicon 40 and 44 are blanket-etched or wet-etched to expose a portion of the upper portion of the insulating film 38. 38) is removed and a photolithography process forms the nod electrode 50 of the capacitor as shown in C of FIG.

Thereafter, as shown in FIG. 2D, the capacitor dielectric film 52 is formed on the surface of the capacitor, and the plate electrode 54 of the capacitor is formed by depositing polysilicon and then photo-etching the BPSG 56. After depositing the metal and the contact window between the drain (DRAIN) to form a metal wiring (58).

The capacitor of the semiconductor memory cell formed as described above may include a first polysilicon layer 36 on a transistor including a gate electrode 32, a source / drain region 33, and an insulating layer 34 on the semiconductor substrate 30. On the first polysilicon layer 36, a storage norm electrode 50 of a capacitor including a third polysilicon layer 44 formed in a plurality of pillars is formed. A capacitor dielectric film 52 is formed on the surface of the capacitor norm electrode 50, and a plate electrode 54 of a capacitor made of polysilicon is formed on the capacitor dielectric film 52. The nord electrode 50, the dielectric film 52 and the plate electrode 54 form a capacitor, which is formed in the form of a plurality of pillars on the first polysilicon layer 36. Having the third polysilicon layer 44, the surface area is increased to increase the filling capacity. A BPSG 56 is formed on the capacitor to expose the drain DRAIN, and a metal wiring 58 is formed on the BPSG 56.

As described above, according to the method of the present invention, if the thickness of the insulating film 38 is adjusted, a sufficiently large filling capacity can be obtained, and since wet etching is also available, damage by RIE is reduced, and polysilicon is formed during the formation of norwood poly. When the oxide film is etched using the etching mask, even if the thickness of the polysilicon is slightly adjusted, the loss of the pattern during the oxide film etching is almost eliminated.

Claims (5)

A method of manufacturing a capacitor of a memory cell on a semiconductor substrate, the method comprising forming a gate electrode source / drain region, covering a surface with an insulating layer, opening a contact hole to be connected to a non-electrode capacitor, and manufacturing a capacitor of the memory cell thereon. After forming the silicon layer 36 and the insulating film 38, the second polysilicon layer 40 is formed and appropriate heat treatment to form a hemispherical structure, (2) a half-shaped polysilicon Deposition and etch back the mask layer on the layer 40 so that the mask layer 42 remains only on the flaw of the hemispherical irregularities. (3) The second polysilicon layer (using the mask layer 42 as an etching mask) 40 is blanket-etched and exposed to the insulating film 38 under the peak of the second polysilicon layer, the insulating film 38 is etched by etching the insulating film 38 using the remaining portion of the second polysilicon layer 40 as an etching mask. Forming a plurality of holes in the (4) After forming the third polysilicon 44, the third polysilicon 44 and the second polysilicon 40 are etched to expose a portion of the upper portion of the insulating film 38, and the insulating film 38 is removed. And forming the capacitor storage electrode 50 of the capacitor through a photolithography process (5) forming a capacitor dielectric layer 52 on the surface of the capacitor storage electrode 50, and the plate electrode 54 of the capacitor thereon. A capacitor manufacturing method of a semiconductor memory cell comprising the step of forming a. The method of manufacturing a capacitor of a semiconductor memory cell according to claim 1, wherein in the first step (1), the dielectric film (38) is selected from an oxide film, BPSG, SOG, or TEOS. The method of manufacturing a capacitor of a semiconductor memory cell according to claim 1, wherein in step (2), the mask layer on the polysilicon layer (40) is formed of an oxide film or SOG. The method of manufacturing a capacitor of a semiconductor memory cell according to claim 1, wherein a blanket etching or a wet etching is performed when the insulating film is removed in step (4). A capacitor for a semiconductor memory cell comprising a gate electrode, a source / drain region, and an insulating film on a semiconductor substrate, the capacitor comprising: a storage electrode made of a plurality of polysilicon pillars in electrical contact with a polysilicon layer on the semiconductor memory cell; A capacitor for a semiconductor memory cell, characterized in that it comprises a silicon layer, a dielectric formed on a plurality of polysilicon pillar surfaces, and a plate electrode made of polysilicon formed on the dielectric surface.