KR940022855A - Capacitor Manufacturing Method of Semiconductor Memory Cell - Google Patents

Capacitor Manufacturing Method of Semiconductor Memory Cell Download PDF

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Publication number
KR940022855A
KR940022855A KR1019930003594A KR930003594A KR940022855A KR 940022855 A KR940022855 A KR 940022855A KR 1019930003594 A KR1019930003594 A KR 1019930003594A KR 930003594 A KR930003594 A KR 930003594A KR 940022855 A KR940022855 A KR 940022855A
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South Korea
Prior art keywords
forming
capacitor
layer
polysilicon
insulating film
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KR1019930003594A
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Korean (ko)
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KR960013639B1 (en
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송주현
김인기
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문정환
금성일렉트론 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 기판 상에 게이트전극 및 소오스/드레인 영역을 형성하고, 표면을 절연층으로 덮고 캐패시터의 노우드 전극과 연결한 콘택홀을 연후 그 위에 메모리 셀의 캐패시터를 제조하는 방법으로서, (1) 제1폴리실리콘층(36)을 형성하고, 절연막(38)를 형성한후, 제2폴리실리콘층(40)를 형성하고 적절한 열처리를 함으로써 반구모양의 구조를 형성하는 단계, (2) 반구형의 폴리실리콘층(40) 위에 마스크층을 데포지션하고 에치백하여 반구형 요철의 홈 부위에만 마스크층(42)이 남도록하는 단계, (3) 상기 마스크층(42)을 식각 마스크로하여 제2폴리실리콘층(40)를 블랭킷식각하고, 제2폴리실리콘층의 봉우리부분 밑의 절연막(38)이 드러나면 제2폴리실리콘층(40)의 나머지부분을 식각 마스크로하여 절연막(38)을 에치하여 저연막(38)에 다수의 구멍을 형성하는 단계, (4) 제3폴리실리콘층(44)을 형성한 다음, 제3폴리실리콘층(44) 및 제2폴리실리콘층(40)을 식각하여 절연막(38)의 윗부분 일부가 드러나게 하고, 절연막(38)을 제거하고 사진식각 공정을 통해 캐패시터의 저장용 전극(50)을 형성하는 단계, (5) 캐패시터의 저장용 전극(50) 표면에 캐패시터 유전막(52)을 형성하고, 그 위에 캐패시터의 플레이트 전극(54)을 형성하는 단계로 이루어진다.The present invention provides a method for forming a capacitor of a memory cell on a semiconductor substrate by forming a gate electrode and a source / drain region, covering a surface with an insulating layer, opening a contact hole connected with the nord electrode of the capacitor, and (1) ) Forming a hemispherical structure by forming the first polysilicon layer 36, forming the insulating film 38, and then forming the second polysilicon layer 40 and performing appropriate heat treatment, (2) Depositing and etching back the mask layer on the polysilicon layer 40 of the polysilicon layer 40 so that the mask layer 42 remains only in the groove portion of the hemispherical irregularities, (3) the second poly using the mask layer 42 as an etching mask When the silicon layer 40 is blanket-etched and the insulating film 38 under the peak portion of the second polysilicon layer is exposed, the remaining portion of the second polysilicon layer 40 is used as an etch mask to etch the insulating film 38 into a low state. Form a plurality of holes in the smoke screen 38 Step (4) After forming the third polysilicon layer 44, the third polysilicon layer 44 and the second polysilicon layer 40 are etched to expose a portion of the upper portion of the insulating film 38, (38) removing and forming a storage electrode 50 of the capacitor through a photolithography process, (5) forming a capacitor dielectric film 52 on the surface of the storage electrode 50 of the capacitor, on top of the capacitor The plate electrode 54 is formed.

Description

반도체 메모리 셀의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Memory Cell

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 반도체 메모리 셀의 케패시터 제조방법을 설명하기 위한 일부 단면도이다.2 is a partial cross-sectional view for explaining a method of manufacturing a capacitor of a semiconductor memory cell of the present invention.

Claims (5)

반도체 기판 상에 게이트전극 및 소오스/드레인 영역을 형성하고, 표면을 절연층으로 덮고 캐패시터의 노우드 전극과 연결할 콘택홀을 연후 그 위에 메모리 셀의 캐패시터를 제조하는 방법에 있어서, (1) 제1폴리실리콘층(36)을 형성하고, 절연막(38)를 형성한후, 제2폴리실리콘층(40)를 형성하고 적절한 열처리를 함으로써 반구모양의 구조를 형성하는 단계, (2) 반구형의 폴리실리콘층(40) 위에 마스크층을 데포지션하고 에치백하여 반구형 요철의 홈 부위에만 마스크형(42)이 남도록하는 단계, (3) 상기 마스크층(42)을 식각 마스크로하여 제2폴리실리콘층(40)를 불랭킷식각하고, 제2폴리실리콘층의 봉우리부분 밑의 절연막(38)이 드러나면 제2폴리실리콘층(40)의 나머지부분을 식각 마스크로하여 절연막(38)을 에치하여 절연막(38)에 다수의 구멍을 형성하는 단계, (4) 제3폴리실리콘(44)을 형성한 다음, 제3폴리실리콘(44) 및 제2폴리실리콘층(40)을 식각하여 절연막(38)의 윗부분 일부가 드러나게 하고, 절연막(38)을 제거하고 사진식각 공정을 통해 캐패시터의 저장용 전극(50)을 형성하는 단계를 (5) 캐패시터의 저장용 전극(50) 표면에 캐패시터 유전막(52)을 형성하고, 그 위에 캐패시터의 플레이트 전극(54)을 형성하는 단계로 이루어지는 반도체 메모리 셀의 캐패시터 제조방법.1. A method of forming a capacitor of a memory cell on a semiconductor substrate, the method comprising forming a gate electrode and a source / drain region, covering a surface with an insulating layer, opening a contact hole to be connected to the capacitor's nord electrode, and manufacturing a capacitor thereon. Forming a polysilicon layer 36, forming an insulating film 38, and then forming a hemispherical structure by forming a second polysilicon layer 40 and performing appropriate heat treatment, (2) hemispherical polysilicon Deposition and etch back the mask layer on the layer 40 so that the mask type 42 remains only in the groove portion of the hemispherical irregularities, (3) the second polysilicon layer using the mask layer 42 as an etching mask ( If the insulating film 38 is unetched and the insulating film 38 under the peak portion of the second polysilicon layer is exposed, the insulating film 38 is etched using the remaining portion of the second polysilicon layer 40 as an etching mask. Forming a plurality of holes) (4) After forming the third polysilicon 44, the third polysilicon 44 and the second polysilicon layer 40 are etched to expose a portion of the upper portion of the insulating film 38, and the insulating film 38 is removed. (5) forming a capacitor dielectric layer 52 on the surface of the storage electrode 50 of the capacitor, and forming a plate electrode 54 of the capacitor thereon. And forming a capacitor). 제1항에 있어서, 제(1)단계에서 절연막(38)은 산화막, BPSG, SOG, 혹은 TEOS에서 선택하여 형성하는 것을 특징으로 하는 반도체 메모리 셀의 캐패시터 제조방법.The method of manufacturing a capacitor of a semiconductor memory cell according to claim 1, wherein in step (1), the insulating film is selected from an oxide film, BPSG, SOG, or TEOS. 제1항에 있어서, 제(2)단계에서 폴리실리콘층(40) 위의 마스크층은 산화막 또는 SOG로 형성하는 것을 특징으로 하는 반도체 메모리 셀의 캐패시터 제조방법.The method of manufacturing a capacitor of a semiconductor memory cell according to claim 1, wherein in step (2), the mask layer on the polysilicon layer (40) is formed of an oxide film or SOG. 제1항에 있어서, 제(4)단계에서 절연막(38)을 제거할대는 블랭킷식각 혹은 습식식각하는 것을 특징으로 하는 반도체 메모리 셀의 캐패시터 제조방법.The method of manufacturing a capacitor of a semiconductor memory cell according to claim 1, wherein the removal of the insulating film (38) is performed by blanket etching or wet etching. 반도체 메모리 셀 용의 캐패시터로서, 폴리실리콘 바닥위에 세워진 다수의 폴리실리콘 기둥으로 된 저장전극과, 상기 다수의 폴리실리콘 기둥표면에 부착된 유전체와, 상기 유전체 표면에 부착된 폴리실리콘으로 된 플레이트 전극으로 이루어진 것이 특징인 반도체 메모리 셀 용 캐패시터.A capacitor for a semiconductor memory cell, comprising: a storage electrode of a plurality of polysilicon pillars erected on a polysilicon bottom, a dielectric attached to the surface of the plurality of polysilicon pillars, and a plate electrode of polysilicon attached to the dielectric surface Capacitor for semiconductor memory cells characterized in that made. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930003594A 1993-03-11 1993-03-11 Manufacture and structure of semiconductor memory cell KR960013639B1 (en)

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KR1019930003594A KR960013639B1 (en) 1993-03-11 1993-03-11 Manufacture and structure of semiconductor memory cell

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KR940022855A true KR940022855A (en) 1994-10-21
KR960013639B1 KR960013639B1 (en) 1996-10-10

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