JPH07307395A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the capacity of a memory cell without increasing the allowable area of a capacitor by a method wherein when SOG films and silicon oxide films are formed in a laminated structure and a contact hole between a storage electrode and a semiconductor substrate is formed, a cylindrical storage electrode having a fin-shaped part is formed simultaneously with the formation of the contact hole. CONSTITUTION:A polycrystalline silicon film 119 is formed in a film thickness of the radius or longer of a contact hole 118. Subsequently, an entire surface etching of the film 119 is performed and the film 119 is left only in the part of the hole 118. Subsequently, SOG films 113 and 115 and silicon oxide films 112, 114 and 116 are removed. A lower polycrystalline silicon electrode 108 is formed. The form of the electrode 108 is formed into a cylindrical form having a fin-shaped part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a polycrystalline silicon film provided on a semiconductor substrate is used as an electrode of a memory element and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices have been miniaturized and integrated, semiconductor memory elements (hereinafter simply referred to as memory cells)
The area per piece is small. Therefore, in order to secure the memory cell capacity, a stacked capacitor using a large step on the semiconductor substrate is adopted instead of the conventional planar capacitor formed on the semiconductor substrate. In a stacked capacitor, polycrystalline silicon is used as an electrode, and a capacitive insulating film is formed on this electrode.

A conventional stacked capacitor and its manufacturing method will be described below. FIG. 15 is a schematic sectional view of a stacked capacitor formed by a conventional manufacturing method. 16 to 19 are sectional views in order of steps of the manufacturing method.

In FIGS. 15 to 19, 1 is a semiconductor substrate, 2 is a LOCOS oxide film, 3 is a gate oxide film, 4 is a gate electrode, 5 is a sidewall, 6 is an n-type diffusion layer, 7 is a silicon oxide film, Reference numeral 8 is a lower polycrystalline silicon electrode, 9 is a capacitive insulating film, 10 is an upper polycrystalline silicon electrode, 11 is a silicon oxide film, and 12 is a photoresist film.

The process steps will be described below. Semiconductor substrate 1
LOCOS oxide film 2 on top, by the method already known,
After forming the gate oxide film 3, the gate electrode 4, the sidewall 5, and the n-type diffusion layer (source diffusion layer, drain diffusion layer) 6, a silicon oxide film 11 is formed so as to cover them (FIG. 16).

Subsequently, the silicon oxide film 11 is etched by using the photoresist film 12 as a mask to form a contact hole on the n-type diffusion layer 6 on the surface of the semiconductor substrate 1 (FIG. 1).
7). Next, after removing the photoresist film 12, CV
A polycrystalline silicon film is formed by the D method, impurities are diffused into the polycrystalline silicon film to enhance conductivity, and then the polycrystalline silicon film is selectively etched by a known method to form the lower polycrystalline silicon electrode 8 Are formed (FIG. 18). On the lower polycrystalline silicon electrode 8, a capacitance insulating film 9 is formed by sequentially stacking a silicon nitride film and a silicon oxide film. After that, a polycrystalline silicon film is formed on the capacitor insulating film 9, its conductivity is increased by impurity diffusion, and then selectively etched by a known method to form an upper polycrystalline silicon electrode 10 (FIG. 19). As described above, the conventional stacked capacitor is formed.

[0007]

However, the above-mentioned conventional manufacturing method has a problem in that a sufficient memory cell capacity is secured with the miniaturization of the memory cell.

The present invention solves the conventional problems described above, and provides a semiconductor device capable of increasing the memory cell capacitance without increasing the capacitor allowable area and a method of manufacturing the same, by a method corresponding to miniaturization. It is a thing.

[0009]

In order to achieve this object, a semiconductor device according to the present invention comprises a first conductive film provided on a semiconductor substrate and an insulating film covering at least a part of the first conductive film. And a second conductive film formed so as to cover the insulating film, a capacitor is formed, and the capacitor has a cylindrical shape having a fin-shaped portion.

Further, the first conductive film provided on the semiconductor substrate, the insulating film covering at least a part of the first conductive film, and the second conductive film formed so as to cover the insulating film form a capacitance. An element is formed, the capacitive element has a cylindrical shape with a fin-shaped portion, and an opening is formed in the upper portion of the capacitive element.

To achieve this object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a silicon nitride film on a step of a semiconductor substrate, a step of forming a hygroscopic film on the silicon nitride film, A step of forming a moisture resistant film on the hygroscopic film, a step of forming contact holes in the silicon nitride film, the hygroscopic film and the moisture resistant film, and a step of forming a contact hole in the silicon nitride film, the hygroscopic film, the moisture resistant film and the contact hole. No. 1 conductive film is formed, the conductive film is entirely etched to leave the first conductive film only inside the contact hole, the hygroscopic film and the moisture resistant film are removed, and the first conductive film is removed. The method includes a step of forming a capacitive insulating film on the film surface and a step of forming a second conductive film on the capacitive insulating film.

Further, a step of forming a silicon nitride film on a step formed on a semiconductor substrate, a step of forming a hygroscopic film on the silicon nitride film, and a step of forming a moisture resistant film on the hygroscopic film. A step of forming a contact hole in the hygroscopic film and the moisture resistant film, a step of forming a first conductive film in the silicon nitride film, the hygroscopic film, the moisture resistant film and the contact hole;
Of selectively etching the conductive film, the step of removing the hygroscopic film and the moisture resistant film to form the second conductive film, and the step of forming the capacitor insulating film on the second conductive film. And a step of forming a third conductive film on the capacitive insulating film.

The thickness of the second conductive film is 95% or less of the radius of the contact hole.

Further, it has a plurality of laminated bodies of a hygroscopic film and a moisture resistant film. Furthermore, the hygroscopic film is an SOG film.

[0015]

According to the present invention, since the SOG film and the silicon oxide film have a laminated structure, a cylindrical storage electrode having a fin-shaped portion is formed at the same time when the contact hole between the storage electrode and the semiconductor substrate is formed. Can be formed. Therefore, since a storage electrode having a large surface area can be formed at the time of forming a contact hole by dry etching, it becomes possible to easily secure the memory cell capacity even if miniaturization progresses.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to a first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of this embodiment. In FIG. 1, 101 is a semiconductor substrate, 102 is a LOCOS oxide film, 103 is a gate oxide film, 104 is a gate electrode, 105 is a sidewall,
106 is an n-type diffusion layer, 107 is a silicon nitride film, 108 is a lower polycrystalline silicon electrode, 109 is a capacitive insulating film, and 110 is an upper polycrystalline silicon electrode.

The shape of the lower polycrystalline silicon electrode 108 is a cylinder having a fin-shaped portion. As a result, the surface area of the lower polycrystalline silicon electrode 108, which is a storage electrode, increases, so that the memory cell capacitance can be increased without increasing the capacitor allowable area of the memory cell. Therefore, a sufficient memory cell capacity can be easily obtained even with miniaturization.

Next, a method of manufacturing the semiconductor device according to the first embodiment of the present invention will be described in detail with reference to the drawings.

2 to 7 are schematic cross-sectional views in the order of steps in this manufacturing method. Only the memory cell forming process is shown for simplification of the drawing.

First, on the semiconductor substrate 101, the LOCOS oxide film 102, the gate oxide film 103, and the
After sequentially forming the gate electrode 104, the sidewall 105, and the n-type diffusion layer (source diffusion layer, drain diffusion layer) 106, a silicon nitride film 107 is formed by a CVD method. Then, the silicon oxide film 112 is formed by plasma CVD.
SOG film 113, silicon oxide film 114, SOG film 115,
And silicon oxide films 116 are formed alternately (FIG. 2).

Next, using the photoresist film 117 as a mask, a contact hole 118 is formed on the n-type diffusion layer 106 on the surface of the semiconductor substrate 101 by a dry etching method.
Etching at that time is performed while forming a reaction product on the inner wall surface of the contact hole 118 in order to obtain anisotropy. However, the silicon oxide films 112 and 11 which are water resistant films
SOG film 11 which is a hygroscopic film sandwiched between 4, 116
Since water is released at the portions 3 and 115 at the same time as the etching, reaction products are not formed at the portions SOG films 113 and 115. Therefore, if overetching is performed in this state, S without reaction products is attached.
The OG films 113 and 115 are laterally etched as shown in the figure. As a result, an annular recess is formed on the inner wall surface of the contact hole 118 (FIG. 3).

Subsequently, the polycrystalline silicon film 119 is formed in the contact hole 118 while introducing impurities by the CVD method.
Is formed with a film thickness equal to or larger than the radius. The contact hole 118 is filled with polycrystalline silicon by forming the film with a film thickness equal to or larger than the radius (FIG. 4).

Then, the entire surface of the polycrystalline silicon film 119 is etched to leave the polycrystalline silicon only in the contact hole 118 portion (FIG. 15).

Subsequently, the SOG film 11 is formed by using a hydrofluoric acid solution.
3, 115, and silicon oxide films 112, 114, 116
To remove. At this time, since the gate electrode portion is protected by the silicon nitride film, the lower polycrystalline silicon electrode 108 is formed without being etched during etching (FIG. 6).

Subsequently, a capacitive insulating film 109 made of, for example, a silicon nitride film and a silicon oxide film is formed on the lower polycrystalline silicon electrode 108, and polycrystalline is formed on the capacitive insulating film 109 by introducing an impurity by a CVD method. Forming a silicon film,
Etching is performed using the photoresist film as a mask to form the upper polycrystalline silicon electrode 110 (FIG. 7). A memory cell is formed as described above.

In the method of this embodiment, since the SOG films 112, 114, and 116 are etched at the time of etching the contact holes, the size of the fin-shaped portion can be controlled by the overetching amount of the contact holes, and the miniaturization can be achieved. It is easy to deal with. Further, since the lower polycrystalline silicon electrode 108 is formed by etching the entire surface, there is no need to pattern the polycrystalline silicon film using the photoresist film as a mask, and the process can be simplified.

Further, in the method of this embodiment, S normally performed is
The heat treatment after forming the OG films 113 and 115 is not particularly necessary. This is because the amount of water released increases and the fin-shaped portion can be formed more easily. However, since the SOG film has a strong hygroscopic property, the heat treatment does not hinder the formation of the fin-shaped portion. Further, according to the method of this embodiment, the silicon oxide films 112, 114, 116 and the SOG films 113, 1 are
The case where the formation of 15 is repeated twice has been described.
Since the number of fin-shaped portions is determined according to the number of layers of the SOG films 113 and 115, the purpose of increasing the memory cell capacity by increasing the electrode surface area can be achieved by repeating the process once or more. In addition, the SOG films 113 and 115 and the silicon oxide film 11
It is also clear that the same effect can be obtained even if the formation order of 2, 114 and 116 is reversed.

Next, a semiconductor device according to the second embodiment of the present invention will be described with reference to the sectional view of FIG. In FIG. 8, 101 is a semiconductor substrate and 102 is LO.
COS oxide film, 103 is a gate oxide film, 104 is a gate electrode, 105 is a sidewall, 106 is an n-type diffusion layer,
107 is a silicon nitride film, 119 is a lower polycrystalline silicon electrode, 120 is a capacitive insulating film, and 121 is an upper polycrystalline silicon electrode.

The lower polycrystalline silicon electrode 119 is a tubular body having a fin-shaped portion and the upper portion of the lower electrode is open, so that the electrode surface is completely used. Although it requires patterning with a photoresist film,
When the number of fin-shaped portions is the same as in the embodiment of
The surface area of lower polycrystalline silicon electrode 108 is more than doubled. Therefore, the memory cell capacitance is further increased without increasing the capacitor allowable area of the memory cell.

Next, the manufacturing method of this embodiment will be described in detail with reference to the drawings. 9 to 14 are cross-sectional views in order of the steps of this method. Here, only the memory cell forming step is shown for simplification.

First, a LOCOS oxide film 102, a gate oxide film 103, a gate electrode 104, a sidewall 105, and an n-type diffusion layer (source diffusion layer, drain diffusion layer) 106 are formed on a semiconductor substrate 101 by a known method. After that, the silicon nitride film 107 is formed by the CVD method. Then, the silicon oxide film 112, SO
The G film 113, the silicon oxide film 114, the SOG film 115, and the silicon oxide film 116 are alternately formed (FIG. 9).

Next, using the photoresist film 117 as a mask, a contact hole 118 is formed by dry etching on the n-type diffusion layer 106 on the surface of the semiconductor substrate 101 (FIG. 10).

At this time, the contact hole is etched while forming a reaction product on the side wall of the contact hole in order to obtain anisotropy. However, in the portions of the SOG films 113 and 115 which are hygroscopic films sandwiched between the silicon oxide films 112, 114 and 116 which are water resistant films, moisture is released at the same time as the etching, so the SOG films 113, 115 1
No reaction product is formed in part 15. Therefore,
When over-etching is performed in this state, the portions of the SOG films 113 and 115 which do not have reaction products are removed as shown in FIG.
As shown in FIG. This allows
An annular recess is formed on the inner wall surface of the contact hole 118. Next, while introducing impurities by the CVD method, the polycrystalline silicon film 122 is formed with a film thickness of 95% or less of the radius of the contact hole 118. In the figure, 1 / radius
The thickness is shown as 2. As a result, the contact hole 11
The upper part of 8 is not blocked by the polycrystalline silicon film 122. When the film thickness of the polycrystalline silicon film 122 is 95% or more and less than 100% of the radius of the contact hole 118, the upper portion of the contact hole 118 is opened after the polycrystalline silicon film 122 is formed, but the capacitive insulating film or the upper portion of the contact hole 118 is opened. The electrodes cannot be formed. Therefore, the thickness of the polycrystalline silicon film 122 is 95 times the radius of the contact hole 118.
Must be less than or equal to%. Next, the photoresist film 123
Is used as a mask to etch the polycrystalline silicon film 122 to pattern the lower polycrystalline silicon electrode (FIG. 12).

Then, a silicon oxide film 1 is formed by using a hydrofluoric acid solution.
12, 114, 116 and SOG films 113, 115
To remove. At this time, the gate electrode portion is the silicon nitride film 10
The lower polycrystalline silicon electrode 119 is formed without being etched at the time of etching because it is protected by 7 (FIG. 13). Then, the lower polycrystalline silicon electrode 11
9, a capacitor insulating film 120 made of, for example, a silicon nitride film and a silicon oxide film is formed, a polycrystalline silicon film is formed on the capacitor insulating film 120 by introducing an impurity by a CVD method, and the photoresist film is used as a mask for etching. Then, the upper polycrystalline silicon electrode 121 is formed. As described above,
A memory cell is formed.

In the manufacturing method of this embodiment, since the etching of the SOG film at the time of contact hole etching is utilized, the size of the fin-shaped portion can be controlled by the overetching amount of the contact hole, which leads to miniaturization. Is easy to handle. Further, as compared with the first embodiment, since the upper portion of the lower polycrystalline silicon electrode is opened, the electrode surface can be effectively utilized.

Further, in the manufacturing method of this embodiment, the heat treatment after the formation of the SOG film, which is usually performed, is not necessary. This is because the amount of water released increases and the fin-shaped portions are more easily formed. However, since the SOG film has a strong hygroscopic property, the heat treatment does not hinder the formation of the fin-shaped portion.

Furthermore, in the method of this embodiment, the formation of the silicon oxide film and the SOG film was repeated twice, but since the number of fin-shaped portions is determined according to the number of layers of the SOG film, the fin-shaped portions are repeated once or more. By doing so, the purpose of increasing the memory cell capacity by increasing the electrode surface area can be achieved. Also,
It is also clear that the same effect can be obtained even when the order of forming the SOG film and the silicon oxide film is reversed.

[0038]

According to the present invention, by stacking the SOG film and the silicon oxide film at least once before forming the contact hole,
A tubular storage electrode having a fin-shaped portion can be formed when the contact hole is formed. Therefore, even if miniaturization progresses,
An excellent semiconductor device capable of easily increasing the memory cell capacity without increasing the capacitor allowable area and a method for manufacturing the same.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a process sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 4 is a process sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 5 is a process sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 6 is a process sectional view of a method for manufacturing a semiconductor device, which is a first embodiment of the present invention.

FIG. 7 is a process sectional view of a method for manufacturing a semiconductor device, which is a first embodiment of the present invention.

FIG. 8 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 9 is a process sectional view of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a process sectional view of a method for manufacturing a semiconductor device, which is a second embodiment of the present invention.

FIG. 11 is a process sectional view of a method for manufacturing a semiconductor device, which is a second embodiment of the present invention.

FIG. 12 is a process sectional view of a method for manufacturing a semiconductor device, which is a second embodiment of the present invention.

FIG. 13 is a process sectional view of a method for manufacturing a semiconductor device, which is a second embodiment of the present invention.

FIG. 14 is a process sectional view of a method for manufacturing a semiconductor device, which is a second embodiment of the present invention.

FIG. 15 is a sectional view of a conventional semiconductor device.

FIG. 16 is a process sectional view of a conventional method for manufacturing a semiconductor device.

FIG. 17 is a process sectional view of a conventional method for manufacturing a semiconductor device.

FIG. 18 is a process cross-sectional view of a conventional method for manufacturing a semiconductor device.

FIG. 19 is a process sectional view of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 101 semiconductor substrate 102 LOCOS oxide film 103 gate oxide film 104 gate electrode 105 sidewall 106 n-type diffusion layer 107 silicon nitride film 108 lower polycrystalline silicon electrode 109 capacitor insulating film 110 upper polycrystalline silicon electrode 112 silicon oxide film 113 SOG film 114 Silicon oxide film 115 SOG film 116 Silicon oxide film 117 Photoresist film 118 Contact hole 119 Lower polycrystalline silicon film 120 Capacitive insulating film 121 Upper polycrystalline silicon electrode 122 Polycrystalline silicon film

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/822

Claims (7)

[Claims] 1. A first conductive film provided on a semiconductor substrate, an insulating film covering at least a part of the first conductive film, and a second conductive film formed so as to cover the insulating film. And a capacitor is formed, and the capacitor has a cylindrical shape having a fin-shaped portion. 2. A first conductive film provided on a semiconductor substrate, an insulating film covering at least a part of the first conductive film, and a second conductive film formed so as to cover the insulating film. The semiconductor device is characterized in that the capacitive element is formed by the method, the capacitive element has a cylindrical shape having a fin-shaped portion, and an opening is formed in an upper portion of the capacitive element. 3. A step of forming a silicon nitride film on a step of a semiconductor substrate, a step of forming a hygroscopic film on the silicon nitride film, and a step of forming a moisture resistant film on the hygroscopic film, Forming a contact hole in the silicon nitride film, the hygroscopic film and the moisture resistant film; and forming a first conductive film in the silicon nitride film, the hygroscopic film, the moisture resistant film and the contact hole. And the step of etching the entire surface of the conductive film to leave the first conductive film only inside the contact hole, removing the hygroscopic film and the moisture resistant film, and removing the first conductive film. A method of manufacturing a semiconductor device, comprising: a step of forming a capacitive insulating film on a surface; and a step of forming a second conductive film on the capacitive insulating film. 4. A step of forming a silicon nitride film on a step formed on a semiconductor substrate, a step of forming a hygroscopic film on the silicon nitride film, and a moisture resistant film on the hygroscopic film. And a step of forming contact holes in the hygroscopic film and the moisture resistant film, and a first step in the silicon nitride film, the hygroscopic film, the moisture resistant film and the contact hole.
Forming a conductive film, selectively etching the first conductive film, removing the hygroscopic film and the moisture resistant film, and forming a second conductive film. ,
Forming a capacitive insulating film on the second conductive film;
And a step of forming a third conductive film on the capacitive insulating film. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the thickness of the second conductive film is 95% or less of the radius of the contact hole. 6. The method of manufacturing a semiconductor device according to claim 3, wherein there are a plurality of laminated bodies of a hygroscopic film and a moisture resistant film. 7. The method of manufacturing a semiconductor device according to claim 3, wherein the hygroscopic film is an SOG film.