JPH08204141A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PURPOSE: To cut down the number of steps by a method wherein the polysilicon layer used as an etching mask in the case of forming the storage node contact hole of a condenser in a memory cell is not removed but to be reused as the storage node of a condenser. CONSTITUTION: A polysilicon layer 24 using the plane part 18b of a storage node comprising a storage node 19c in a memory cell region as an etching mask in the case of forming a contact hole 33a of the storage node is reused as a part of the storage node 19c. Next, since the etching mask 24 is formed in a memory cell region and simultaneously the polysilicon layer 40 formed in the peripheral circuit region is left as a part of a pad 41, the absolute stepped part in question between the memory cell and the peripheral circuit region can be relieved. Accordingly, the depth of the contact hole to be formed is made shallower thereby enabling the contact hole formation margin to be increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and a manufacturing method of a semiconductor device having a memory cell region composed of elements such as capacitors and transistors and peripheral circuits.

[0002]

2. Description of the Related Art FIG. 14 is a diagram showing a conventional semiconductor device disclosed in, for example, Japanese Patent Laid-Open No. 4-755.
OSFET (METAL OXIDE SEMICONDUCTOR FIELD EFFECT
TRANSISTOR) and one capacitor connected thereto, so-called one-transistor / one-capacitor type transistor. In FIG. 14, 1
Is a silicon substrate (semiconductor substrate), 2 is a LO formed by partially field-oxidizing one main surface of the semiconductor substrate 1.
COS (LOCAL OXIDATION OF SILICON) isolation region, 3 is a transfer gate transistor formed on one main surface of the semiconductor substrate 1, 4 is a word line serving as a gate electrode of the transfer gate transistor 2, and 5 is the gate electrode 4 and the semiconductor substrate. 1, a gate insulating layer formed between the main surfaces 1, a source / drain region 6 formed in the semiconductor substrate 1, 7 a bit line made of a conductive material formed in contact with the source / drain region 6, Reference numeral 8 is an interlayer insulating film laminated on the semiconductor substrate 1 so as to embed the word line 4 and the bit line 7, and 9 is formed so as to contact the source / drain regions 6 where the bit line 7 is not formed. Contact holes 10 are silicon nitride films formed on the interlayer insulating film 8 as an etching mask during the etching of the contact holes 9; Reference numeral 1 denotes a storage node formed by projecting in the vertical direction and the side surface and bottom surface of the contact hole 9 and the upper plane of the silicon nitride film 10, 12 is a dielectric film formed on the upper layer of the storage node 11, and 13 is the above. Cell plates laminated so as to surround the dielectric film 12, 14 is the cell plate 13
An insulating layer made of a silicon oxide film, which is laminated on the upper layer and has a flat upper surface, and a wiring layer 15 formed on the insulating layer. Further, reference numeral 16 in the figure is the storage node 1.
1, a capacitor including a dielectric film 12 and a cell plate 13 is shown.

FIG. 14 is a sectional view of a part of a semiconductor device. Next, since it is convenient for showing the problems of the conventional technique, the memory cell region and the memory cell region existing on the same substrate will be described. One sectional view showing peripheral circuits side by side (Fig. 15)
Indicates. In FIG. 15, the diagram on the left side is a DRAM (DYNAMI
C RANDUM ACCESS MEMORY) is a cross-sectional view showing a memory cell region, and the right side is a cross-sectional view of a peripheral circuit. 15, the same reference numerals as those shown in FIG. 15 indicate the same or corresponding portions. In addition, 4a, 4b, 4c, and 4d are word lines, 6a and 6b are low-concentration and high-concentration impurity layers, 9a and 9b are contact holes, 9c is a contact, and 17 is a capacitor formed inside the contact hole 9. A storage node contact electrically connecting the storage node and the source / drain region 6, 18b is a plane portion of the storage node of the cylindrical capacitor, 19b is a cylindrical portion of the storage node of the cylindrical capacitor, The storage node 19 is formed by the plane portion 18b and the tubular portion 19b.
c is configured. Further, in the figure showing the peripheral circuit, a portion indicated by reference numeral 20 is a barrier metal formed in close contact with the bit line 7, 21 is an insulating layer formed on the silicon oxide film 14, and 22 is a word. Line 4a,
4b, 4c, 4d is a wiring layer protective layer made of an insulating material and surrounding the periphery.

A method of forming a semiconductor device having the structure shown in FIG. 15 will be described with reference to FIGS. 16 to 33. First, as shown in FIG. 16, the LOCOS isolation region 2 is partially formed on the main surface of the semiconductor substrate 1 by field oxidation, and then the main substrate of the semiconductor substrate 1 in which the LOCOS isolation region 2 is not formed. A gate insulating layer 5 made of a silicon oxide film is formed in the surface region by oxidation or a CVD (CHEMICAL VAPOR DEPOSITION) technique. Next, the word line 4 made of polysilicon is laminated on the entire surface of the semiconductor substrate 1, and further, the insulating layer 22a serving as a protective film for the word line 4 is laminated.

Next, with respect to the semiconductor device in the manufacturing process shown in FIG. 16, an etching mask is formed by patterning a resist film on a region left as a word line by photolithography, and anisotropic etching is performed. The semiconductor substrate 1 is formed in a region other than a portion which is left as a word line after being performed.
Of the resist used as an etching mask at the time of anisotropic etching by forming the low-concentration impurity regions 6a forming the active regions of the source / drain regions by the ion implantation method until the surface of the substrate is exposed. The pattern is removed (FIG. 17).

Thereafter, a silicon oxide film is laminated on the entire surface of the semiconductor substrate 1 by a CVD technique and anisotropic etching is performed to form a sidewall 23 made of an insulating layer so as to be in close contact with at least the side surface of the word line 4. To do.
Next, as in the case shown in FIG. 17, ion implantation is performed to form the high-concentration impurity regions 6b forming the source / drain regions, and thereby the source / drain regions 6 of the LDD (LIGHT DOPED DRAIN) structure are formed. The formation is complete. After that, the structure of this device is connected to the upper part of the gate electrode (word line 4c) in the sectional view showing the peripheral circuit via the conductive material with the active region of the source / drain region 6 of the same device. Therefore, a resist pattern is formed in a region other than the upper portion of the word line 4c by photolithography, and etching is performed using the resist pattern as an etching mask.
Is removed so that the upper surface of the word line 4c is exposed (FIG. 18).

Further, a polysilicon layer to be the bit line 7 is laminated on the entire surface of the above semiconductor device by the CVD technique, and the bit line 7 is further formed in the peripheral circuit region.
In order to reduce the resistance, a conductive material (barrier metal) 20 having a low resistance such as silicide is laminated. Then bit line 7
Then, a resist pattern is formed on the region where the polysilicon layer is to be left, and anisotropic etching is performed to pattern and form the bit line 7 and the barrier metal 20 (FIG. 19). Next, the interlayer insulating layer 8 made of a silicon oxide film is laminated, and the wiring layer 15 formed above the interlayer insulating layer 8 and the source / source formed on one main surface of the semiconductor substrate 1 are stacked.
A polysilicon layer 24 is formed which will serve as an etching mask when forming the contact hole 9a necessary for electrical connection with the drain region 6 (FIG. 20).

Next, in the memory cell area, TEOS (TETRA ETYLE ORTHO SI SI) is formed on the polysilicon layer 24.
The LICATE) layer 25 is formed on a region other than the contact hole forming region, and the side wall 26 made of TEOS is formed on the side surface portion of the TEOS layer 25, similarly to the case where the side wall 23 is formed on the side surface of the word line 4. Then, the etching mask 27 for the contact hole of the storage node
Are formed (FIG. 21). Then, anisotropic etching is performed using the etching mask 27 to form contact holes 9a so as to contact the source / drain regions 6 formed on the one main surface of the semiconductor substrate 1 (FIG. 22). At this time, the TEOS layer 25 and the sidewalls 26 made of TEOS formed in the memory cell region are also etched away during the anisotropic etching, and the surface of the polysilicon layer 24 is exposed as the uppermost layer of the semiconductor device. It is in a state.

Next, the polysilicon layer 24 used as an etching mask when forming the contact hole 9a is
Semiconductor substrate 1 including memory cell area and peripheral circuit area
The resist can be completely removed by applying a resist, baking, etc. to the entire surface of, and then performing etching (FIG. 23). At this time, the contact hole 9
The resist 28 left inside a can be thereafter removed by ashing or can be completely removed by wet etching using sulfuric acid. In this manner, the inside of the contact hole 9a is made into a space, the surface of the region which is the source / drain region 6 of the semiconductor substrate 1 is exposed, and the resist film is formed so as to cover the peripheral circuit region. A polysilicon layer 18a is deposited on the region by a CVD technique or a sputtering method, and polysilicon is simultaneously embedded in the contact hole 9a to form a storage node contact 17. In addition, CMP (CMEMICAL MECHANICAL POLISHIN
G) method, or reflow, polysilicon layer 18
Flatten the surface of a (FIG. 24). Further, at the stage of moving to the next step, the resist film formed as the protective film in the peripheral circuit region is removed.

Then, a silicon oxide film 14 is laminated on the entire surface of the semiconductor substrate 1 (FIG. 25). Further, a silicon nitride film to be the antireflection film 29 is formed by a CVD technique, or a titanium nitride layer is laminated by a sputtering method, and a capacitor in a memory cell region is formed on the antireflection film 29 by photolithography. A resist pattern 30 for forming is formed (FIG. 26). Anisotropic etching is performed using the resist pattern 30 as an etching mask to form a groove 31 that comes into contact with the interlayer insulating film 8 (FIG. 27). When the groove 31 was formed, the resist pattern 30 that was an etching mask
Are completely removed and the next step is carried out.

Next, a polysilicon layer 19a is laminated on the entire surface of the semiconductor device by the CVD technique (FIG. 28). Further, in the next step, anisotropic etching is performed to completely remove the polysilicon layer 19a at the bottom of the groove 32 and expose the interlayer insulating layer 8. At this time, also on the upper surface of the memory cell region and the upper surface of the peripheral circuit region, the polysilicon layer 19a is completely removed, and the polysilicon layer 19a is left only on the sidewall of the groove 31, The cylindrical portion 19b of the storage node of the capacitor is formed (FIG. 29).

Next, a resist etch back method is used to remove the silicon oxide film 14 which is buried in the tubular portion of the tubular capacitor. First, a resist is applied to the entire surface of the semiconductor device so that the inside of the groove 31 is filled with the resist. Then, etching is performed under the condition that the silicon oxide film 14 is selectively etched to completely remove the silicon oxide film 14 embedded in the cylindrical portion of the cylindrical capacitor. At this time, a resist film is formed on the silicon oxide film 14 in the peripheral circuit region so that the silicon oxide film is not etched. Furthermore, this silicon oxide film 1
The resist film remaining on the outside of the cylinder of the cylindrical capacitor in the memory cell region for etching 4 is removed by wet etching using ashing or sulfuric acid as in the case described above (FIG. 30).

Next, the dielectric layer 12 is formed only in the memory cell region.
Is formed on the entire surface of the region, and then a layer made of a conductive material such as polysilicon to be the cell plate 13 of the capacitor is entirely formed on the dielectric layer 12 (FIG. 31).
Further, a silicon oxide film or the like is laminated on the entire surface of the memory cell region and the peripheral circuit region by the CVD method to form an insulating layer 2
1 is formed (FIG. 32). Next, in order to form the contact hole 9b so as to come into contact with the barrier metal 20 formed as a wiring pad in the peripheral circuit region, a resist pattern is formed by photolithography and anisotropic etching is performed. As a result, a semiconductor device having a structure as shown in FIG. 33 could be obtained.

[0014]

Since the conventional semiconductor device is configured as described above, the polysilicon layer 24, which is an etching mask for forming the contact hole 9a of the storage node 27 shown in FIG. 22, is formed. When removing the resist, a resist etch back process is generally used. In this resist etch back process,
Includes a step of applying a resist to the entire main surface of the semiconductor substrate, a step of baking a resist film, a step of etching the entire surface of the semiconductor substrate, and a step of removing the resist left in the contact holes by wet etching or ashing. It was a process with a large number of steps.

Further, in the conventional invention, as shown in FIG. 24, a step with the peripheral circuit area is generated at the stage where the polysilicon layer 18a to be the storage node of the capacitor is formed only in the memory cell area. Was not eliminated even in a post process, and remained as an absolute step even when the semiconductor device was completed. Here, when a step is generated in the peripheral circuit area and the memory cell area, when forming a metal wiring or the like, the wiring is formed on a surface having the step, which may cause a disconnection or a thin wiring, A product with high dimensional accuracy could not be obtained due to a cause such as overweight.

Further, as shown in FIG. 33, it is very difficult to form the contact hole 9b from the surface of the semiconductor substrate so as to be in contact with the barrier metal 20, because the aspect ratio is large, and the manufacturing margin is small. There was a problem.

The present invention has been made in order to solve the above problems, and it is possible to obtain a semiconductor device in which the manufacturing process can be simplified and an absolute level difference is hardly generated in the memory cell region and the peripheral circuit region. It is an object of the present invention to obtain a semiconductor device that can be manufactured and has a large manufacturing margin, and further to provide a manufacturing method suitable for this device.

[0018]

In a semiconductor device according to the present invention, a conductive layer forming a storage node serves as an etching mask for forming a contact hole in a memory cell region, and the manufacturing method of the present invention is a storage node. Is used as a storage node without removing the polysilicon layer used as the etching mask when forming the storage node contact hole.

Further, the semiconductor device of the present invention is electrically conductive so as to come into contact with the bit line formed in contact with the source / drain regions formed in the peripheral circuit region and the barrier metal formed in close contact with the bit line. A pad is formed of a material, and a polysilicon portion is formed of a conductive material in contact with a lower portion of the pad so as to be in contact with an upper flat portion of the pad. Further, the pad is formed to have a height higher than that of the conventional pad, and the polysilicon portion is formed simultaneously with the formation of the polysilicon layer used as the etching mask for forming the storage node contact hole in the memory cell region.

Further, in the semiconductor device of the present invention, an etching mask made of a conductive layer (polysilicon) used when forming the storage node contact holes in the memory cell region is formed, and at the same time, aluminum is formed on the source / drain regions in the peripheral circuit region. A conductive material to be a pad for wiring or the like is formed.

[0021]

The semiconductor device according to the present invention can be used as the storage node of the capacitor without removing the polysilicon layer used as the etching mask when forming the storage node contact hole of the capacitor formed in the memory cell region. The number of processes can be reduced.

In the semiconductor device according to the present invention, the polysilicon layer, which is an etching mask for forming the storage node contact hole formed in the memory cell region, is simultaneously formed with the polysilicon layer also in the peripheral circuit region. Can form a pad with height,
It is possible to reduce the aspect ratio of the contact hole formed in the peripheral circuit region. Further, the polysilicon pad becomes higher than the conventional one by the thickness of the polysilicon layer, and the absolute step difference between the memory cell region and the peripheral circuit region can be reduced.

[0023]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to FIGS.
Will be explained. In FIG. 1, reference numeral 32 denotes a storage node contact which is formed in the memory cell region and is buried inside the contact hole 33, and 34 is formed in close contact with a flat surface portion of a pad made of polysilicon formed in the peripheral circuit region. The polysilicon portion 35 is formed at least above the polysilicon portion 34, and the flat surface portion of the pad 41 made of polysilicon is formed so as to contact the barrier metal. 36 is the flat surface of the pad 41 made of polysilicon. The contact portion (vertical portion) of the pad 41 made of polysilicon formed so as to connect the portion 35 and the barrier metal 20, 37 is a contact hole formed on the pad 41, and 38 is the inside of the contact hole 37. Wiring 39 and source / drain regions 6 made of aluminum or the like buried in It is a contact for electrically connecting.

Next, an embodiment of the method of manufacturing the semiconductor device according to the present invention shown in FIG. 1 will be described. First, processing is performed according to the order of steps shown in FIGS.
5 is patterned, and sidewalls 26 are formed on the cross section of the TEOS layer 25 using the same material. Next, FIG.
As shown in FIG. 3, in the peripheral circuit region as well, similarly to the memory cell region, the TEOS layer 25 is formed in the uppermost layer, and the TEOS layer 25 is patterned, and the sidewall 26 is formed in the cross section to form the contact hole etching mask 27. To do.

Next, anisotropic etching is performed using the etching mask 27 to form a contact hole 33a in the memory cell region so as to be in contact with the source / drain region 6 formed in the semiconductor substrate 1. In the peripheral circuit region, the contact hole 33b is formed so as to be in contact with the source / drain region 6 or the conductive material (barrier metal) 20. After that, the TEOS layer 25 and the side wall 26 made of TEOS formed as the etching mask 27 are removed, and then the entire surface of the semiconductor device and the inside of the contact holes 33a and 33b are formed by using the CVD technique. A conductive material 40 such as polysilicon is laminated so as to be embedded (FIG. 3). As a result, in the memory cell area and the peripheral circuit area, the source / source
The contacts 32 and 36 electrically connected to the drain region 6 are formed.

Next, the entire memory cell region is etched back to remove a part of the conductive material 40 formed of polysilicon or the like, so that the polysilicon layer 24 is exposed (FIG. 4). After that, a photolithography process is performed to form a pad 41 formed of polysilicon or the like for electrically connecting the wiring layer such as aluminum formed in the upper layer of the peripheral circuit region to the source / drain region 6 or the barrier metal 20. A resist film is formed on the memory cell region and in regions other than the regions where the polysilicon layers 24 and 35 are desired to be left as the pads 41, and anisotropic etching is performed to pattern the polysilicon layers 24 and 40, and the pads A flat surface portion 35 that constitutes 41 and a polysilicon portion 34 are formed immediately below the flat surface portion 35. After forming the above pattern, the resist mask formed as an etching mask is removed (FIG. 5).

After that, the conventional technique shown in FIGS.
In the memory cell region, the cylindrical conductive material 19b is added to the storage node 19 by performing the same process as the process shown in FIG.
A capacitor having c is formed, and in the peripheral circuit area,
An insulating layer 14 made of a silicon oxide film is formed on the uppermost layer (FIG. 6). Next, the insulating layer 21 is laminated on the entire surface of the memory cell region and the peripheral circuit region (FIG. 7), and then on the insulating layer 21 in a region other than the upper portion of the polysilicon pad formed in the peripheral circuit region. By forming a resist pattern by photolithography and performing anisotropic etching, a semiconductor device having the structure shown in FIG. 1 can be formed.

As described above, in the semiconductor device shown in this embodiment, the plane portion 18b of the storage node forming the storage node 19c formed in the memory cell region is
Polysilicon layer 2 used as etching mask when forming contact hole 33a of storage node
4 is used as a part of the storage node 19c without being removed. In this way, by reusing the polysilicon layer 24 that was the etching mask as the storage node 19c, the number of manufacturing steps can be simplified. Further, since the etching layer 24 of the contact hole 33a of the storage node is formed in the memory cell region, and at the same time, the polysilicon layer 40 formed in the peripheral circuit region is left as a part of the pad 41, the problem arises in the memory cell. The absolute level difference between the region and the peripheral circuit region is relaxed, and even when the wiring layer is formed over the memory cell region and the peripheral circuit region, it is possible to suppress disconnection and deterioration of the pattern dimensional accuracy.

Further, conventionally, the source / source of the peripheral circuit area is
In order to electrically connect the drain region 6 and the upper layer wiring (aluminum wiring) 39, etc., the contact hole was formed by one-time contact hole etching. Therefore, the aspect ratio of the formed contact hole is large. However, there is almost no manufacturing margin, and there is difficulty in burying a conductive material in the contact hole. However, as shown in this embodiment, since the pad 41 made of a conductive material such as polysilicon is formed, the depth of the contact hole to be formed becomes small,
The manufacturing margin for forming the contact hole can be expanded. As a result, the cylindrical portion of the electrode formed in the memory cell region can be formed higher, and a capacitor having a large capacitance can be obtained. Further, in this embodiment, the capacitor formed in the memory cell region has the cylindrical electrode, but the cylindrical portion 19b of the storage node is formed.
A semiconductor device having substantially the same effect can be obtained even if it has a flat plate electrode having no.

Example 2. Next, another embodiment will be described with reference to FIGS. 8 to 10 and the description of the prior art and the first embodiment. FIG. 8 shows a cross-sectional view of the semiconductor device of this embodiment. The reference numerals in the drawings are the same as those used in the conventional technique and the first embodiment, and the same reference numerals indicate the same or corresponding portions. In addition, the reference numeral 42a denotes a memory cell region (the cross section shown on the left side of each drawing). (Corresponding to the figure) of the storage node, and 42b indicates the plane of the storage node. In addition, 43 of the peripheral circuit area (corresponding to the sectional view shown on the right side of each drawing)
Reference numeral a denotes a contact portion of the pad 43c made of a conductive material such as polysilicon, and reference numeral 43b denotes a flat portion of the pad 43c.

The difference between this embodiment and the above-described first embodiment lies in the structure and the forming method thereof. Structurally, the pad 43c formed in the peripheral circuit region (see the symbol 4 in the first embodiment).
1), but in the first embodiment, the plane portion has a two-layer structure (symbols 34 and 35), in the present embodiment,
The flat part is that it is composed of one layer (symbol 43a). Further, the difference in the method of manufacturing the semiconductor device is that the etching mask 24 made of polysilicon is used as the etching mask when forming the contact hole 33a of the storage node in the memory cell region in the first embodiment. In order to form the contact holes 33a and 33b as shown in FIG. 9 in this embodiment,
The point is that the resist film is used as an etching mask.

Next, an embodiment of a method of manufacturing the semiconductor device having the structure shown in FIG. 8 will be described. First, as in the first embodiment, processing is performed according to the order of steps shown in FIGS. 16 to 19 of the conventional technique, and the transfer gate transistor 3, the bit line 7, the barrier metal 20, the wiring layer protection layer 2 are formed on the semiconductor substrate 1.
2 etc. are formed. Next, the interlayer insulating film 8 is formed on the entire surface of the semiconductor substrate 1 (including at least the memory cell region and the peripheral circuit region).
Are stacked by a method such as a CVD technique or a sputtering method, and then contact holes 33a and 33b are formed so as to contact the source / drain regions 6 formed in the semiconductor substrate 1 or the barrier metal 20 on the bit line 7. Therefore, a resist pattern serving as an etching mask at the time of contact hole etching is formed by photolithography. Next, anisotropic etching is performed to form contact holes 33a in the memory cell region and the peripheral circuit region, respectively.
33b is formed (FIG. 9).

Next, a conductive material such as polysilicon is laminated on the entire surface of the semiconductor substrate 1 by the CVD technique, and the flat portion 42a of the storage node is formed on the interlayer insulating film 8 in the memory cell region.
And the contact holes 33a and 33b opened in the previous step at the same time by forming a conductive layer to be the flat portion 43a of the pad on the interlayer insulating layer 8 in the peripheral circuit region.
A conductive material is also embedded in the inside to form the contact portion 42b of the storage node and the contact portion 43b of the pad.
Then, in the peripheral circuit region, the conductive layer is subjected to photoengraving and etching to form a flat portion 43b of the pad, and a pad 43c as shown in FIG. 10 is formed.

A semiconductor device corresponding to the structure shown in FIG. 5 of the first embodiment is obtained by the above processing, and thereafter, the same processing as the processing described with reference to FIGS. 6 and 7 is performed. To form the capacitor 16 and the insulating layer 14
(Formed only in the peripheral circuit region), 21 are stacked, and then
The peripheral circuit region is subjected to photoengraving and anisotropic etching to form a contact hole 37 so as to abut the pad 43a made of a conductive material such as polysilicon, and the inside of the contact hole 37 is buried. The conductive material is laminated on the surface of the contact 38 by the CVD technique,
After forming the above, the semiconductor device having the structure shown in FIG. 8 can be formed by forming the aluminum wiring layer 39 and the like on the contact hole 38.

As described above, in the semiconductor device shown in this embodiment, when the contact holes 33a and 33b are formed, it is not necessary to perform the resist etching back process as in the conventional case, so that the same effect can be obtained with a small number of steps. It is possible to complete a semiconductor device that achieves Further, in the peripheral circuit region, the source / drain region 6
Since the pad 43c electrically connected to the contact hole is formed, the aspect ratio of the contact hole to be formed can be reduced, and the manufacturing margin of the contact 38 such as the aluminum wiring 39 and the contact hole 37 can be expanded. As a result, the cylindrical portion of the electrode formed in the memory cell region can be formed higher, and a capacitor having a large capacitance can be obtained. Further, in this embodiment, the capacitor formed in the memory cell region has the cylindrical electrode, but the cylindrical portion 19 of the storage node is used.
Even if a flat electrode having no b is provided, a semiconductor device having substantially the same effect can be obtained.

Example 3. An embodiment of the present invention will be described below with reference to FIGS. In FIG. 11, 4
Reference numeral 4a indicates a storage node contact formed in the memory cell region, and 45a and 45b indicate a pad 45d made of tungsten formed in the peripheral circuit region.
The flat portion and the contact portion that constitute the
Indicates a conductive layer which is a part of the storage node contact. Further, the other reference numerals, which are the same as those in the first and second embodiments and the prior art, indicate the same or corresponding portions. The difference between this embodiment and the second embodiment is that
In the second embodiment, the storage node contact and the pad made of polysilicon are made of tungsten.

Next, an embodiment of the method of manufacturing the semiconductor device according to the present invention shown in FIG. 11 will be described. First, Examples 1 and 2
16 to 19 of the prior art, processing is performed in the same manner as described above, and a trench far gate transistor 3, a bit line 7, and a barrier metal 2 are formed on the semiconductor substrate 1.
0, the wiring layer protection layer 22 and the like are formed. Next, as shown in FIG. 9 of the second embodiment, after laminating the interlayer insulating film 8, a resist pattern is formed by photolithography and etching is performed using this as a mask to form the contact holes 33a and 33b. Next, the contact holes 33a and 33b are buried in the entire surface of the semiconductor device formed as described above,
Further, the tungsten film 44 covering the interlayer insulating film 8 is formed.
b and 45c are laminated by sputtering. At this stage, a storage node contact 44a is formed in the contact hole 33a and a tungsten film 44b is formed on the interlayer insulating film 8 in the memory cell region. At the same time, in the peripheral circuit region, the contact portion 4 of the tungsten pad is formed in the contact hole 33b.
5b, and a tungsten film 45c having the same thickness as the tungsten film 44b in the memory cell region is formed on the interlayer insulating film 8 (FIG. 12).

After that, for the memory cell region, the entire surface is etched until the upper surface of the interlayer insulating film 8 is exposed under the condition that the selection ratio of tungsten is larger than that of the silicon oxide film forming the interlayer insulating film 8. Backing is performed, leaving only the storage node contact 44a and removing the other tungsten film 44b and the like. In addition, a resist pattern is formed by photolithography on a region other than a region where the pad 45d made of tungsten is to be formed, on the upper layer of the tungsten film 45c in the peripheral circuit region.
The entire surface of the memory cell region is etched back and etched at the same time to form a plane portion 45a of the tungsten pad 45d (FIG. 13).

Next, with respect to the memory cell region, a conductive layer 46, which is a part of the storage node of the capacitor, is further stacked on the upper layer by using polysilicon or the like. A semiconductor device corresponding to the structure shown in FIG. 5 of the first embodiment is obtained by performing the above-described processing, and then, as with the processing performed in the second embodiment, description is made with reference to FIGS. 6 and 7. By performing the same process as the process, the capacitor 16 is formed and the insulating layer 1
4 and 21 are laminated, and then the peripheral circuit region is subjected to photolithography and anisotropic etching treatment to form a contact hole so as to be in contact with the tungsten pad 45a, thereby forming the structure shown in FIG. A semiconductor device having the semiconductor device can be formed. Further, a contact hole 33c is opened on the tungsten pad in the peripheral circuit region, a conductive material is embedded in the contact hole 33c to form a contact 38, and then a wiring such as aluminum is formed on the contact 38. A semiconductor device as shown in FIG. 11 is obtained.

As described above, in the semiconductor device according to the present embodiment, when the contact holes 33a and 33b are formed, it is not necessary to carry out the treatment by the resist etch back process as in the conventional case. It is possible to complete a semiconductor device having an effect.
Further, in the peripheral circuit region, since the tungsten pad 45b electrically connected to the source / drain region 6 is formed, the aspect ratio of the contact hole to be formed can be reduced, and the manufacturing margin of the contact can be expanded. became. As a result, the cylindrical portion of the electrode formed in the memory cell region can be formed higher.
It is possible to obtain a capacitor having a large capacity. In addition, the storage node contact 44a and the pad 4
Since the material of 5d is low resistance tungsten, there are advantages such as improved conductivity. Further, in the present embodiment, the capacitor 16 formed in the memory cell region has the cylindrical electrode, but even if the capacitor 16 has the flat plate electrode without the cylindrical portion 19b of the storage node, substantially the same effect is obtained. A semiconductor device is obtained.

[0041]

As described above, according to the present invention, the storage node of the capacitor forming the memory cell is formed by using the etching mask used when the contact hole of the storage node is formed by etching. The process can be simplified and the device can be made inexpensive. Further, since the polysilicon pad is formed in the peripheral circuit region, the aspect ratio of the contact hole formed above the polysilicon pad can be reduced and the manufacturing margin is increased. In the peripheral circuit area,
Since the conductive layer formed at the same time as the etching mask for opening the contact hole of the storage node is left as a part of the polysilicon pad, it occurs in the memory cell region and the peripheral circuit region formed in the same semiconductor substrate. In addition, the absolute step difference is mitigated, and there is an effect that the deterioration of the dimensional accuracy caused by the step difference can be suppressed.

Further, according to the present invention, the polysilicon pad in the peripheral circuit region is formed simultaneously with the formation of the storage node contact of the capacitor forming the memory cell, so that the contact hole can be increased without increasing the number of steps. The aspect ratio can be reduced and a semiconductor device with a large manufacturing margin can be obtained.

Further, according to the present invention, the tungsten pad in the peripheral circuit region is formed simultaneously with the formation of the storage node contact of the capacitor forming the memory cell, so that the contact hole can be formed without increasing the number of steps. The aspect ratio can be reduced, and a semiconductor device with a large manufacturing margin can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 9 is a sectional view of a semiconductor device manufacturing process in a second embodiment of the present invention.

FIG. 10 is a sectional view of a semiconductor device manufacturing process according to a second embodiment of the present invention.

FIG. 11 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 12 is a sectional view showing a step of manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 13 is a sectional view of a semiconductor device in a manufacturing process according to a third embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a conventional semiconductor device.

FIG. 15 is a cross-sectional view showing a conventional semiconductor device.

FIG. 16 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 17 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 18 is a cross-sectional view of manufacturing steps of a conventional semiconductor device.

FIG. 19 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 20 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 21 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 22 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 23 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 24 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 25 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 26 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 27 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 28 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 29 is a sectional view of the manufacturing process of the conventional semiconductor device.

FIG. 30 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 31 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 32 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 33 is a sectional view of the manufacturing process of the conventional semiconductor device.

[Explanation of symbols]

1. Semiconductor substrate, 2. LOCOS isolation region, 3. Transfer gate transistors 4, 4, 4a, 4b, 4c,
4d. Word line (gate electrode), 5. Gate insulation layer,
6. Source / drain regions, 6a. Low concentration impurity region,
6b. High concentration impurity region, 7. Bit line, 8. Interlayer insulating film, 9, 9a, 9b. Contact hole, 10. Silicon nitride film, 11. Storage node, 12. Dielectric film,
13. Cell plate, 14. Insulating layer, 15. Wiring layer, 1
6. Capacitor, 17. Storage node contact,
18a. A polysilicon layer, 18b. Storage node (planar portion), 19a. A polysilicon layer, 19b. Storage node (cylindrical portion), 19c. Storage node, 2
0. Conductive layer (barrier metal), 21. Insulating layer, 22. Wiring layer protection film, 22a. Insulating layer, 23. Sidewalls,
24. A polysilicon layer, 25. TEOS layer, 26. Sidewall, 27. Etching mask, 28. Resist, 29. Antireflection film, 30. Resist pattern, 3
1. Groove, 32. Storage node contact, 33a,
33b, 33c. Contact hole, 34. Polysilicon part, 35. Pad (flat surface portion), 36. Pad (contact portion), 37. Contact hole, 38. Contacts, 39. Wiring layer, 40. Conductive material, 41. Pad, 4
2a. Storage node (planar portion), 42b. Storage node (contact portion), 43a. Pad (planar portion), 43b. Pad (contact portion), 43c. Pad, 44a. Storage node contact, 44b. Tungsten film, 45a. Tungsten pad (flat surface portion), 45b. Tungsten pad (contact part),
45c. Tungsten film, 45d. Pad, 46. Conductive layer

Claims (10)

[Claims] 1. A semiconductor substrate, first and second source / drain regions formed on one main surface of the semiconductor substrate, word lines formed on the semiconductor substrate via an insulating layer, and the first line. Bit line formed on the semiconductor substrate so as to be in contact with the source / drain region, the bit line, the word line, an interlayer insulating film formed on the first and second source / drain regions, and in the interlayer insulating film. A contact formed in contact with the second source / drain region, a first conductive layer formed in contact with the upper portion of the contact and serving as a contact hole etching mask when the contact is formed, A semiconductor device comprising a dielectric film formed so as to cover the surface of a conductive layer, and at least a second conductive layer formed on the dielectric film. 2. A third and fourth source / drain regions formed on one main surface of the semiconductor substrate, and a third conductive layer formed on the semiconductor substrate so as to be in contact with the third source / drain regions. Layer, a barrier metal formed in close contact with the third conductive layer, the third and fourth source / drain regions, a third conductive layer, another interlayer insulating film formed on the barrier metal, the second On the interlayer insulating layer of the above, the third,
A fourth conductive layer formed in a region including above the fourth source / drain region, a fifth conductive layer formed on the fourth conductive layer, the fifth conductive layer, and a third conductive layer A second contact formed in the second interlayer insulating film so as to be in contact with the conductive layer or the barrier metal, and the fourth conductive layer is formed in the same process as the first conductive layer. The semiconductor device according to claim 1, wherein: 3. A semiconductor substrate, first and second source / drain regions formed on one main surface of the semiconductor substrate, word lines formed on the semiconductor substrate via an insulating layer, and the first source. / Bit line formed on the semiconductor substrate so as to be in contact with the / drain region, the bit line, the word line, the first interlayer insulating film formed on the first and second source / drain regions, the first line First contact formed in contact with the second source / drain region and buried in the interlayer insulating film of, and formed simultaneously with the formation of the first contact, and in contact with the upper portion of the first contact in the horizontal direction. A memory cell region having a first conductive layer having a width, a dielectric film formed to cover the surface of the first conductive layer, a second conductive layer formed on the dielectric film, Within the semiconductor substrate or above semiconductor On a substrate, the third,
A fourth source / drain region and a second interlayer insulating film are formed similarly to each element in the memory cell region, and further formed on the semiconductor substrate so as to be in contact with the third source / drain region. A third conductive layer, a barrier metal formed in close contact with the third conductive layer, and formed simultaneously with the formation of the first contact that is a constituent element of the memory cell region, A second contact formed by being embedded in the second interlayer insulating film so as to be in contact with either one, and a first contact formed in an upper layer of the second interlayer insulating film so as to be in contact with the second contact. A semiconductor device comprising a peripheral circuit region having four conductive layers. 4. The semiconductor device according to claim 3, wherein a part or all of the first and second contacts and the fourth conductive layer are made of a metal such as tungsten. 5. The cylindrical conductive layer extending in the vertical direction in the vicinity of the end portion of the first conductive layer formed in the memory cell region, according to any one of claims 1 to 4. Semiconductor device. 6. A first step of forming first and second source / drain regions on one main surface of a semiconductor substrate, and a second step of forming a word line on the semiconductor substrate via an insulating layer. A third step of forming a bit line in contact with the first source / drain region, a fourth step of forming an interlayer insulating film on the word line, the bit line, and the first and second source / drain regions Step, a fifth step of forming a conductive film on the interlayer insulating film, a sixth step of patterning the conductive film to form a contact hole etching mask,
A seventh step of forming a contact hole in contact with the second source / drain region by anisotropically etching using the contact hole etching mask, an eighth step of forming a contact in contact with the inside of the contact hole A ninth step of forming a first conductive layer in contact with the upper portion of the contact and having a horizontal spread, a tenth step of forming a dielectric film so as to cover at least the surface of the first conductive layer Including the eleventh step of forming a second conductive layer in contact with the dielectric film, the first conductive layer being formed by using a part of the contact hole etching mask. Manufacturing method of semiconductor device. 7. A twelfth step of forming third and fourth source / drain regions on one main surface of the semiconductor substrate, wherein a third step is provided on the semiconductor substrate in contact with the third source / drain regions. Thirteenth step of forming a conductive layer, fourteenth step of forming a barrier metal in close contact with the third conductive layer, third,
Fifteenth step of forming a fourth conductive layer on the interlayer insulating film including the fourth source / drain regions, and sixteenth step of forming a fifth conductive layer on the fourth conductive layer. The fifth conductive layer and the third conductive layer or a barrier metal so that the second contact is embedded in the interlayer insulating film so as to contact the fourth conductive layer. 7. The method of manufacturing a semiconductor device according to claim 6, wherein is formed in the same process as the first conductive layer. 8. A first step of forming first and second source / drain regions on one main surface of a semiconductor substrate, a second step of forming a word line on the semiconductor substrate via an insulating layer,
A third step of forming a bit line on the semiconductor substrate so as to contact the first source / drain region, the bit line, the word line, and the first interlayer insulation on the first and second source / drain regions. A fourth step of forming a film, a fifth step of embedding in the first interlayer insulating film and forming a first contact in contact with the second source / drain region, an upper portion of the first contact And a sixth step of forming a first conductive layer having a horizontal spread centering on the contact point with the first contact, the dielectric film covering at least the surface layer of the first conductive layer. Including a seventh step of forming a second conductive layer on the dielectric film, a memory cell region is formed by the first to eighth steps, and a second step is formed on the semiconductor substrate. Forming third and fourth source / drain regions Ninth step, tenth step of forming a third conductive layer on the semiconductor substrate so as to contact the third source / drain regions, forming a barrier metal formed in close contact with the third conductive layer Eleventh step of forming, second and fourth source / drain regions, third conductive layer, twelfth step of forming second interlayer insulating film on barrier metal, constituent elements of the memory cell region Simultaneously with the formation of the first conductive layer which is, a second contact embedded in the second interlayer insulating film so as to be in contact with either the third conductive layer or the barrier metal is formed. And a fourteenth step of forming a fourth conductive layer on the surface of the second interlayer insulating layer so as to contact the second contact, and the peripheral circuit region is formed by the ninth to fourteenth steps. Of a semiconductor device characterized by forming Law. 9. The method of manufacturing a semiconductor device according to claim 8, wherein a part or all of the first and second contacts and the fourth conductive layer are made of a metal such as tungsten. 10. The method according to claim 6, further comprising the step of forming a cylindrical conductive layer in the memory cell region, in which the vicinity of the end of the first conductive layer extends vertically. A method for manufacturing a semiconductor device as described above.