KR970003978A - Method of forming capacitor of DRAM cell - Google Patents

Method of forming capacitor of DRAM cell Download PDF

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Publication number
KR970003978A
KR970003978A KR1019950017223A KR19950017223A KR970003978A KR 970003978 A KR970003978 A KR 970003978A KR 1019950017223 A KR1019950017223 A KR 1019950017223A KR 19950017223 A KR19950017223 A KR 19950017223A KR 970003978 A KR970003978 A KR 970003978A
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KR
South Korea
Prior art keywords
forming
polysilicon layer
photoresist pattern
etching
insulating film
Prior art date
Application number
KR1019950017223A
Other languages
Korean (ko)
Inventor
안성환
장환수
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950017223A priority Critical patent/KR970003978A/en
Publication of KR970003978A publication Critical patent/KR970003978A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 DRAM 셀의 캐패시터의 형성 방법을 개시한다. 활성영역이 형성되어 있는 반도체 기판상의 절연막상에 제1폴리실리콘층을 형성한 후, 상기 제1폴리실리콘층 표면에 감광막을 도포하여 소정의 감광막 패턴을 형성하는 단계; 상기의 감광막 패턴에 따라 제1폴리실리콘층을 선택적으로 식각하여 상기 절연막의 일정 부분을 노출시키는 단계; 상기 절연막의 노출 부분을 상기의 감광막 패턴에 따라 습식으로 동방성 식각하여 상기 절연막에 홀을 형성하는 단계; 상기 감광막 패턴에 따라 상기 반도체 기판의 활성영역이 노출되도록 건식 비등방성 식각하여 상기 절연막에 콘택홀을 형성하는 단계; 상기 감광막 패턴을 제거하는 단계; 상기 제1폴리실리콘층의 상부면, 측벽부 및 상기 콘택홀과 마주하여 노출되어 있는 하부 부분과 상기 콘택홀의 내부 전면에 제2폴리실리콘층을 형성하는 단계; 상기 제2폴리실리콘층의 전면에 유전체를 중착하는 단계 및 상기 유전체의 전면에 상부 전극을 형성하는 단계를 포함한다. 개시된 방법에 의하면, 더욱 많은 용량을 지니는 캐패시터를 비교적 단순한 공정으로 형성할 수 있다.The present invention discloses a method of forming a capacitor of a DRAM cell. Forming a first polysilicon layer on an insulating film on a semiconductor substrate on which an active region is formed, and then forming a predetermined photoresist pattern by coating a photoresist on the surface of the first polysilicon layer; Selectively etching the first polysilicon layer according to the photoresist pattern to expose a portion of the insulating layer; Forming a hole in the insulating film by wet isotropically etching the exposed portion of the insulating film according to the photoresist pattern; Forming a contact hole in the insulating layer by dry anisotropic etching to expose the active region of the semiconductor substrate according to the photoresist pattern; Removing the photoresist pattern; Forming a second polysilicon layer on an upper surface, a sidewall portion of the first polysilicon layer, a lower portion exposed to the contact hole, and an inner front surface of the contact hole; Depositing a dielectric on the front surface of the second polysilicon layer and forming an upper electrode on the front surface of the dielectric. According to the disclosed method, a capacitor with more capacity can be formed in a relatively simple process.

Description

디램(DRAM) 셀의 캐패시터의 형성 방법Method of forming capacitor of DRAM cell

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도(마)는 본 발명의 DRAM 셀의 캐패시터의 형성방법을 설명하기 위한 각 공정에서의 반도체 소자의 요부 단면도.FIG. 2E is a cross-sectional view of the principal parts of the semiconductor device in each step for explaining the method for forming the capacitor of the DRAM cell of the present invention. FIG.

Claims (4)

(가) 활성영역이 형성되어 있는 반도체 기판상의 절연막상에 제1폴리실리콘층을 형성한 후, 상기 제1폴리실리콘층 표면에 감광막을 도포하여 소정의 감광막 패턴을 형성하는 단계; (나) 상기의 감광막 패턴에 따라 제1폴리실리콘층을 선택적으로 식각하여 상기 절연막의 일정 부분을 노출시키는 단계; (다) 상기 절연막의 노출 부분을 상기의 감광막 패턴에 따라 반도체 기판상의 활성영역이 노출되지 않을 정도로 소정의 두께만큼 습식으로 등방성 식각하여 상기 절연막에 홀을 형성하는 단계; (라) 상기 감광막 패턴에 따라, 상기 반도체 기판의 활성영역이 노출되도록 건식 비등방성 식각하여 상기 절연막에 콘택홀을 형성하는 단계; (마) 상기 감광막 패턴을 제거하는 단계; (바) 상기 제1폴리실리콘층의 상부면, 측벽부 및 상기 콘택홀과 마주하여 노출되어 있는 제1폴리실리콘층의 하부 부분과 상기 콘택홀의 내부 전면에 제2폴리실리콘층을 형성하는 단계; (사) 상기 제2폴리실리콘층의 전면에 유전체를 증착하는 단계 및 (아) 상기 유전체의 전면에 상부 전극을 형성하는 단계를 포함하는 것을 특징으로 하는 DRAM 셀의 캐패시터의 형성 방법.(A) forming a first polysilicon layer on the insulating film on the semiconductor substrate on which the active region is formed, and then applying a photoresist on the surface of the first polysilicon layer to form a predetermined photoresist pattern; (B) selectively etching the first polysilicon layer according to the photosensitive film pattern to expose a portion of the insulating film; (C) forming a hole in the insulating film by wet isotropically etching the exposed portion of the insulating film by a predetermined thickness such that the active region on the semiconductor substrate is not exposed according to the photoresist pattern; (D) forming a contact hole in the insulating layer by dry anisotropic etching to expose the active region of the semiconductor substrate according to the photoresist pattern; (E) removing the photoresist pattern; (F) forming a second polysilicon layer on an upper surface of the first polysilicon layer, a sidewall portion, and a lower portion of the first polysilicon layer exposed to face the contact hole and an inner front surface of the contact hole; (G) depositing a dielectric on the entire surface of the second polysilicon layer, and (h) forming an upper electrode on the entire surface of the dielectric. 제1항에 있어서, 단계 (다)에서, 습식 등방성 식각을 위하여 HF+H2O 또는 NH4F+HF+H2O 식각 용액을 사용하는 것을 특징으로 하는 DRAM 셀의 캐패시터의 형성 방법.The method of claim 1, wherein in step (c), HF + H 2 O or NH 4 F + HF + H 2 O etching solution is used for wet isotropic etching. 제1항에 있어서, 단계 (다)에서, 등방성 식각 높이가 100~3500Å인 것을 특징으로 하는 DRAM 셀의 캐패시터의 형성 방법.The method of forming a capacitor of a DRAM cell according to claim 1, wherein in step (c), the isotropic etching height is 100 to 3500 mW. 제1항에 있어서, 단계 (라)에서, 건식 식각이 1torr 미만의 압력에서 실시되는 것을 특징으로 하는 DRAM 셀의 캐패시터의 형성 방법.The method of claim 1, wherein in step (d), dry etching is performed at a pressure of less than 1 torr. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950017223A 1995-06-23 1995-06-23 Method of forming capacitor of DRAM cell KR970003978A (en)

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KR1019950017223A KR970003978A (en) 1995-06-23 1995-06-23 Method of forming capacitor of DRAM cell

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KR1019950017223A KR970003978A (en) 1995-06-23 1995-06-23 Method of forming capacitor of DRAM cell

Publications (1)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100486197B1 (en) * 1997-06-30 2006-04-21 삼성전자주식회사 Capacitor bottom electrode formation method using halftone mask
KR100753049B1 (en) * 2005-11-28 2007-08-30 주식회사 하이닉스반도체 Method for forming storagenonode contact plug in semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100486197B1 (en) * 1997-06-30 2006-04-21 삼성전자주식회사 Capacitor bottom electrode formation method using halftone mask
KR100753049B1 (en) * 2005-11-28 2007-08-30 주식회사 하이닉스반도체 Method for forming storagenonode contact plug in semiconductor device

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