KR950019956A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR950019956A
KR950019956A KR1019930026882A KR930026882A KR950019956A KR 950019956 A KR950019956 A KR 950019956A KR 1019930026882 A KR1019930026882 A KR 1019930026882A KR 930026882 A KR930026882 A KR 930026882A KR 950019956 A KR950019956 A KR 950019956A
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KR
South Korea
Prior art keywords
conductive layer
layer
etching
insulating
contact hole
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KR1019930026882A
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Korean (ko)
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KR970007791B1 (en
Inventor
이호석
정재갑
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김주용
현대전자산업 주식회사
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Priority to KR93026882A priority Critical patent/KR970007791B1/en
Publication of KR950019956A publication Critical patent/KR950019956A/en
Application granted granted Critical
Publication of KR970007791B1 publication Critical patent/KR970007791B1/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 고집적 반도체소자의 캐패시터 제조방법에 관한 것으로, 디램셀의 캐패시터 용량을 증대시키기 위하여 도전층과 절연막을 콘택홀 상부에 적층시키되, 콘택홀에서 증착되는 도전층과 절연막의 두께가 얇은 특성을 이용하는 기술이다.The present invention relates to a method for manufacturing a capacitor of a highly integrated semiconductor device, in order to increase the capacitor capacity of the DRAM cell, a conductive layer and an insulating film are laminated on the contact hole, and the thickness of the conductive layer and the insulating film deposited in the contact hole is thin. It is technology to use.

Description

반도체소자의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도의 (A), (B), (C)는 콘택홀 상부에 형성되는 상부층의 스텝커버리지를 나타내기 위해 도시한 단면도.(A), (B), (C) of FIG. 1 are sectional drawing shown in order to show the step coverage of the upper layer formed in the upper part of a contact hole.

제2도의 (A)~(F)는 본 발명에 의해 캐패시터 저장전극을 제조하는 단계를 도시한 단면도.2 (A) to (F) are cross-sectional views showing steps of manufacturing a capacitor storage electrode according to the present invention.

Claims (4)

디램셀의 캐패시터 제조방법에 있어서, 웨이퍼 상부에 제1 및 제2절연막을 형성한 후, 저장전극 콘택마스크를 이용하여 콘택영역의 제2 및 제1절연막을 식각하여 콘택홀을 형성하는 공정과, 제1도전층을 상기 제2절연막과 콘택홀 상부에 증착하는 공정과, 제3절연막을 제2도전층 상부에 예정된 두께로 형성하는 공정과, 상기 제3절연막의 일정두께를 비등방성 식각공정으로 식각하여 콘택홀 저부의 제2도전층을 노출시키는 공정과 제2도전층을 증착하여 제1도전층에 접속시키는 공정과, 제2도전층 상부에 제4절연막을 도포하되, 상기 콘택홀을 채우도록 형성하는 단계와, 상기 제4절연막을 에치백 공정으로 일정두께 식각하여 콘택홀 상부에 있는 제2도전층을 노출시키는 단계와, 제3도전층을 증착한 다음, 그 상부에 저장전극 마스크를 형성하는 단계와, 저장전극 마스크가 없는 지역의 제3, 제2, 제1도전층과 제4, 제3절연층을 순차적으로 식각하는 공정과, 남아있는 제4, 제3절연층과 제2절연층을 습식식각으로 제거하여 제1, 제2 및 제3도전층 패턴으로 이루어진 저장전극을 형성하는 공정을 포함하는 캐패시터 제조방법.A method for manufacturing a capacitor of a DRAM cell, comprising: forming a contact hole by forming first and second insulating layers on a wafer and then etching the second and first insulating layers in a contact region using a storage electrode contact mask; Depositing a first conductive layer on the second insulating layer and the contact hole, forming a third insulating layer on the second conductive layer to a predetermined thickness, and anisotropic etching the predetermined thickness of the third insulating layer. Etching to expose the second conductive layer at the bottom of the contact hole, depositing the second conductive layer to connect to the first conductive layer, and applying a fourth insulating layer on the second conductive layer to fill the contact hole. Exposing the second conductive layer on the contact hole by etching the fourth insulating layer to a predetermined thickness by using an etch back process, depositing a third conductive layer, and then applying a storage electrode mask thereon. Forming step, Sequentially etching the third, second and first conductive layers and the fourth and third insulating layers in the region where the long electrode mask is not present, and wet etching the remaining fourth and third insulating layers and the second insulating layer. And forming a storage electrode formed of the first, second and third conductive layer patterns by removing the same. 제1항에 있어서, 상기 제2, 제3 및 제4절연막은 저온옥사이드 박막으로 형성하는 것을 특징으로 하는 캐패시터 제조방법.The method of claim 1, wherein the second, third, and fourth insulating layers are formed of a low temperature oxide thin film. 제1항에 있어서, 상기 제1, 제2도전층은 다결정 실리콘층으로 형성하는 것을 특징으로 하는 캐패시터 제조방법.The method of claim 1, wherein the first and second conductive layers are formed of a polycrystalline silicon layer. 제1항에 있어서, 상기 제2절연막은 제1절연막에 대하여 예정된 에찬트에서 식각비가 다른 것을 특징으로 하는 캐패시터 제조방법.The method of claim 1, wherein the second insulating layer has a different etching ratio at a predetermined etchant with respect to the first insulating layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR93026882A 1993-12-08 1993-12-08 Process for manufacturing capacitor of semiconductor KR970007791B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93026882A KR970007791B1 (en) 1993-12-08 1993-12-08 Process for manufacturing capacitor of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93026882A KR970007791B1 (en) 1993-12-08 1993-12-08 Process for manufacturing capacitor of semiconductor

Publications (2)

Publication Number Publication Date
KR950019956A true KR950019956A (en) 1995-07-24
KR970007791B1 KR970007791B1 (en) 1997-05-16

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Application Number Title Priority Date Filing Date
KR93026882A KR970007791B1 (en) 1993-12-08 1993-12-08 Process for manufacturing capacitor of semiconductor

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Also Published As

Publication number Publication date
KR970007791B1 (en) 1997-05-16

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