KR940016766A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR940016766A
KR940016766A KR1019920026714A KR920026714A KR940016766A KR 940016766 A KR940016766 A KR 940016766A KR 1019920026714 A KR1019920026714 A KR 1019920026714A KR 920026714 A KR920026714 A KR 920026714A KR 940016766 A KR940016766 A KR 940016766A
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KR
South Korea
Prior art keywords
polysilicon layer
pattern
insulating film
cavity
forming
Prior art date
Application number
KR1019920026714A
Other languages
Korean (ko)
Other versions
KR960003859B1 (en
Inventor
이헌철
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920026714A priority Critical patent/KR960003859B1/en
Publication of KR940016766A publication Critical patent/KR940016766A/en
Application granted granted Critical
Publication of KR960003859B1 publication Critical patent/KR960003859B1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 고집적 반도체 소자의 캐패시터 제조방법에 관한것으로, 디램셀의 캐패시터 용량을 증대시키기 위해 제1 및 제 2 캐비티 구조를 저장전극을 형성하되, 종래의 캐비티 구조의 저장전극과 핀구조의 저장전극을 형성하는 공정을 이용한 저장전극 제조방법이다.The present invention relates to a method for manufacturing a capacitor of a highly integrated semiconductor device, wherein the storage electrodes of the first and second cavity structures are formed to increase the capacitance of the DRAM cell, and the storage electrodes of the conventional cavity structure and the fin structure are formed. The storage electrode manufacturing method using the process of forming a.

Description

반도체 소자의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도 내지 제 6 도는 본 발명에 의해 캐패시터의 저장전극 제조단계를 도시한 단면도.1 to 6 are cross-sectional views showing a storage electrode manufacturing step of a capacitor according to the present invention.

Claims (2)

반도체 소자의 캐패시터 제조방법에 있어서, 실리콘기판에 형성된 트랜지스터 상부에 제 1 절연층을 형성하고 평탄화시킨 다음, 제 1 절연막의 소정부분을 식각하여 실리콘기판의 노출된 저장전극 콘택홀을 형성하는 단계와, 전체구조 상부에 제 1 폴리실리콘층, 제 2 절연막, 제 2 폴리실리콘층, 제 3 절연막을 예정된 두께로 각각 적층하는 단계와, 제 3 절연층 상부에 캐비티 마스크용 감광막패턴을 형성하는 단계와, 상기 감광막패턴을 마스크로 사용하여 제 3 절연막, 제 2 폴리실리콘층 및 제 2 절연막을 식각하여 제 3 절연막패턴, 제 2 폴리실리콘층 패턴 및 제 2 절연막패턴을 형성하고, 감광막패턴을 제거하는 단계와, 전체구조 상부에 제 3 폴리실리콘층을 증착하고, 그 상부에 저장전극 마스크용 감광막패턴을 형성하는 단계와, 제 2 절연막패턴과 제 3 절연막패턴을 습식식각 공정으로 제거하여 제 1 캐비티와 제 2 캐비티를 형성하는 단계와, 노출된 제 1 폴리실리콘층을 식각하여 제 1 폴리실리콘층 패턴을 형성한후 저장전극 마스용 감광막패턴을 제거하는 단계로 이루어져 그로인하여 제 1 캐비티, 제 2 캐비티를 가지며 제1, 제2, 제 3 폴리실리콘층 패턴으로 이루어지는 저장전극을 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.A method of manufacturing a capacitor of a semiconductor device, comprising: forming a planarized first insulating layer over a transistor formed on a silicon substrate, and then planarizing the etching process to form an exposed storage electrode contact hole of the silicon substrate by etching a predetermined portion of the first insulating layer; Stacking a first polysilicon layer, a second insulating film, a second polysilicon layer, and a third insulating film on the entire structure to a predetermined thickness, and forming a photoresist pattern for a cavity mask on the third insulating layer; And etching the third insulating film, the second polysilicon layer and the second insulating film using the photosensitive film pattern as a mask to form a third insulating film pattern, a second polysilicon layer pattern and a second insulating film pattern, and removing the photosensitive film pattern. Depositing a third polysilicon layer over the entire structure, and forming a photoresist pattern for a storage electrode mask thereon; Removing the insulating layer pattern by a wet etching process to form a first cavity and a second cavity, etching the exposed first polysilicon layer to form a first polysilicon layer pattern, and then forming a photoresist pattern for a storage electrode mask. And forming a storage electrode having a first cavity, a second cavity, and having a first, second, and third polysilicon layer pattern. 제 1 항에 있어서, 상기 제 1 절연막과 제 1 폴리실리콘층 사이에 질화막을 형성하여 제 1 폴리실리콘층 식각시 식각정지층으로 이용하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 1, wherein a nitride film is formed between the first insulating film and the first polysilicon layer to serve as an etch stop layer during etching of the first polysilicon layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920026714A 1992-12-30 1992-12-30 Method of making a capacitor for a semiconductor device KR960003859B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920026714A KR960003859B1 (en) 1992-12-30 1992-12-30 Method of making a capacitor for a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920026714A KR960003859B1 (en) 1992-12-30 1992-12-30 Method of making a capacitor for a semiconductor device

Publications (2)

Publication Number Publication Date
KR940016766A true KR940016766A (en) 1994-07-25
KR960003859B1 KR960003859B1 (en) 1996-03-23

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920026714A KR960003859B1 (en) 1992-12-30 1992-12-30 Method of making a capacitor for a semiconductor device

Country Status (1)

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KR (1) KR960003859B1 (en)

Also Published As

Publication number Publication date
KR960003859B1 (en) 1996-03-23

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