KR930018721A - Method for manufacturing capacitor storage electrode of DRAM cell - Google Patents

Method for manufacturing capacitor storage electrode of DRAM cell Download PDF

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Publication number
KR930018721A
KR930018721A KR1019920002285A KR920002285A KR930018721A KR 930018721 A KR930018721 A KR 930018721A KR 1019920002285 A KR1019920002285 A KR 1019920002285A KR 920002285 A KR920002285 A KR 920002285A KR 930018721 A KR930018721 A KR 930018721A
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KR
South Korea
Prior art keywords
polysilicon
depositing
etching
oxide film
contact hole
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Application number
KR1019920002285A
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Korean (ko)
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KR950013900B1 (en
Inventor
정제승
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문정환
금성일렉트론 주식회사
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Priority to KR1019920002285A priority Critical patent/KR950013900B1/en
Publication of KR930018721A publication Critical patent/KR930018721A/en
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Publication of KR950013900B1 publication Critical patent/KR950013900B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

디램 셀의 캐패시터 저장전극 제조방법에 있어서, 디램 용 트랜지스터들은 반도체 기판상에 종래의 방법으로 형성한 다음에, 기판전체에 산화막(20)을 데포지션하여 평탄화시키고, 그 위에 질화막(21)과 폴리실리콘(22)을 차례로 데포지션하는 단계, 캐패시터의 스토리지 노드 콘택마스크 작업을 하여 콘택홀이 형성될 부분의 폴리실리콘(22)을 식각하여 제거하는 단계, 다시 폴리실리콘을 데포지션하고 에치백하여 폴리실리콘의 사이드월(23)을 형성하는 단계, 이 폴리실리콘(22,23)을 마스크로 이용하여 질화막(21)과 산화막(20)을 에치하여 콘택홀을 형성하는 단계 그 후 폴리실리콘(23)을 데포지션하여 콘택홀을 폴리실리콘으로 완전히 채우고, 그 위에 산화막(24)를 두껍게 데포지션하는 단계, 다시 스토리지노드 콘택마스크를 이용하여 폴리실리콘(23)위의 산화막(24)에 콘택홀을 형성하고 폴리실리콘(25)을 데포지션하는 단계, 폴리실리콘(25)을 에치백하여 작은 실린더(26)을 형성한 후, 스토리지 노드 마스크를 이용하여 포토레지스트를 패턴닝하고 산화막(24)을 식각한 후 포토레지스트를 제거하는 단계, 폴리실리콘을 데포지션하고 에치 백하여 작은 실린더(26) 바깥쪽으로 큰 실린더(27)를 형성하고, 작은 실린더(26)와 큰 실린더(27) 사이의 산화막(24)을 습식식각 공정으로 제거하는 단계로 이루어지는 디램셀의 캐패시터 저장전극 제조방법.In the method of manufacturing a capacitor storage electrode of a DRAM cell, the DRAM transistors are formed on a semiconductor substrate in a conventional manner, and then deposited and planarized by depositing the oxide film 20 over the entire substrate. Depositing the silicon 22 in sequence, etching the polysilicon 22 in the portion where the contact hole is to be formed by performing a storage node contact mask operation of the capacitor, and depositing and etching back the polysilicon. Forming the sidewalls 23 of silicon, etching the nitride film 21 and the oxide film 20 using the polysilicon 22, 23 as a mask to form a contact hole, and then the polysilicon 23 Depositing the contact hole completely with polysilicon, and thickly depositing the oxide layer 24 thereon, again using the storage node contact mask, on the polysilicon 23. Forming a contact hole in the film 24 and depositing the polysilicon 25, etching back the polysilicon 25 to form a small cylinder 26, and then patterning the photoresist using a storage node mask. And etching the oxide film 24 and then removing the photoresist, depositing and etching back the polysilicon to form the large cylinder 27 out of the small cylinder 26, the small cylinder 26 and the large cylinder. A method for manufacturing a capacitor storage electrode of a DRAM cell comprising the step of removing the oxide film (24) between the (27) by a wet etching process.

Description

디램 셀의 캐패시터 저장전극 제조방법Method for manufacturing capacitor storage electrode of DRAM cell

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 공정도.1 is a process diagram of the present invention.

Claims (1)

디램 셀의 캐패시터 저장전극 제조방법에 있어서, 디램 용 트랜지스터들은 반도체 기판상에 종래의 방법으로 형성한 다음에, 기판전체에 산화막(20)을 데포지션하여 평탄화시키고, 그 위에 질화막(21)과 폴리실리콘(22)을 차례로 데포지션하는 단계, 캐패시터의 스토리지 노드 콘택마스크 작업을 하여 콘택홀이 형성될 부분의 폴리실리콘(22)을 식각하여 제거하는 단계, 다시 폴리실리콘을 데포지션하고 에치백하여 폴리실리콘의 사이드월(23)을 형성하는 단계, 이 폴리실리콘(22,23)을 마스크로 이용하여 질화막(21)과 산화막(20)을 에치하여 콘택홀을 형성하는 단계. 그 후 폴리실리콘(23)을 데포지션하여 콘택홀을 폴리실리콘으로 완전히 채우고, 그 위에 산화막(24)를 두껍게 데포지션하는 단계, 다시 스토리지노드 콘택마스크를 이용하여 폴리실리콘(23)위의 산화막(24)에 콘택홀을 형성하고 폴리실리콘(25)을 데포지션하는 단계, 폴리실리콘(25)을 에치백하여 작은 실린더(26)을 형성한 후, 스토리지 노드 마스크를 이용하여 포토레지스트를 패턴닝하고 산화막(24)을 식각한 후 포토레지스트를 제거하는 단계, 폴리실리콘을 데포지션하고 에치 백하여 작은 실린더(26) 바깥쪽으로 큰 실린더(27)를 형성하고, 작은 실린더(26)와 큰 실린더(27) 사이의 산화막(24)을 습식식각 공정으로 제거하는 단계로 이루어지는 디램셀의 캐패시터 저장전극 제조방법.In the method of manufacturing a capacitor storage electrode of a DRAM cell, the DRAM transistors are formed on a semiconductor substrate in a conventional manner, and then deposited and planarized by depositing the oxide film 20 over the entire substrate. Depositing the silicon 22 in sequence, etching the polysilicon 22 in the portion where the contact hole is to be formed by performing a storage node contact mask operation of the capacitor, and depositing and etching back the polysilicon. Forming a sidewall (23) of silicon; forming a contact hole by etching the nitride film (21) and the oxide film (20) using the polysilicon (22, 23) as a mask. Thereafter, the polysilicon 23 is deposited to completely fill the contact hole with polysilicon, and the oxide film 24 is thickly deposited thereon, and the oxide layer on the polysilicon 23 is formed using the storage node contact mask. 24, forming a contact hole and depositing polysilicon 25, etching back the polysilicon 25 to form a small cylinder 26, and then patterning the photoresist using a storage node mask. Etching the oxide film 24 and then removing the photoresist, depositing and etching back the polysilicon to form a large cylinder 27 out of the small cylinder 26, the small cylinder 26 and the large cylinder 27 A method for manufacturing a capacitor storage electrode of a DRAM cell comprising the step of removing the oxide film (24) in a wet etching process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920002285A 1992-02-15 1992-02-15 Dram cell manufacturing process KR950013900B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920002285A KR950013900B1 (en) 1992-02-15 1992-02-15 Dram cell manufacturing process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920002285A KR950013900B1 (en) 1992-02-15 1992-02-15 Dram cell manufacturing process

Publications (2)

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KR930018721A true KR930018721A (en) 1993-09-22
KR950013900B1 KR950013900B1 (en) 1995-11-17

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KR1019920002285A KR950013900B1 (en) 1992-02-15 1992-02-15 Dram cell manufacturing process

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100745924B1 (en) * 2005-06-30 2007-08-02 주식회사 하이닉스반도체 Method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100745924B1 (en) * 2005-06-30 2007-08-02 주식회사 하이닉스반도체 Method for manufacturing semiconductor device

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Publication number Publication date
KR950013900B1 (en) 1995-11-17

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