KR950021548A - Capacitor of Semiconductor Memory Device and Manufacturing Method Thereof - Google Patents

Capacitor of Semiconductor Memory Device and Manufacturing Method Thereof Download PDF

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KR950021548A
KR950021548A KR1019930028594A KR930028594A KR950021548A KR 950021548 A KR950021548 A KR 950021548A KR 1019930028594 A KR1019930028594 A KR 1019930028594A KR 930028594 A KR930028594 A KR 930028594A KR 950021548 A KR950021548 A KR 950021548A
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side wall
conductive layer
layer
etching
etch stop
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KR1019930028594A
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KR0124576B1 (en
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박재현
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문정환
금성일렉트론 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 메모리장치의 커패시터 및 이의 제조방법에 관한 것으로, 메모리셀 트랜지스터의 소오스(또는 드레인)영역에 접속되어 형성된 기둥부(A)와, 상기 기둥부(A)상에 기둥부의 직경보다 큰 직경을 가지고 형성된 원판형태의 밑면부(B), 상기 밑면부(B)의 가장자리에 수직방향으로 일정높이를 가지고 형성된 원통형태의 외측 벽면부(C), 및 상기 외측 벽면부(C)의 안쪽에 외측 벽면부와 일정거리를 두고 형성된 원통형태의 내측 벽면부(D)로 구성된 이중 실린더 구조의 커패시터 스토리지노드를 포함하고 구성되는 것을 특징으로 하는 반도체 메모리장치의 커패시터를 제공함으로써 대용량의 커패시터 구현을 가능하게 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor memory device and a method of manufacturing the same, wherein the pillar portion A is connected to a source (or drain) region of a memory cell transistor, and the pillar portion A is larger than the diameter of the pillar portion. A bottom portion B of a disk shape having a diameter, an outer wall portion C having a cylindrical shape formed with a predetermined height in a direction perpendicular to the edge of the bottom portion B, and an inner side of the outer wall portion C. Implementing a large capacity capacitor by providing a capacitor of the semiconductor memory device comprising a capacitor storage node of a double cylinder structure consisting of a cylindrical inner wall portion (D) formed at a certain distance from the outer wall portion in the Make it possible.

Description

반도체 메모리장치의 커패시터 및 이의 제조방법Capacitor of Semiconductor Memory Device and Manufacturing Method Thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 실린더구조의 스토리지노드를 갖춘 커패시터 형성방법을 도시한 공정순서도.1 is a process flowchart showing a method of forming a capacitor having a storage node of a conventional cylinder structure.

제2도는 본 발명의 실린더구조의 스토리지노드를 갖춘 커패시터 형성방법을 도시한 공정순서도.2 is a process flowchart showing a method of forming a capacitor having a storage node of a cylinder structure according to the present invention.

제3도는 본 발명의 커패시터의 스토리지노드 부위를 나타낸 개략적인 사시도.Figure 3 is a schematic perspective view showing the storage node portion of the capacitor of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

9 : 절연층 10 : 제1식각저지층9 Insulation layer 10 First etch stop layer

11 : 버퍼층 14 : 제1도전층11 buffer layer 14 first conductive layer

15 : 제2식각저지층 16 : 제2도전층15: second etch stop layer 16: the second conductive layer

17 : 포토레지스트패턴 18 : 제1측벽17 photoresist pattern 18 first side wall

19 : 제2측벽 20 : 제3측벽19: second side wall 20: third side wall

21 : 커패시터 스토리지노드21: Capacitor Storage Node

Claims (10)

반도체 기판(1)상에 형성된 셀트랜지스터 상부에 절연층(9), 제1식각저지층(10), 버퍼층(11)을 차례로 형성하는 공정과, 상기 버퍼층(11), 제1식각저지층(10) 및 절연층(9)을 선택적으로 식각하여 상기 셀트랜지스터의 소오스(또는 드레인)영역이 노출되도록 콘택홀을 형성하는 공정, 결과물 전면에 제1도전층(14), 제2식각저지층(15), 제2도전층(16)을 차례로 형성하는 공정, 상기 제2도전층(16)상에 포토레지스트를 도포하고 이를 포토리소그래피공정을 통해 각각의 셀 커패시터의 스토리지노드패턴(17)으로 패터닝하는 공정, 상기 포토레지스트패턴(17)을 마스크로 하여 상기 제2도전층(16)과 제2식각저지층(15)을 차례로 식각하는 공정, 상기 스토리지노드패턴으로 패터닝된 제2도전층(16) 및 제2식각저지층(15)의 측면에 제1측벽(18)을 형성하는 공정, 상기 제1측벽(18)의 노출된 측면에 제2측벽(19)을 형성하는 공정, 상기 제1측벽(18) 및 제2측벽(19)을 마스크로 하여 상기 제2도전층(16) 및 제1도전층(14)을 식각하는 공정, 상기 제2도전층의 식각에 따라 노출되는 상기 제1측벽(18)의 측면에 제3측벽(20)을 형성하는 공정, 상기 제1측벽(18)을 제거하는 공정, 상기 제2측벽(19) 및 제3측벽(20)을 마스크로 하여 그 하부의 제1도전층(14)을 일정 깊이로 식각하여 일정두께가 남도록 하는 공정, 및 상기 제2측벽 및 제3측벽(19, 20)과 버퍼층(11)을 제거하는 공정을 포함하여 이루어지는 것을 특징으로 하는 반도체 메모리 장치의 커패시터 제조방법.Sequentially forming an insulating layer 9, a first etch stop layer 10, and a buffer layer 11 on the cell transistor formed on the semiconductor substrate 1, and the buffer layer 11 and the first etch stop layer ( 10) and selectively etching the insulating layer 9 to form a contact hole to expose the source (or drain) region of the cell transistor, the first conductive layer 14, the second etch stop layer ( 15), forming a second conductive layer 16 in sequence, applying a photoresist on the second conductive layer 16 and patterning it into a storage node pattern 17 of each cell capacitor through a photolithography process. And etching the second conductive layer 16 and the second etch stop layer 15 in sequence using the photoresist pattern 17 as a mask, and the second conductive layer 16 patterned with the storage node pattern. ) And the first side wall 18 on the side of the second etch stop layer 15, the first side wall 18 The second side wall 19 is formed on the exposed side surface, and the second conductive layer 16 and the first conductive layer 14 are formed using the first side wall 18 and the second side wall 19 as a mask. Etching, forming a third sidewall 20 on a side surface of the first sidewall 18 exposed by etching of the second conductive layer, removing the first sidewall 18, the first step Etching the first conductive layer 14 below the second side wall 19 and the third side wall 20 as a mask to a predetermined depth so that a predetermined thickness remains, and the second side wall and the third side wall 19 20) and a process of removing the buffer layer (11). 제1항에 있어서, 상기 제1도전층(14) 및 제2도전층(16)을 각각 폴리실리콘을 증착하여 형성함을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.The method of claim 1, wherein the first conductive layer (14) and the second conductive layer (16) are formed by depositing polysilicon, respectively. 제1항에 있어서, 상기 제1도전층(14)은 적어도 5000Å 이상 두껍게 형성하는 것을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.The method of claim 1, wherein the first conductive layer (14) is formed to be thicker than at least 5000 GPa. 제1항에 있어서, 상기 제2식각저지층(15)은 상기 제1도전층(14)과의 식각선택비가 높은 물질로 형성함을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.The method of claim 1, wherein the second etch stop layer (15) is formed of a material having a high etching selectivity with respect to the first conductive layer (14). 제1항에 있어서, 상기 제1측벽(18)은 상기 스토리지노드패턴으로 패터닝된 제2도전층(16) 및 제2식각저지층(15) 전면에 제2도전층(16)과의 식각선택비가 높은 물질을 증착한 후 이를 에치백하여 형성함을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.The etching method of claim 1, wherein the first side wall 18 is etched with the second conductive layer 16 over the second conductive layer 16 and the second etch stop layer 15 patterned with the storage node pattern. A method of manufacturing a capacitor of a semiconductor memory device, characterized in that formed by depositing a material having a high rain and then etched back. 제1항에 있어서, 상기 제2측벽(19)은 상기 스토리지노드패턴으로 패터닝된 제2도전층(16) 및 제2식각저지층(15)과 제1측벽(18) 전면에 상기 제2도전층(16) 및 제1측벽(18)과의 식각선택비가 높은 물질을 증착한 후 이를 에치백하여 형성함을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.2. The second conductive layer of claim 1, wherein the second side wall 19 is formed on the entire surface of the second conductive layer 16, the second etch stop layer 15, and the first side wall 18. And depositing a material having a high etching selectivity with the layer (16) and the first side wall (18), and then etching back the material (16). 제1항에 있어서, 상기 제3측벽(20)은 상기 제1측벽(18) 및 제2측벽(19)이 형성된 결과물 전면에 제1측벽(18)을 이루는 물질과의 식각선택비가 높은 물질을 증착한 후 이를 에치백하여 형성함을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.The material of claim 1, wherein the third side wall 20 is formed of a material having a high etch selectivity with respect to a material forming the first side wall 18 on the entire surface of the product on which the first side wall 18 and the second side wall 19 are formed. A method of manufacturing a capacitor of a semiconductor memory device, characterized in that it is formed by etching back after deposition. 제7항에 있어서, 상기 제3측벽(20) 형성용 물질을 증착한 후 에치백하는 과정에서 상기 남아 있는 제2식각저지층(15)이 함께 식각하는 것을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.The method of claim 7, wherein the remaining second etch stop layer 15 is etched together during the etching of the third sidewall 20 forming material. Way. 제1항에 있어서, 상기 제1측벽(18)은 질화막으로 형성하고, 제2측벽(19) 및 제3측벽(20)은 산화막으로 형성하는 것을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.The method of claim 1, wherein the first side wall (18) is formed of a nitride film, and the second side wall (19) and the third side wall (20) are formed of an oxide film. 제1항에 있어서, 상기 제1측벽(18)은 산화막으로 형성하고, 제2측벽(19) 및 제3측벽(20)은 질화막으로 형성하는 것을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.The method of claim 1, wherein the first side wall (18) is formed of an oxide film, and the second side wall (19) and the third side wall (20) are formed of a nitride film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930028594A 1993-12-20 1993-12-20 Capacitor apparatus of semiconductor memory KR0124576B1 (en)

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