KR950010076A - DRAM cell manufacturing method of semiconductor device - Google Patents

DRAM cell manufacturing method of semiconductor device Download PDF

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KR950010076A
KR950010076A KR1019930017581A KR930017581A KR950010076A KR 950010076 A KR950010076 A KR 950010076A KR 1019930017581 A KR1019930017581 A KR 1019930017581A KR 930017581 A KR930017581 A KR 930017581A KR 950010076 A KR950010076 A KR 950010076A
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South Korea
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forming
contact hole
bit line
storage electrode
polysilicon layer
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KR1019930017581A
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Korean (ko)
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KR970008811B1 (en
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최양규
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes

Abstract

본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 디램셀에서 셀사이즈를 최소로 하기 위하여 워드방향으로 길게 오픈된 저장전극 콘택 패드 마스크를 사용하여 비트라인에 의해 자기정렬되는 콘택홀을 형성한 다음, 콘택홀 측벽에 형성되는 절연층 스페이서에 의해 비트라인과 저장전극을 절연시키는 디램셀의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and in particular, to form a contact hole self-aligned by a bit line using a storage electrode contact pad mask that is opened in a long direction in the word direction in order to minimize the cell size in a DRAM cell. The present invention relates to a method for manufacturing a DRAM cell insulated from a bit line and a storage electrode by an insulating layer spacer formed on sidewalls of a contact hole.

Description

반도체소자의 디램셀 제조방법DRAM cell manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도 내지 제9도는 본 발명의 제1실시예에 의해 디램셀의 제조공정을 도시한 단면도.2 to 9 are cross-sectional views showing the manufacturing process of the DRAM cell according to the first embodiment of the present invention.

제2도는 비트라인 콘택홀에 비트라인용 다결정실리콘층, 질화막, 식각베리어용 다결정실리콘층을 적층한 것을 도시한 단면도.2 is a cross-sectional view showing a lamination of a polycrystalline silicon layer for a bit line, a nitride film, and an polysilicon layer for an etching barrier in a bit line contact hole.

제3도는 비트라인 마스크를 이용하여 비트라인 패턴을 형성한 것을 도시한 단면도.3 is a cross-sectional view illustrating the formation of a bit line pattern using a bit line mask.

제4도는 저장전극 콘택 패스 마스크를 이용하여 저장전극용 콘택홀을 형성한 것을 도시한 단면도.4 is a cross-sectional view of a storage electrode contact hole formed using a storage electrode contact path mask.

제5도는 비트라인 측벽과 저장전극용 콘택홀 측벽에 절연물 스페이서를 형성한 것을 도시한 단면도.FIG. 5 is a cross-sectional view illustrating an insulator spacer formed on sidewalls of bit lines and sidewalls of contact holes for storage electrodes.

제6도는 저장전극용 콘택홀에만 감광막을 채운 것을 도시한 단면도.6 is a cross-sectional view showing that the photosensitive film is filled only in the contact hole for the storage electrode.

제7도는 비트라인 상부에 있는 다결정실리콘층을 제거하고 저장전극용 콘택홀에 있는 감광막을 제거한 것을 도시한 단면도.7 is a cross-sectional view showing that the polysilicon layer on the bit line is removed and the photoresist film in the storage hole contact hole is removed.

제8도는 저장적극용 감광막을 형성한 것을 도시한 단면도.8 is a cross-sectional view showing the formation of a storage photosensitive film.

제9도는 저장전극패턴을 형성한 것을 도시한 단면도.9 is a cross-sectional view showing a storage electrode pattern formed.

Claims (8)

반도체소자의 디램셀(DRAM)제조방법에 있어서, 실리콘기판위에 산화막, 게이트산화막, 워드라인 및 소오스/드레인을 공지의 기술로 형성하고 제1산화절연막으로 워드라인을 절연시킨후, 그 상부에 평탄화된 제2산화절연막을 형성하는 공정과, 비트라인 콘택홀을 형성하고, 그상부에 비트라인용 다결정실리콘층, 질화막, 식각베리어용 다결정실리콘층을 적층하는 공정과, 비트라인 마스크를 이용한 사진식각공정으로 비트라인과 질화막패턴, 식각베어용 다결정실리콘층 패턴을 형성하는 공정과, 저장전극 콘택 패드 마스크를 이용한 사진식각공정으로 제1, 제2산화절연막의 일정부분을 식각하여 워드라인 방향으로는 비트라인에의해 자기정렬되는 콘택홀을 형성하는 공정과, 콘택홀 측벽과 비트라인 측벽에 산화막 스페이서를 형성하는 공정과, 상기 비트라인 상부에 있는 다결정실리콘 패턴을 제거하는 공정과, 저장전극용 다결정실리콘을 콘택홀을 포함한 전체상부구조에 증착하고 저장전극 마스크를 이용한 사진식각방법으로 일정부부의 저장전극용 다결정실리콘층을 식각하여 저장전극을 형성하는 공정을 포함하는 반도체소자의 제조방법.In a method of manufacturing a DRAM cell of a semiconductor device, an oxide film, a gate oxide film, a word line and a source / drain are formed on a silicon substrate by a known technique, and the word line is insulated with a first oxide insulating film, and then planarized thereon. Forming a second oxide insulating film, forming a bit line contact hole, laminating a polysilicon layer for a bit line, a nitride film, and a polysilicon layer for an etching barrier thereon, and photolithography using a bit line mask Forming a bit line, a nitride film pattern, and a polysilicon layer pattern for an etch bear, and a photolithography process using a storage electrode contact pad mask to etch certain portions of the first and second oxide insulating films in the word line direction. Forming a contact hole self-aligned by the bit line, forming an oxide spacer on the contact hole sidewall and the bitline sidewall, Etching the polysilicon layer for the storage electrode at a certain part by removing the polysilicon pattern on the upper line, depositing the polysilicon for the storage electrode on the entire upper structure including the contact hole, and using a photolithography method using the storage electrode mask. Forming a storage electrode. 제1항에 있어서, 상기 질화막 스페이서는 전체구조상부에 일정두께로 도포한 후, 이방성식각공정에 의해 콘택홀과 비트라인측벽에 형성하는 것을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the nitride film spacer is coated on the entire structure with a predetermined thickness and then formed in the contact hole and the bit line side wall by an anisotropic etching process. 제1항에 있어서, 상기 저장전극 콘택 패드 마스크의 창이 워드라인 방향으로 길게 형성되고 워드라인이 노출되지 않도록 되는 것을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the window of the storage electrode contact pad mask is formed to extend in a word line direction, and the word line is not exposed. 제1항에 있어서, 상기 다결정실리콘 패턴을 제거하기 위하여 콘택홀에만 감광막을 채운 다음, 다결정실리콘층 패턴을 제거하고 다시 콘택홀에 채워진 감광막을 제거하는 것을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the photoresist is filled only in the contact hole in order to remove the polysilicon pattern, the polysilicon layer pattern is removed, and the photoresist film filled in the contact hole is removed. 반도체소자의 디램셀 제조방법에 있어서, 실리콘기판위에 산화막, 게이트산화막, 워드라인 및 소오스/드레인을 공지의 기술로 형성하고 제1산화절연막으로 워드라인을 절연시킨후, 그 상부에 평탄화된 제2산화절연막을 형성하는 공정과, 비트라인 콘택홀을 형성하고, 그상부에 비트라인용 다결정실리콘층, 질화막, 식각베리어용 다결정실리콘층 적층하는 공정과, 비트라인 마스크를 이용한 사진식각공정으로 비트라인과 질화막패턴, 식각베어용 다결정실리콘층 패턴을 형성하는 공정과, 저장전극 콘택 패드 마스크를 이용한 사진식각공정으로 제1, 제2산화막의 일정부분을 식각하여 워드라인 방향으로는 비트라인에 의해 자기정렬되는 콘택홀을 형성하는 공정과, 콘택홀 측벽과 비트라인 측벽에 질화막 스페이서를 형성하는 공정과, 상기 비트라인 상부에 있는 다결정실리콘 패턴을 제거하는 공정과, 저장전극용 제1다결정실리콘을 콘택홀을 포함한 전체상부구조에 증착하고 상부에 평탄한 제3산화절연막을 형성하는 공정과, 저장전극용 콘택마스크를 이용하여 노출된 제3산화절연막을 식각하여 제1다력정실리콘층이 노출된 콘택홀을 형성하는 공정과, 저장전극용 제2다결정실리콘층을 증착한 다음, 그 상부에 저장전극 마스크용 감광막 패터을 형성하는 공정과, 노출된 제2다결정실리콘층을 건식식각하고 습식식각으로 제2산화절연막을 제거하는 공정과, 건식식각으로 제1다결정실리콘층을 식각하여 제1,2다결정실리콘층 패턴으로 이루어진 핀(fin)형 저장전극을 형성하는 공정을 포함하는 반도체소자의 제조방법.In a method for manufacturing a DRAM cell of a semiconductor device, an oxide film, a gate oxide film, a word line, and a source / drain are formed on a silicon substrate by a known technique, and the word line is insulated with a first oxide insulating film, and then the second planarized thereon. A bit line by forming an oxide insulating film, forming a bit line contact hole, laminating a polysilicon layer for a bit line, a nitride film, and a polysilicon layer for an etch barrier thereon, and a photolithography process using a bit line mask A process of forming a nitride film pattern, a polysilicon layer pattern for an etching bear, and a photolithography process using a storage electrode contact pad mask to etch certain portions of the first and second oxide films by bit lines in the word line direction. Forming a contact hole to be aligned; forming a nitride film spacer on the contact hole sidewalls and the bitline sidewalls; Removing the polysilicon pattern in the portion; depositing the first polycrystalline silicon for the storage electrode on the entire upper structure including the contact hole; forming a flat third oxide insulating film on the upper portion; and using a contact electrode for the storage electrode. Etching the exposed third oxide insulating film to form a contact hole exposing the first polysilicon silicon layer, depositing a second polysilicon layer for the storage electrode, and then depositing a photoresist pattern for the storage electrode mask thereon. Forming the first polycrystalline silicon layer by dry etching the exposed second polysilicon layer and removing the second oxide insulating layer by wet etching, and etching the first polycrystalline silicon layer by dry etching to form the first and second polysilicon layer patterns. A method of manufacturing a semiconductor device comprising the step of forming a fin storage electrode. 제5항에 있어서, 제3산화절연막의 두께를 조절하여 캐패시터의 용량을 조절하는 방법을 포함하는 반도체소자의 제조방법.The method of manufacturing a semiconductor device according to claim 5, comprising a method of controlling a capacitance of a capacitor by adjusting a thickness of a third oxide insulating film. 반도체소자의 디램셀 제조방법에 있어서, 실리콘기판위에 산화막, 게이트산화막, 워드라인 및 소오스/드레인을 공지의 기술로 형성하고 제1산화절연막으로 워드라인을 절연시킨후, 그 상부에 평탄화된 제2산화절연막을 형성하는 공정과, 비트라인 콘택홀을 형성하고, 그상부에 비트라인용 다결정실리콘층, 질화막, 식각베리어용 다결정실리콘층 적층하는 공정과, 비트라인 마스크를 이용한 사진식각공정으로 비트라인과 질화막패턴, 식각베어용 다결정실리콘층 패턴을 형성하는 공정과, 저장전극 콘택 패드 마스크를 이용한 사진식각공정으로 제1, 제2산화막의 일정부분을 식각하여 워드라인 방향으로는 비트라인에 의해 자기정렬되는 콘택홀을 형성하는 공정과, 콘택홀 측벽과 비트라인 측벽에 산화막 스페이서를 형성하는 반도체 소자의 제조방법.In a method for manufacturing a DRAM cell of a semiconductor device, an oxide film, a gate oxide film, a word line, and a source / drain are formed on a silicon substrate by a known technique, and the word line is insulated with a first oxide insulating film, and then the second planarized thereon. A bit line by forming an oxide insulating film, forming a bit line contact hole, laminating a polysilicon layer for a bit line, a nitride film, and a polysilicon layer for an etch barrier thereon, and a photolithography process using a bit line mask A process of forming a nitride film pattern, a polysilicon layer pattern for an etching bear, and a photolithography process using a storage electrode contact pad mask to etch certain portions of the first and second oxide films by bit lines in the word line direction. Forming a contact hole to be aligned; and forming an oxide spacer on the contact hole sidewall and the bit line sidewall. 제7항에 있어서, 상기 저장전극용 다결정실리콘층을 식각할 때 그 하부의 노출되어지는 식각베리어용 다결정실리콘층을 식각하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 7, wherein the etching barrier polycrystalline silicon layer is etched when the polycrystalline silicon layer for the storage electrode is etched. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR93017581A 1993-09-03 1993-09-03 Method for manufacturing a dram cell for semiconductor device KR970008811B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487514B1 (en) * 1998-07-28 2005-09-02 삼성전자주식회사 Semiconductor device and method of fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487514B1 (en) * 1998-07-28 2005-09-02 삼성전자주식회사 Semiconductor device and method of fabricating the same

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